MICRONAS Edition Nov. 7, 2001 6251-522-1DS MAS 3504D G.729 Annex A Voice Codec MICRONAS MAS 3504D Contents Page Section Title 4 4 5 5 5 1. 1.1. 1.2. 1.2.1. 1.2.2. Introduction Features Application Overview Decoder Mode Encoder Mode 6 6 6 6 6 6 6 6 6 7 7 8 8 8 8 9 9 10 10 10 11 11 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.4. 2.6.5. 2.6.5.1. 2.6.5.2. Functional Description of the MAS 3504D DSP Core Firmware (Internal Program ROM) G.729 Encoder G.729 Decoder Program Download Feature Clock Management Power Supply Concept Internal Voltage Monitor DC/DC Converter Stand-by Functions Start-up Sequence Interfaces Parallel Input Output Interface (PIO) Parallel Data Output Parallel Data Input DMA Handshake Protocol End of DMA Transfer Audio Input Interface (SDI) Audio Output Interface (SDO) Example 1:16 Bits/Sample (I2S Compatible Data Format) Example 2:32 Bit/Sample (Inverted SOI) 12 12 12 13 13 14 14 14 14 14 15 15 15 16 16 16 16 17 3. 3.1. 3.1.1. 3.2. 3.2.1. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.3.6. 3.3.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.2.1. Control Interfaces I2C Bus Interface Device address and Subaddresses Command Structure Conventions for the Command Description Detailed MAS 3504D Command Syntax Run Write Register Write D0 Memory Write D1 Memory Read Register Read D0 Memory Read D1 Memory Version Number Register Table DC/DC Converter (Reg. 8Ehex) User Control (Reg. FDhex) Data Transmission Format 2 Micronas MAS 3504D Contents, continued Page Section Title 17 17 18 18 18 18 18 18 18 3.5.2.2. 3.5.2.3. 3.5.2.4. 3.5.3. 3.5.4. 3.5.4.1. 3.5.4.2. 3.5.4.3. 3.5.5. Encoder Operation Decoder Operation Pause and Mute Volume Control (Reg. FChex) Interface Control Wordlength Control (Reg. 74hex) Input Configuration (Reg. 61hex) Output Configuration (Reg. E1hex) Hardware Control (Reg. FAhex) 22 22 23 25 25 25 25 25 25 25 26 26 26 26 26 27 28 28 29 30 31 32 33 34 36 4. 4.1. 4.2. 4.2.1. 4.2.1.1. 4.2.1.2. 4.2.1.3. 4.2.1.4. 4.2.1.4.1. 4.2.1.4.2. 4.2.1.5. 4.2.1.6. 4.2.1.7. 4.2.1.8. 4.2.2. 4.2.3. 4.2.4. 4.2.4.1. 4.2.4.2. 4.2.4.3. 4.2.4.3.1. 4.2.4.3.2. 4.2.4.3.3. 4.2.4.4. 4.2.4.5. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins DC/DC Converter Pins Control Lines Parallel Interface Lines PIO Handshake Lines PIO Data Lines Voltage Supervision And Other Functions Serial Input Interface Serial Output Interface Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics I2C Characteristics I2S Bus Characteristics – SDI I2S Characteristics – SDO DC/DC Converter Characteristics Typical Performance Characteristics 40 5. Data Sheet History License Notice Supply of this implementation of G.729A technology does not convey a license nor imply any right to use this implementation in any finished end-user or ready-to-use final product. An independant license for such use is required. For information on such license agreement please contact: Sipro Lab Telecom Inc. email: [email protected] http://www.sipro.com Fax: +1 (514) 737-2327 Micronas 3 MAS 3504D G.729 Annex A Voice Codec 1.1. Features – Single-chip G.729 decoder 1. Introduction – G.729 Annex A encoder The MAS 3504D is a single-chip codec for use in memory-based voice recording and playback applications. Due to embedded memories, the embedded DC/ DC up-converter, and the very low power consumption, the MAS 3504D is ideally suited for portable electronics. The MAS 3504D implements a voice encoder and decoder that is compliant to the ITU Standard G.729 Annex A. This standard works on 8 kHz, 16 bit, mono audio data that is compressed to 1 bit per audio sample. One second of compressed audio data uses 1000 bytes of memory. – ITU compliance tests passed – Parallel input and parallel output of coded bitstream data – Input audio data read from an I2S bus (in various formats) – Output audio data delivered via an I2S bus (in various formats) – Digital volume / mute – Low power dissipation (150 mW for encoder, 80 mW for decoder @ 3.3 V) – Supply voltage range: 1.0 V to 3.6 V due to built-in DC/DC converter (1-cell battery operation) – Adjustable power supply supervision – Power-off function – Additional functionality achievable via download software (ADPCM encoder/decoder) CLKI decoded output /3/ voice audio data /3/ Clock Synthesizer MAS 3504D DC/DC Converter Serial Out I2S RISC DSP Core PIO Serial In /3/ parallel I/O I2C /8+5/ serial control /2/ Fig. 1–1: MAS 3504D block diagram 4 Micronas MAS 3504D 1.2. Application Overview A delayed response of the host to the request signal (max. 20 milliseconds) will be tolerated by the MAS 3504D as long as the input buffer does not run empty. A PC might use its DMA capabilities to transfer the data in the background to the MAS 3504D without interfering with its foreground processes. The MAS 3504D can be applied in two major environments: as standalone decoder or as encoder/decoder combination. For decoding only mode, the DAC 3550A fits perfectly to the requirements of the MAS 3504D. It is a high-quality multi sample rate DAC (8 kHz.. 50 kHz) with internal crystal oscillator, which is only needed for generating the decoder Clock, and integrated stereo headphone amplifier plus two stereo inputs. The source of the bit stream may be a memory (e.g. ROM, Flash) or PC peripherals, such as CD-ROM drive, a hard disk or a floppy disk drive. 1.2.2. Encoder Mode 1.2.1. Decoder Mode For encoding a support routine must be downloaded to the MAS 3504D via I2C. After the encoder is started, it begins to encode the incoming audio data and writes the coded datastream to the parallel (PIO) interface. In a memory-based voice playback environment, the decoding is started with a command from a controller. Then the MAS 3504D continuously requests frames of G.729 data every 10 ms via the parallel (PIO) interface. A delayed response of the host to the data available signal (max. 20 milliseconds) will be tolerated by the MAS 3504D as long as the output buffer does not overrun. I2C Host (PC, Controller) 18.432 MHz demand signal demand clock I2S MAS 3504D line out DAC 3550A G.729 bit stream CLKI ROM, CD-ROM, RAM, Flash Mem. .. CLKOUT Fig. 1–2: Block diagram of a MAS 3504D, decoding a stored bit stream in a decoding only application I2C Host (PC, Controller) Handshake signals G.729 bit stream data in data out MAS 3504D strobe clock AD/DA line in Mic in line out PLL I2S lines CLKI ROM, CD-ROM, RAM, Flash Mem. .. Fig. 1–3: Block diagram of a MAS 3504D in an encoding/decoding application Micronas 5 MAS 3504D 2. Functional Description 2.3. Program Download Feature 2.1. DSP Core The overall function of the MAS 3504D can be altered by downloading up to 1 kWord program code into the internal RAM and by executing this code instead of the ROM code. During this time, G.729 processing is not possible. The hardware of the MAS 3504D consists of a high performance Digital Signal Processor and appropriate interfaces. The processor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. The instruction set of the DSP is highly optimized for audio data compression and decompression. Thus, only very small areas of internal RAM and ROM are required. All data input and output actions are based on a ‘non cycle stealing’ background DMA that does not cause any computational overhead. 2.2. Firmware (Internal Program ROM) The firmware fully contains a G.729 voice decoder. With an additional support routine the IC is extended to a G.729 Annex A encoder. The code must be downloaded by the ‘write to memory’ command (see Section 3.3. on page 14) into an area of internal RAM. A ‘run’ command starts the operation. Micronas provides modules for encoding and decoding audio data with ADPCM. Detailed information about downloading is provided in combination with the MAS 3504D software development package from Micronas. 2.4. Clock Management The G.729 standard compresses 8 kHz/16 bit mono voice data in frames of 80 samples to 10 bytes each, what results in a compressed bitstream of 1 bit/sample. The encoding according to Annex A has reduced complexity, but is fully compatible to the initial G.729 standard. Therefore the MAS 3504D can decode bitstreams that were encoded by other G.729 encoders and it can encode bitstreams that can be decoded with other G.729 decoders. The MAS 3504D should be driven by a single clock at a frequency of 18.432 MHz. The CLKI signal acts as a reference for the embedded clock synthesizer that generates the internal system clock. 2.5. Power Supply Concept 2.2.1. G.729 Encoder For encoding operation the MAS 3504D has to be prepared by downloading an additional routine to support the encoder. After starting the encoder, 80 audio samples are continuously read via the serial input interface. Each audio block of 80 samples is encoded to a G.729 data frame consisting of 10 bytes which is sent via the parallel interface. It is possible to monitor the input audio samples also directly via the serial output interface. 2.2.2. G.729 Decoder The MAS 3504D expects a sequence of valid G.729 frames (10 bytes each) as input. The compressed data is sent via the parallel interface. Each frame is decoded to 80 audio samples, modified by the volume/ mute control and sent out via the serial output interface. 6 The MAS 3504D offers an embedded controlled DC/ DC converter and voltage monitoring circuits for battery based power supply concepts. It works as an upconverter. The application circuit for the DC/DC converter is shown in Fig. 2–1. 2.5.1. Internal Voltage Monitor An internal voltage monitor compares the input voltage at the VSENS pin with an internal reference value that is adjustable via I2C bus. The PUP output pin becomes inactive when the voltage at the VSENS pin drops below the programmed value of the reference voltage. It is important that the WSEN must not be activated before the PUP is generated. The PUP signal thresholds are listed in Table 3–8 on page 19. Micronas MAS 3504D 2.5.2. DC/DC Converter 2.5.3. Stand-by Functions The DC/DC converter of the MAS 3504D is used to generate a fixed power supply voltage even if the chip is powered by battery cells in portable applications. The DC/DC converter is designed for the application of 1 or 2 batteries or NiCd cells. The DC/DC converter is switched on by activating the DCEN pin. Its output power is sufficient for other ICs as well. The digital part of the MAS 3504D and the DC/DC converter are turned on by setting WSEN. If only the DC/ DC converter should work, it can remain active bysetting DCEN alone to supply other parts of the application even if the audio decoding part of the MAS 3504D is not being used. The WSEN power-up pin of the digital part should be handled by the controller. A 22 µH inductor is required for the application. The important specification item is the inductor saturation current rating, which should be greater than 2.5 times the DC load current. The DC resistance of the inductor is important for efficiency. The primary criterion for selecting the output filter capacitor is low equivalent series resistance (ESR), as the product of the inductor current variation and the ESR determines the high-frequency amplitude seen on the output voltage. The Schottky diode should have a low voltage drop VD for a high overall efficiency of the DC/DC converter. The current rating of the diode should also be greater than 2.5 times the DC output current. The VSENS pin is always connected to the output voltage at the low ESR capacitor. Please pay attention to the fact, that the I2C interface is working only if the processor is powered up (WSEN = 1). CLKI VDD optional filter AVDD 22 µH DCSO Start-up oscillator DCSG + − DC/DC converter Start-up divider 64...94 x2 DCEN 32...47 voltage monitor +32 DCCF 8ehex 9 10 0...15 Power-On Push Button PUP COUT 330 µF Low ESR + CIN 330 µF VIN ≥ 0.9 V − 10 kΩ WSEN VSENSE 16 VSS AVSS 10 nF 47 kΩ 47 kΩ µController Fig. 2–1: DC/DC converter connections Micronas 7 MAS 3504D 2.5.4. Start-up Sequence The DC/DC converter starts from a minimum input voltage of 0.9 V. There should be no output load during startup. In case WSEN is active, the MAS 3504D is in the DSP operation mode. The start-up script should be as follows: 1. Enable the DC/DC-converter with a high signal (VDD, AVDD) at pin DCEN. µController DSP operation =1 WSEN > 2 V 2. Wait until PUP goes “high”. 3. Wait one more millisecond to guarantee that the output voltage has settled (recommended). 4. Enable the MAS 3504D with a “high” signal at pin “WSEN”. DC/DC On > 0.9 V DCEN button Fig. 2–2: DC/DC startup Please also refer to Figure 2–2. 2.6.2. Parallel Data Output 2.6. Interfaces The MAS 3504D uses an I2C control interface, a parallel I/O interface (PIO) for G.729- or ADPCM-data, a digital audio input interface (SDI) for audio data input and a digital audio output interface (SDO) for the decoded audio data (I2S or similar). The G.729 bit stream generated by an encoder is aligned in frames of 10 bytes. The parallel data required from the G.729 decoder must be sent in byteswapped order related to the standard specification. The G.729 encoder also sends the encoded bit stream byte-swapped to the PIO interface. 2.6.1. Parallel Input Output Interface (PIO) The parallel interface of the MAS 3504D consists of the lines PI0...PI4, PI8, PI12...PI19, and several control lines. t0 t1 t2 In encoding mode, PIO lines PI12...PI19 are switched to the MAS 3504D data output which hence will be an 8-bit parallel output port with MSB first (at position PI19) for the G.729 bit stream data. The data is transferred in bursts of 10 bytes (1 frame) each 10 ms. If the transmission of headers is enabled, there is an additional 10 byte burst before each sequence of 50 frames. Handshaking for PIO output mode is accomplished through the RTW, PCS, and PI12..PI19 signal lines (see Fig. 2–3). The PR line has to be set to high level. RTW will go low as soon as a byte is available in the output buffer and will stay low until a byte has been read. Reading of a byte is performed with a PCS pulse. Data is latched out from the MAS 3504D on the falling edge of PCS and removed from the bus on the rising edge of PCS. t3 RTW PIxx t4 t5 PCS Fig. 2–3: Parallel Data Output (PIO) Timing 8 Micronas MAS 3504D Table 2–1: PIO Output Mode Timing1) 1) 2.6.3. Parallel Data Input Symbol Pin Name Min. Max. Unit t0 RTW, PCS 0.010 1800 µs t1 PCS 0.330 µs t2 PCS, RTW 0.010 µs t3 RTW 0.330 t4 PI 0.330 µs t5 PI 0.081 µs 10000 see Figure 2–3 tst tr trtrq µs In decoding mode, PIO lines PI12...PI19 are switched to the MAS 3504D data input which hence will be an 8bit parallel input port with MSB first (at position PI19) for the G.729 bit stream data. In order to write data to this parallel port, a special handshake protocol has to be used by the controller (see Fig. 2–4). 2.6.3.1. DMA Handshake Protocol The data transfer can be started after the EOD pin of the MAS 3504D is set to high. After verifying this, the controller indicates the transmission of data by activating the PR line. The MAS 3504D responds by setting the RTR line to the low level. The MAS 3504D reads the data PI[19:12] after the rising edge of the PR. The next data word write operation will again be initialized by setting the PR line via the controller. Please refer to Figure 2–4 and Table 2–2 for the exact timing. trpr teod teodq tpd high low EOD high PR tpr low high RTR PI[19:12] low tset th high low Byte 1 Byte 15 MAS 3504D latches the PIO DATA Fig. 2–4: Handshake protocol for writing G.729 data to the PIO-DMA Micronas 9 MAS 3504D 2.6.3.2. End of DMA Transfer 2.6.4. Audio Input Interface (SDI) The above procedure will be repeated until the MAS 3504D sets the EOD signal to “0”, which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to “0”, wait until EOD rises again, and then repeat the procedure ((see Section 2.6.3.1. on page 9)) to send the next block of data. The DMA buffer is 10 bytes long (one frame). The A/D interface is a standard I2S interface (16/32 bit, stereo). This input is used for G.729 recording mode and must be slaved to the D/A output clock and wordstrobe signals. The recommended PIO DMA conditions and the characteristics of the PIO timing are given in Table 2–2. – no delay or delay of data related to word strobe The interface is configurable by software to work in different modes. It is possible to choose: – inverted or non inverted word strobe (SOI), – inverted or non inverted I2S-Clock (SOC). For further details see Section 3.5.4. on page 18 Table 2–2: PIO DMA Timing 2.6.5. Audio Output Interface (SDO) Symbol PIO Pin Min. Max. Unit tst PR, EOD 0.010 2000 µs tr PR, RTR 40 160 ns tpd PR, PI[19:12] 120 480 ns tset PI[19:12] 160 no limit ns th PI[19:12] 160 no limit ns – inverted or non inverted word strobe (SOI), trtrq RTR 200 30000 ns – no delay or delay of data related to word strobe tpr PR 480 no limit ns trpr PR, RTR 40 no limit ns teod PR, EOD 40 160 ns teodq EOD 2.5 500 µs 10 The audio output interface of the MAS 3504D is a standard I2S interface. As the G.729 standard is only working on mono signals, the same signal is written to both output channels (left and right). The interface is configurable by software to work in different modes. It is possible to choose: – 16 or 32 bit/sample modes, – inverted or non inverted I2S-clock (SOC). For further details see Section 3.5.4. on page 18 Micronas MAS 3504D 2.6.5.1. Example 1:16 Bits/Sample (I2S Compatible Data Format) A schematic timing diagram of the SDO interface in 16 bit/sample mode with delayed data by 1 clock cycle is shown in Fig. 2–5. Vh SOC Vl Vh SOD V l SOI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vh Vl left 16-bit audio sample right 16-bit audio sample Fig. 2–5: Schematic timing of the SDO interface in 16bit/sample mode 2.6.5.2. Example 2:32 Bit/Sample (Inverted SOI) If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default (see Fig. 2–6). SOC SOD Vh ... ... Vl Vh Vl 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 Vh SOI Vl left 32-bit audio sample right 32-bit audio sample Fig. 2–6: Schematic timing of the SDO interface in 32 bit/sample mode Micronas 11 MAS 3504D 3. Control Interfaces 3.1. I2C Bus Interface The MAS 3504D is controlled via the I2C bus slave interface. 3.1.1. Device Address and Subaddresses The IC is selected by transmitting the MAS 3504D device addresses. (see Table 3–1). Writing is done by sending the device write address, (3Ahex) followed by the subaddress byte (68hex) and two or more bytes of data. Reading is done by sending the write device address (3Ahex), followed by the subaddress byte (69hex). Without sending a stop condition, reading of the addressed data is completed by sending the device read address (3Bhex) and reading n-bytes of data. By means of the RESET bit in the CONTROL register, the MAS 3504D can be reset by the controller. Due to the internal architecture of the MAS 3504D, the IC cannot react immediately to an I2C request. The typical response time is about 0.5 ms. If the MAS 3504D cannot accept another complete byte of data, it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by ’Wait’ in Section 3.3. on page 14. The maximum wait period of the MAS 3504D during normal operation mode is less than 4 ms. Table 3–1: I2C Bus Device Addresses MAS 3504D device address Write Read MAS_I2C_ADR 3Ahex 3Bhex Table 3–2: Control Register (Subaddress: 6Ahex) Name Subaddress Bit [8] Bit : 0-7, 9-15 CONTROL 6Ahex 1 : Reset 0 : normal 0 Table 3–3: I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL_MAS 0110 1010 6Ahex Write control subaddress (see Table 3–2) WR_MAS 0110 1000 68hex Write write subaddress RD_MAS 0110 1001 69hex Write read subaddress 1 0 I2C_DA S P I2C_CL Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high) Note: S = P= A= N= Wait = 12 I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave or master Not Acknowledge-Bit: HIGH on I2C_DA from master to indicate ‘End of Read’ I2C-Clock line is held low, while the MAS 3504D is processing the I2C command. This waiting time is max. 1 ms Micronas MAS 3504D 3.2. Command Structure 3.2.1. Conventions for the Command Description The I2C control of the MAS 3504D is done completely via the I2C data register by using a special command syntax. The commands are executed by the MAS 3504D during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. These I2C commands allow the controller to access internal states, RAM contents, internal hardware control registers, and to download software modules. The command structure allows sophisticated control of the MAS 3504D. The registers of the MAS 3504D are either general purpose, e.g. for program flow control, or specialized registers that directly affect hardware blocks. The unrestricted access to these registers allows the system controller to overrule the firmware configuration. The description of the various controller commands uses the following formalism: The MAS 3504D firmware scans the I2C interface periodically and checks for pending or new commands. Table 3–4 on page 13 shows the basic controller commands that are available by the MAS 3504D. – A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. – Data values in nibbles are always shown in hexadecimal notation indicated by a preceding $. – A hexadecimal 20-bit number d is written, e.g. as d = $17C63, its five nibbles are d0 = $3, d1 = $6, d2 = $C, d3 = $7, and d4 = $1. – Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don’t care – Variables used in the following descriptions: dev_write $3A dev_read $3B data_write $68 data_read $69 Table 3–4: Basic Controller Commands Code [hex] Command Comment 0 1 run Start execution of an internal program. (Run 0 means freeze operating system.) 9 write register An internal register of the MAS 3504D can be written directly to by the controller. A B write to memory A block of the DSP memory can be written to by the controller. This feature may be used to download alternate programs. D read register The controller can read an internal register of the MAS 3504D. E F read memory A block of the DSP memory can be read by the controller. Micronas 13 MAS 3504D 3.3. Detailed MAS 3504D Command Syntax 3.3.3. Write D0 Memory 3.3.1. Run S S DW W A data_write A a3,a2 A a1,a0 W A Example: ‘run’ at address 1hex (start of G.729 decoder) has the following I2C protocol: A data_write A A,0 A $0,$0 W A n3,n2 A n1,n0 W A a3,a2 A a1,a0 W A d3,d2 A d1,d0 W A $0,$0 A $0,d4 W ....repeat for n data values.... A d3,d2 A d1,d0 W A $0,$0 A $0,d4 W A P n3..n0: number of words to be transmitted a3..a0: start address in MASD memory d4..d0: data value The MAS 3504D has 2 memory areas of 2048 words each called D0 and D1 memory. For both memory areas, read and write commands are provided. <$3A><$68><$A0><$00> (write D0 memory) <$00><$01> (1 word to write) <$03><$21> (start address) <$23><$45> (value = 12345hex) <$00><$01> 3.3.2. Write Register W A data_write A Example: writing one word to address d0:0321hex has the following I2C protocol: <$3A><$68><$00><$01> DW W P The ‘run’ command causes the start of a program part at address a = (a3, a2, a1, a0). The nibble a3 is restricted to 0hex or 1hex which also acts as command selector. Run with address a = 0hex will suspend the encoding/decoding function and only I2C commands are evaluated. This freezing is required if alternative software is downloaded into the internal RAM of the MAS 3504D. Detailed information about downloading is provided in combination with a MAS 3504D software development package or together with MAS 3504D software modules available from Micronas. S DW 9,r1 A r0,d4 W A d4,d3 A d2,d1 W A P 3.3.4. Write D1 Memory The controller writes the 20-bit value (d = d4, d3, d2, d1, d0) into the MAS 3504D register (r = r1,r0). In contrast to memory cells, registers are always addressed individually, and they may also interact with built-in hardware blocks. A list of registers is given in Section 3.5. on page 16 Example: G.729 decoding is started by writing the value 1 into the register with the number FDhex: <$3A><$68><$9F><$D1><$00><$00> S DW W A data_write A B,0 A $0,$0 W A n3,n2 A n1,n0 W A a3,a2 A a1,a0 W A d3,d2 A d1,d0 W A $0,$0 A $0,d4 W ....repeat for n data values.... A d3,d2 A d1,d0 W A $0,$0 A $0,d4 W A P n3..n0: number of words to be transmitted a3..a0: start address in MASD memory d4..d0: data value For further details, see ‘write D0 memory’ command. 14 Micronas MAS 3504D 3.3.5. Read Register 3.3.7. Read D1 Memory 1) send command 1) send command S DW W A data_write A D,r1 A r0,$0 W A P S DW W A data_write A 2) get register value S DW A W d3,d2 A data_read A S DR W A W x,x A d1,d0 A A x,d4 W N P A $0,$0 W A n3,n2 A n1,n0 W A a3,a2 A a1,a0 W A P 2) get memory value S r1, r0: register r d3..d0: data value in r x: don’t care F,$0 DW A W d3,d2 A data_read A S DR W W A $0,$0 A $0,d4 W A $0,$0 A $0,d4 W A d1,d0 ....repeat for n data values.... The MAS 3504D has an address space of 256 registers. Some of the registers (r = r1, r0 in the figure above) are direct control inputs for various hardware blocks, others do control the internal program flow. In the next section, those registers that are of any interest with respect to the G.729 codec are described in detail. Example: Read the content of the PIO data register (C8hex): A d3,d2 A d1,d0 W N P n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value The ‘read D1 memory’ command is provided to get information from memory cells of the MAS 3504D. It gives the controller access to all memory cells of the internal D1 memory. <$3A><$68><$DC><$80> <$3A><$69><$3B> now read: <d3,d2><d1,d0><x,x><x,d4> 3.3.6. Read D0 Memory 1) send command S DW W A data_write A E,$0 A 0$,$0 W A n3,n2 A n1,n0 W A a3,a2 A a1,a0 W A P 2) get memory value S DW A W d3,d2 A data_read A S DR W W A $0,$0 A $0,d4 W A $0,$0 A $0,d4 W A d1,d0 ....repeat for n data values.... A d3,d2 A d1,d0 W N P n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value The ‘read D0 memory’ command is provided to get information from memory cells of the MAS 3504D. It gives the controller access to all memory cells of the internal D0 memory. Direct access to memory cells is an advanced feature of the DSP. It is intended for users of the MASC software development kit. Micronas 15 MAS 3504D 3.4. Version Number system crash of the decoder operation which can only be restored by a reset. Table 3–5 shows where the chip identification and the name of the software is located. 3.5.1. DC/DC Converter (Reg. 8Ehex) Table 3–5: MAS 3504D Version Addr. [hex] Content Example Value D1:FF6 name of MAS 3504D version 0x03504 3504 D1:FF9 description: “G.729a CODEC” 0x0472e G. D1:FFA 0x03732 72 D1:FFB 0x03961 9A D1:FFC 0x02043 C D1:FFD 0x04f44 OD D1:FFE 0x04543 EC D1:FFF 0x02020 3.5. Register Table In Table 3–6, the internal registers for controlling the MAS 3504D are listed. They are accessible by ‘register read/write’ I2C commands (see Section 3.3. on page 14). For a more detailed register usage (see Table 3–8 on page 19). Important note! Writing into undocumented registers or read-only registers is always possible, but it is highly recommended not to do so. It may damage the function of the firmware and may even lead to a complete 16 The DCCF Register controls both, the internal voltage monitor and the DC/DC converter. Between output voltage of the DC/DC converter and the internal voltage monitor threshold an offset exists which is shown in Table 3–8 on page 19. Please pay attention to the fact, that I2C protocol is working only if the processor works (WSEN = 1).However, the setting for the DCCF register will remain active if the DCEN and WSEN lines are deasserted. The DC/DC converter may generate interference noise that could be unacceptable for some applications. Thus the oscillator frequency may be adjusted in 32 steps in order to allow the system controller to select a base frequency that does not interfere with an other application. The CLKI input provides the base clock fCLKI for the frequency divider whose output is made symmetrical with an additional divider by two. The divider quotient is determined by the content of the DCCF register. This register allows 32 settings generating a DC/DC converter clock frequency fdc between: f CLKI f SW = -----------------------2 ⋅ (m + n) n ∈ {0, 15} , m ∈ {32, 16} (EQ 1) 3.5.2. User Control (Reg. FDhex) The UserControl register is used to switch between basic operation modes. On startup, after a software reset or a “run 1” command it is set to 0hex. The MAS 3504D sets the control registers to default values, switches off all interfaces (except I2C) and waits for a change in UserControl. Micronas MAS 3504D Table 3–6: Command Register Table Address (hex) Mode Function Default (hex) Name 8E w DC/DC operation control 8000 DCCF FD r/w Operation mode selection 0 UserControl FC r/w Output volume 7FFFF Volume 74 r/w Serial interface wordlength 0 Wordlength E1 r/w Configuration of the I2S audio input interface 4 InputConfig 61 r/w Configuration of the I2S audio output interface 4000 OutputConfig FA r/w Special operation options 0 HWControl 3.5.2.1. Data Transmission Format The codec is working on a page basis. That means, that encoding and decoding is performed in blocks of 50 G.729 frames, whereas each frame consists of 10 bytes in byte swapped order (see Fig. 3–2). Therefore most changes to the UserControl register become effective when processing of a page is finished. The pages are optionally preceeded by 10 byte header frames (see Table 3–7). To switch to encoder operation mode, UserControl has to be set to 3hex. Then 50 frames are encoded and sent via the PIO interface. This is repeated until the UserControl register is changed. If the transmission of headers is enabled, each page of 50 frames is preceeded by a header frame as shown in Table 3–7. To switch off the encoder, UserControl has to be set to 0hex. Then the encoding and sending of frames continues until the end of the current page and the operation mode is set to stop. Table 3–7: Content of Page Header 3.5.2.3. Decoder Operation Byte 1 2 3 4 5 6 7 8 9 10 Value 64 6D 72 31 64 61 74 61 F4 01 [hex] Switching from encoding to decoding mode or vice versa directly is not allowed. Instead the controller has to send a stop request to the MAS 3504D (writing 0hex to UserControl). Then the controller has to keep on sending data in decoding mode or receive data in encoding mode until the current page of 50 frames is finished. After this run out time, the encoding or decoding can be started again. 3.5.2.2. Encoder Operation To enable the G.729 encoder mode, a special routine has to be downloaded to the MAS 3504D IC first. This has to be done with an I2C download before the encoder is started the first time. If the encoder is started without downloading the routine, the behavior of the IC is unpredictable. Micronas The routines for the G.729 decoder mode are completely located in the MAS 3504D firmware. So there is no need to download the encoder routine in a decode only application. To switch to decoder operation mode, UserControl has to be set to 1hex. For decoding with slow speed, set UserControl to 11hex. For decoding with fast speed, set UserControl to 21hex. Then the decoder is requesting several frames via the PIO interface to fill its internal buffer. If enough data is available, 50 frames are decoded. This is repeated until the UserControl register is changed. If the transmission of headers is enabled, a header frame (as shown in Table 3–7) has to be sent before each page of 50 frames. To switch off the decoder, UserControl has to be set to 0hex. Then the decoding of frames continues until the end of the current page and the operation mode is set to stop. 17 MAS 3504D 3.5.2.4. Pause and Mute 3.5.4.2. Input Configuration (Reg. 61hex) If the pause bit is set, the processing continues until the current page is finished and then en-/decoding is paused. The pause mode lasts until the pause bit is cleared again or the mode is set to 0. The content of this register is set on startup by the firmware. Additional to the Wordlength setting for the serial interfaces, some other settings can be made. If the mute bit is set, the output is muted immediately. 3.5.4.3. Output Configuration (Reg. E1hex) Note that the other bits of the UserControl register have to stay on their old values when switching to pause mode. The content of this register is set on startup by the firmware. Additional to the Wordlength setting for the serial interfaces, some other settings can be made. 3.5.3. Volume Control (Reg. FChex) 3.5.5. Hardware Control (Reg. FAhex) Volume control is implemented in the MAS 3504D. It allows to adjust the output volume linear from 0hex (silence) to 7FFFFhex (original volume). The HWControl register is used to set special operation options. If the page headers bit is 0, a header frame is transferred in front of each page of 50 data frames. If the header bit is 1, all the frames are G.729 data frames. 3.5.4. Interface Control All the interface control registers have to be written before the encoder or decoder is started by writing to the UserControl register. Otherwise they have no effect until the operation mode is changed. Bits 2 and 1 are used to select input channels for encoding. If both bits are set to 0, the left and right channel are added to get the mono input signal. If only one of this bits is 1, only the corresponding channel is used as input. 3.5.4.1. Wordlength Control (Reg. 74hex) A value of 0hex sets wordlength on SDI and SDO interfaces to 32 bit. 1hex sets wordlength to 16 bit. page frame frame frame header 1 2 3 ... frame frame page frame frame 49 49 header 51 52 ... frame frame page frame frame 99 100 header 101 102 ... ... 10ms 10ms ... $64 $6d $72 $31 $64 $61 $74 $61 $f4 $01 byte byte byte byte byte byte byte byte byte byte 2 1 4 3 6 7 10 9 5 8 Fig. 3–2: Schematic timing of the data transmission with preceeding header 18 Micronas MAS 3504D Table 3–8: Detailed Register Usage Address (hex) Mode Function Default (hex) Name 61 r/w Configuration of the I2S audio input interface 4 InputConfig 0 Wordlength 74 Micronas r/w bit[19:12] not used, set to 0 bit[11] additional delay of data related to word strobe 0 no delay 1 1 bit delay bit[10:6] not used, set to 0 bit[5] input word strobe signal 0 standard timing 1 inverted timing bit[4:3] not used, set to 0 bit[2] input clock signal 0 standard timing 1 inverted timing bit[1:0] not used, set to 0 Serial output interface wordlength bit[19:1] not used, set to 0 bit[0] wordlength 0 32 bit/sample 1 16 bit/sample 19 MAS 3504D Table 3–8: Detailed Register Usage, continued Address (hex) Mode Function Default (hex) Name 8E w DC/DC operation control 8000 DCCF bit[19:17] not used, set to 0 bit[16:14,9] output voltage / internal voltage monitor (PUP signal becomes inactive when output is below the monitoring voltage) Setting bit [16:14] and [9] DC/DC-Converter Output Voltage [V] Internal Monitor Voltage [V] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 3.57 3.46 3.35 3.25 3.14 3.04 2.94 2.83 2.73 2.63 2.52 2.42 2.32 2.22 2.12 2.02 3.38 3.27 3.16 3.06 2.95 2.85 2.75 2.64 2.54 2.44 2.33 2.23 2.13 2.03 1.93 1.82 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 bit[13:10,8] DC/DC-converter switching frequency fSW [kHz] Setting bit [13:10] Frequency/kHz bit [8] = 0 Frequency/kHz bit [8] = 1 11 11 11 11 10 10 10 10 01 01 01 01 00 00 00 00 156 160 163 167 171 175 179 184 188 194 199 204 210 216 223 230 128 245 253 263 272 283 295 307 320 335 351 368 387 409 433 460 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 bit[7:0] 20 not used, set to 0 Micronas MAS 3504D Table 3–8: Detailed Register Usage, continued Address (hex) Mode Function Default (hex) Name E1 r/w Configuration of the I2S audio output interface 4000 OutputConfig 0 HWControl 7FFFF Volume 0 UserControl FA FC r/w r/w bit[19:15] not used, set to 0 bit[14] output clock signal 0 standard timing 1 inverted timing bit[13:12] not used, set to 0 bit[11] additional delay of data related to word strobe 0 no delay 1 1 bit delay bit[10:6] not used, set to 0 bit[5] output word strobe signal 0 standard timing 1 inverted timing bit[4:0] not used, set to 0 Special operation options bit[19:3] not used, set to 0 bit[2:1] input channel matrixing 00 add left/right channel 01 input only from right channel 10 input only from left channel 11 not allowed bit[0] page headers 0 enable 1 disable Output volume bit[19:0] FD Micronas r/w linear volume level Operation mode selection bit[19:6] not used, set to 0 bit[5:4] decoding speed 00 8 kHz (normal) 01 6 kHz (slow) 10 12 kHz (fast) 11 not allowed bit[3] mute audio output 0 disable 1 enable bit[2] pause encoder/decoder 0 disable 1 enable bit[1:0] mode 00 01 10 11 idle decode not allowed encode 21 MAS 3504D 4. Specifications 4.1. Outline Dimensions 10 x 0.8 = 8 ± 0.1 0.17 ± 0.06 0.8 23 10 ± 0.1 0.34 ± 0.05 13.2 ± 0.2 12 44 0.8 22 34 10 x 0.8 = 8 ± 0.1 33 1 11 2.0 ± 0.1 13.2 ± 0.2 2.15 ± 0.2 10 ± 0.1 0.1 SPGS706000-5(P44)/1E Fig. 4–1: Plastic Metric Quad Flat Pack 44-Pin (PMQFP44) Weight approximately 0.4 g Dimensions in mm A1 Ball Pad Corner 7 6 5 4 3 1.4 Laser marked pin 1 0.36 2 1 A C 0.8 D E F ∅ 0.46 7 6 x 0.8 = 4.8 B G 0.8 6 x 0.8 = 4.8 7 SPGS708000-1(P49)/1E Fig. 4–2: Low-Profile Fine-Pitch Ball Grid Array 49-Pin (LFBGA49) Weight approximately 0.13 g Dimensions in mm 22 Micronas MAS 3504D 4.2. Pin Connections and Short Descriptions NC LV X not connected, leave vacant If not used, leave vacant obligatory, pin must be connected as described in application information VDD connect to positive supply VSS connect to ground Pin No. Pin Name Type Connection Short Description PMQFP 44-pin LFBGA 49-ball Test Alias in () 1 C3 TE IN VSS Test Enable 2 C2 POR IN X Reset, Active Low 3 B1 I2CC IN/OUT X I2C Clock Line 4 D2 I2CD IN/OUT X I2C Data Line 5 C1 VDD SUPPLY X Positive Supply for Digital Parts 6 D1 VSS SUPPLY X Ground Supply for Digital Parts 7 E2 DCEN IN VSS Enable DC/DC Converter 8 E1 EOD OUT LV PIO End of DMA, Active Low 9 F2 RTR OUT LV PIO Ready to Read, Active Low 10 F1 RTW OUT LV PIO Ready to Write, Active Low 11 G1 DCSG SUPPLY VSS DC Converter Transistor Ground 12 E3 DCSO OUT VSS DC Converter Transistor Open Drain 13 F3 VSENS IN VDD DC Converter Voltage Sense 14 G2 PR IN X PIO-DMA Request or Read/Write 15 F4 PCS IN X PIO Chip Select, Active Low 16 G3 PI19 IN/OUT LV PIO Data [19] data bit [7], MSB 17 E4 PI18 IN/OUT LV PIO Data [18] data bit [6] 18 G4 PI17 IN/OUT LV PIO Data [17] data bit [5] 19 F5 PI16 IN/OUT LV PIO Data [16] data bit [4] 20 G5 PI15 IN/OUT LV PIO Data [15] data bit [3] 21 F6 PI14 IN/OUT LV PIO Data [14] data bit [2] 22 G6 PI13 IN/OUT LV PIO Data [13] data bit [1] 23 E5 PI12 IN/OUT LV PIO Data [12] data bit [0] 24 E6 SOD (PI11) OUT LV Serial Output Data 25 F7 SOI (PI10) OUT LV Serial Output Frame Identification 26 D6 SOC (PI9) OUT LV Serial Output Clock Micronas (If not used) 23 MAS 3504D Pin No. Pin Name Type Connection Short Description PMQFP 44-pin LFBGA 49-ball Test Alias in () 27 E7 PI8 IN LV Not used 28 D7 XVDD SUPPLY X Positive Supply of Output Buffers 29 C6 XVSS SUPPLY X Ground of Output Buffers 30 C7 SID (PI7) IN VSS Serial Input Data 31 B6 SII (PI6) IN VSS Serial Input Frame Identification 32 B7 SIC (PI5) IN VSS Serial Input Clock 33 A7 PI4 IN LV Not used 34 B5 PI3 IN LV Not used 35 A6 PI2 IN LV Not used 36 B4 PI1 IN LV Not used 37 A5 PI0 IN LV Not used 38 C4 CLKO OUT LV Not used 39 A4 PUP OUT LV Power Up (status of voltage supervision) 40 B3 WSEN IN X Enable DSP and Start DC/DC Converter 41 A3 WRDY OUT LV If WSEN = 0: valid clock input at CLKI If WSEN = 1: clock synthesizer PLL locked 42 B2 AVDD SUPPLY VDD Supply for Analog Circuits 43 A2 CLKI IN X Clock Input 44 A1 AVSS SUPPLY VSS Ground Supply for Analog Circuits 24 (If not used) Micronas MAS 3504D 4.2.1. Pin Descriptions 4.2.1.3. Control Lines 4.2.1.1. Power Supply Pins I2CC I2CD Connection of all power supply pins is mandatory for the function of the MAS 3504D. VDD VSS SCL SDA IN/OUT IN/OUT Standard I2C control lines. Normally there are Pull-upresistors tied from each line to VDD. SUPPLY SUPPLY 4.2.1.4. Parallel Interface Lines The VDD/VSS pair is internally connected with all digital modules of the MAS 3504D. XVDD XVSS SUPPLY SUPPLY The XVDD/XVSS pins are internally connected with the pin output buffers. AVDD AVSS SUPPLY SUPPLY The AVDD/AVSS pair is connected internally with the analog blocks of the MAS 3504D, i.e. clock synthesizer and supply voltage supervision circuits. ’PIO handshake lines’ are used in operation mode. PIO-DMA mode is used in input mode and µP mode in output mode. PCS IN The ’PIO chip select’ is driven from microcontroller to activate data output from MAS 3504D to the bus. Data is output to the bus on the falling edge of PCS and is removed on the rising edge of PCS. PR IN The ’PIO request’ must be set to ‘1’ to validate data output from MAS 3504D. 4.2.1.2. DC/DC Converter Pins DCEN 4.2.1.4.1. PIO Handshake Lines IN OUT RTR The DCEN input signal enables the DC/DC converter operation. ‘Ready to read’ is driven from the MAS 3504D in PIO/ DMA input mode. DCSG RTW SUPPLY OUT The ‘DC converter Signal Ground’ pin is used as a basepoint for the internal switching transistor of the DC/DC converter. It must always be connected to ground. ‘Ready to write’ is driven from MAS 3504D to indicate that data is available in PIO output mode. DCSO ‘End of DMA’ is supported by the built-in firmware in PIO-DMA input mode. OUT DCSO is an open drain output and should be connected with external circuitry (inductor/diode) to start the DC/DC converter. When the DC/DC converter is not used, it has to be connected to VSS. 4.2.1.4.2. PIO Data Lines PI19...PI12 VSENS PARALLEL DATA OUT/IN IN The VSENS pin is the input for the DC/DC converter feedback loop. It must be connected directly with the Schottky diode and the capacitor as shown in Fig. 2–1 on page 7. When the DC/DC converter is not used, it has to be connected to VDD. Micronas OUT EOD These pins are used to send or receive compressed data. 25 MAS 3504D 4.2.1.5. Voltage Supervision And Other Functions 4.2.1.8. Miscellaneous CLKI POR IN This is the clock input of the MAS 3504D. CLKI should be a buffered output of a crystal oscillator. Standard clock frequency is 18.432 MHz. IN The Power On Reset pin is used to reset the digital parts of the MAS 3504D. POR is a low active signal. TE CLKO The TE pin is for production test only and must be connected with VSS in all applications. This pin has no function. PUP IN OUT OUT 4.2.2. Pin Configurations The PUP output indicates that the power supply voltage exceeds its minimal level (software adjustable). XVDD WSEN IN XVSS PI8 SID WSEN enables DSP operation and switches on the DC/DC-converter. SOC SII SOI SIC SOD PI4 WRDY PI12 OUT 33 32 31 30 29 28 27 26 25 24 23 WRDY has two functions depending on the state of the WSEN signal. If WSEN = ’0’, it indicates that a valid clock has been recognized at the CLKI clock input. If WSEN = ’1’, the WRDY output will be set to ‘0’ until the internal clock synthesizer has locked to the incoming audio data stream, and thus, the CLKO clock output signal is valid. PI3 34 22 PI13 PI2 35 21 PI14 PI1 36 20 PI15 PI0 37 19 PI16 CLKO 38 18 PI17 PUP 39 17 PI18 WSEN 40 16 PI19 WRDY 41 15 PCS AVDD 42 14 PR CLKI 43 13 VSENS AVSS 44 12 DCSO MAS 3504D 1 4.2.1.6. Serial Input Interface 2 3 4 5 6 7 8 9 10 11 TE DCSG RTW POR SID SII SIC IN IN IN Data, Frame Indication, and Clock line of the serial input interface. The SII indicates whether the left or the right audio sample is transmitted. I2CC RTR I2CD EOD VDD DCEN VSS Fig. 4–3: PMQFP44 package 4.2.1.7. Serial Output Interface SOD SOI SOC OUT OUT OUT Data, Frame Indication, and Clock line of the serial output interface. The SOI indicates whether the left or the right audio sample is transmitted. 26 Micronas MAS 3504D 4.2.3. Internal Pin Circuits TTLIN DCSO DCSG Fig. 4–4: Input pins PCS, PR VSS Fig. 4–10: Input/Output pins DCSO, DCSG VDD P Fig. 4–5: Input pin TE, DCEN N VSS Fig. 4–6: Input pins WSEN, POR Fig. 4–11: Output pins WRDY, RTW, EOD, RTR, CLKO, PUP VSENS Fig. 4–7: Input pin CLKI VDD P N VSS Fig. 4–12: Input pin VSENS VDD VSS P Fig. 4–8: Input/Output pins PI0...PI4, PI8, SOC, SOI, SOD, PI12...PI19 N VSS VDD Fig. 4–13: Input/Output pins SIC, SII, SID N VSS Fig. 4–9: Input/Output pins I2CC, I2CD Micronas 27 MAS 3504D 4.2.4. Electrical Characteristics 4.2.4.1. Absolute Maximum Ratings Symbol Parameter TA Ambient operating temperature Pin Name Max. Unit °C - operating conditions - extended temperature range1) TC Min. 0 −30 85 85 Case operating temperature °C - LFBGA49 - PMQFP44 0 0 95 95 TS Storage temperature −40 125 °C PMAX Power dissipation for all packages VDD, XVDD, AVDD 400 mW VSUP Supply voltage VDD, XVDD, AVDD 5.5 V VIdig Input voltage, all digital inputs −0.3 VSUP +0.3 V IIdig Input current, all digital inputs −20 +20 mA VII2C Input Voltage, I2C-Pins −0.3 5.5 V IOut Current, all digital outputs 0.5 A IOutDC Current 1.5 A 1) I2CC I2CD DCSO The functionality of the device in the “extended temperature range” was checked by electrical characterization on sample base. Data sheet parameters are valid for “operating conditions” only. Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 28 Micronas MAS 3504D 4.2.4.2. Recommended Operating Conditions Symbol Parameter TA Ambient operating temperature Pin Name - operating conditions - extended temperature range1) VSUP Supply voltage for G.729 decoder operation and download software Min. Typ. 0 −30 VDD, XVDD, AVDD Supply voltage for G.729 encoder operation Max. Unit 85 85 °C °C 2.5 3.0 3.6 V 3.0 3.3 3.6 V Reference Frequency Generation CLKF Clock Frequency CLKI_V Clock Input Voltage 0 CLKAmp Clock Amplitude 0.5 CLKI 18.432 MHz VSUP V Vpp Levels IIL27 Input Low Voltage @VSUP = 2.5 V ... 3.6 V IIH36 Input High Voltage @VSUP = 2.5 V ... 3.6 V IIH33 POR I2CC, I2CD, DCEN, WSEN 0.4 V 1.8 V Input High Voltage @VSUP = 2.5 V ... 3.3 V 1.7 V IIH30 Input High Voltage @VSUP = 2.5 V ... 3.0 V 1.6 V IILD Input Low Voltage IIHD Input High Voltage Trf Rise / Fall time of digital inputs PI<I>, SII, SIC, SID, PR, PCS, CLKI Dcycle Duty cycle of clock inputs SIC, CLKI 1) 2) PI<I>2), SII, SIC, SID, PR, PCS, TE, 0.4 VSUP− 0.5 40 V V 50 10 ns 60 % The functionality of the device in the “extended temperature range” was checked by electrical characterization on a sample base. Data sheet parameters are valid for “operating conditions” only. i = 0 to 4, 8 , 12 to 19 Micronas 29 MAS 3504D Symbol Parameter Pin Name Min. Typ. Max. Unit DC-DC converter external circuitry C1 Blocking Capacitor (25 mΩ ESR)3) VSENS, DCSG VF Schottky Diode Forward voltage4) DCSO, VSENS L Inductance of Ferrite ring core coil5) (50 mΩ),VAC 616/103 DCSO 3) 4) 5) µF 330 0.35 0.45 V µH 20 Sanyo Oscon 6SA330M (distributed by Endrich Bauelemente, D-72202 Nagold-lselshausen, www.endrich.com) ZETEX ZMCS1000 (distributed by ZETEX, D-81673 München, [email protected]), standard Schottky 1N5817 C8 R/4L, SDS0604 (distributed by Endrich Bauelemente, s.a.), VAC 616/103 4.2.4.3. Characteristics Typ. values at TA = 27 °C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50% Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions 46 mA 3.3 V, G.729 encoding 25 mA 3.3 V, G.729 decoding 15 mA 3.3 V, waiting mode V @ ILOAD = 6 mA V @ ILOAD = 6 mA Supply Voltage ISUP Current Consumption VDD, XVDD, AVDD Digital Outputs and Inputs VDOL Output Low Voltage VDOH Output High Voltage CDIGL Input Capacitance IDLeak Digital Input Leakage Current 1) 30 PI<I>1), SOI, SOC, SOD, EOD, RTR, RTW, WRDY, PUP, CLKO PI<I>, SII, SIC, SID, PR, PCS, CLKI 0.3 VSUP0.3 −1 7 pF 1 µA 0 V < Vpin < VSUP i = 0 to 4, 8 , 12 to 19 Micronas MAS 3504D 4.2.4.3.1. I2C Characteristics at TA = −30 to 85 °C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27 °C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50% Symbol Parameter Pin Name RON Output Resistance fI2C Min. Typ. Max. Unit Test Conditions I2CC, I2CD 60 Ω ILOAD = 5 mA, VSUP = 2.7 V I2C Bus Frequency I2CC 400 kHz tI2C1 I2C START Condition Setup Time I2CC, I2CD 300 ns tI2C2 I2C STOP Condition Setup Time I2CC, I2CD 300 ns tI2C3 I2C Clock Low Pulse Time I2CC 1250 ns tI2C4 I2C Clock High Pulse Time I2CC 1250 ns tI2C5 I2C Data Hold Time before Rising Edge of Clock I2CC 80 ns tI2C6 I2C Data Hold Time after Falling Edge of Clock I2CC 80 ns VI2COL I2C Output Low Voltage I2CC, I2CD 0.3 V ILOAD = 5 mA II2COH I2C Output High Leakage Current I2CC, I2CD 1 uA VI2CH = 3.6 V tI2COL1 I2C Data Output Hold Time after Falling Edge of Clock I2CC, I2CD 20 ns tI2COL2 I2C Data Output Setup Time before Rising Edge of Clock I2CC, I2CD 250 ns TW Wait time I2CC, I2CD 0 0.5 4 fI2C = 400 kHz ms 1/fI2C tI2C4 tI2C3 H L I2CC tI2C1 tI2C5 tI2C6 tI2C2 H L I2CD as input tI2COL2 tIC2OL1 H L I2CD as output Fig. 4–14: I2C timing diagram Micronas 31 MAS 3504D 4.2.4.3.2. I2S Bus Characteristics – SDI at TA = −30 to 85 °C, VSUP = 3.0 to 3.6 V, typ. values at TA = 27 °C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50% Symbol Parameter Pin Name Min. tSICLK I2S Clock Input Period SIC 960 tSIIDS I2S Data SetupTime before Falling Edge of Clock SIC, SID 50 tSIIDH I2S Data Hold Time SID 50 tbw Burst Wait Time SIC, SID 480 Typ. Max. Unit Test Conditions ns tSICLK100 ns ns TSICLK H SIC L H SII L H SID L TSIIDS TSIIDH Fig. 4–15: Serial input 32 Micronas MAS 3504D 4.2.4.3.3. I2S Characteristics – SDO at TA = −30 to 85 °C, VSUP = 3.0 to 3.6 V, typ. values at TA = 27 °C, VSUP = 3.3 V, CLKF = 18.432 MHz, duty cycle = 50% Symbol Parameter Pin Name Min. Typ. Max. tSOCLK I2S Clock Output Period SOC tSOISS I2S Wordstrobe Hold Time after Falling Edge of Clock SOC, SOI 10 tSOCLK/ 2 ns tSOODC I2S Data Hold Time after Falling Edge of Clock SOC, SOD 10 tSOCLK/ 2 ns 1953 Unit Test Conditions ns 8 kHz stereo 32 bit/sample TSOCLK SOC SOI H L H L TSOISS SOD TSOISS H L TSOODC Fig. 4–16: Serial output SOI Micronas 33 MAS 3504D 4.2.4.4. DC/DC Converter Characteristics at TA = −30 to 85 °C, VSUP = 3.0 V, CLKF = 14.725 MHz, fsw = 230 kHz, typ. values at TA = +27 °C Unless otherwise noted: VOUT = 3.0 V, VIN = 1.2 V Note: The following characterizations were made with voltage and clock input that is not usable for G.729 applications. Symbol Parameter Pin Name VIN1 Minimum start-up input voltage VIN2 Minimum operating input voltage VOUT Output voltage range Min. Typ. Max. Unit Test Conditions 1) 0.9 1.1 V ILOAD = 0 mA DCCF = 08000hex (Reset) 1) 0.6 0.9 V ILOAD = 55 mA, DCCF = 08000hex (Reset) 1.3 1.8 V ILOAD = 250 mA, DCCF = 08000hex (Reset) V VIN = 1.2 V ILOAD = 50 mA 3.6 % ILOAD = 50 mA Tj = 27 °C VIN = 1.2 V 150 mA VIN = 0.9..1.5 V 250 mA VIN = 1.8..3.0 V VSENS Bits 16..14, Bit 9 of DCCF Register [hex]: 3.567 3.460 3.354 3.248 3.144 3.039 2.935 2.831 2.729 2.625 2.524 2.422 2.321 2.219 2.118 2.017 1C000 18000 14000 10000 0C000 08000 04000 00000 1C200 18200 14200 10200 0C200 08200 04200 00200 VOTOL Output voltage tolerance VSENS ILOAD1 Output current VSENS −3.6 ILOAD2 dVOUT/dVIN/ VOUT Line regulation VSENS 0.35 %/V ILOAD = 50mA dVOUT/dVIN/ VOUT Line regulation VSENS 0.7 %/V ILOAD = 250 mA, VOUT = 3.5 V, VIN = 2.4 V dVOUT/VOUT Load regulation VSENS −0.5 % ILOAD = 50...150 mA, dVOUT/VOUT Load regulation VSENS −0.5 % ILOAD = 50..250 mA, VOUT = 3.5 V, VIN = 2.4 V 1) 34 All measurements are made with a C8 R/4L 20 µH, 25 mΩ ferrite ring-core coil, Zetex ZLMCS1000 Schottky diode, and Sanyo/Oscon 6SA330M 330 µF, 25 mΩ ESR capacitors at input and output (see Section 4.2.4. on page 28). Micronas MAS 3504D Symbol Parameter hmax Maximum efficiency ISUPPLY Supply current VSENS 1.1 IL,MAX Inductor current limit DCSO, DCSG 1.0 RON Switch on-resistance DCSO, DCSG 0.4 ILEAK Switch leakage current DCSO, DCSG 0.1 1 µA Tj = 27 °C, converter = off, ILOAD = 0 µA fSW Switch frequency DCSO, DCSG 230 460 kHz Depending on DCCF tSTART Start up time asserting to PUP DCEN, PUP 8 ms VIN = 1.0 V, ILOAD = 1 mA, PUPLIM = 010 (Reset) fSTARTUP VSENSE DCSO 250 kHz VSENS < 1.9 V Micronas Pin Name Min. Typ. Max. Unit Test Conditions % VIN = 3.0 V, VOUT = 3.5 V 5 mA VIN = 3.0 V, ILOAD = 0, includ. switch current 1.4 A 90 156 Ω 35 MAS 3504D 4.2.4.5. Typical Performance Characteristics Efficiency vs. Load Current (Vout=3.5V) Efficiency vs. Load Current (Vout=3.0V) 100 100 Vin 80 1.8 V Efficiency (%) Efficiency (%) 80 2.4 V 3.0 V 60 40 Vin: 3.0V 2.4V 1.8V 20 0 10 -4 10-3 10-2 10-1 Vin 0.7 V 60 Vin: 2.4V 1.8V 1.5V 1.2V 0.9V 0.7V 40 20 0 10 -4 1 Load Current (A) 10-3 10-2 10-1 1 Load Current (A) Efficiency vs. Load Current (Vout=2.7V) Efficiency vs. Load Current (Vout=2.2V) 100 100 Vin 2.4 V Vin 80 1.5 V 80 Efficiency (%) Efficiency (%) 1.2 V 60 40 Vin: 2.4V 1.8V 1.2V 20 0.7 V 60 40 Vin: 1.5V 1.2V 0.9V 0.7V 20 0 0 10 -4 10 -3 -2 10 Load Current (A) 10 -1 1 10 -4 10-3 10-2 10-1 1 Load Current (A) Fig. 4–17: Efficiency vs. Load Current 36 Micronas MAS 3504D Output Voltage vs. Input Voltage Iload=250mA Output Voltage vs. Input Voltage Iload=50mA 3.6 3.2 3.1 V 3.5 V 3 3.4 Output Voltage (V) Output Voltage (V) 2.8 3.2 3.1 V 3 2.8 2.7 V 2.6 2.4 2.2 V 2.2 2.7 V 2.6 2 1.5 2 2.5 3 3.5 0.9 Input Voltage (V) 1.4 1.9 2.4 2.9 Input Voltage (V) Fig. 4–18: Output Voltage vs. Input Voltage Output Voltage vs. Load Current 3.6 Output Voltage vs. Load Current Vin 3.4 Vin=3V, 2.4V, 1.8V 3.4 Vin 3.2 3.2 Output Voltage Output Voltage (V) 3 3 Vin=1.5V, 0.9V 2.8 2.6 2.4 Vin 2.8 2.2 Vin=1.5V, 0.9V Vin=2.4V 2.6 0 0.1 2 0.2 Load Current (A) 0.3 0 0.02 0.04 0.06 0.08 Load Current (A) Fig. 4–19: Output Voltage vs. Load Current Micronas 37 MAS 3504D 0.8 6.0 0.6 3.5V 2.2V Vout 0.4 Vout= 3.5V 3.1V 2.7V 2.2V 0.2 0 0 1 2 Input Voltage (V) 3 Vout = 3 V No Load Supply Current (mA) Maximum Load Current (A) No Load Supply Current vs. Input Voltage Maximum Load Current vs. Input Voltage 4.0 2.0 0 0 1 2 3 Input Voltage (V) Fig. 4–20: Maximum Load Current vs. Input Voltage 38 Fig. 4–21: No Load Supply Current vs. Input Voltage Micronas MAS 3504D 3V 3V 3V 3V 0A 0A 0A 500 µs/Div 500.00 µs/Div Vin = 1 V; Iload = 0 mA Vin = 1.2 V; Vout = 3 V 1 Load Current 2 Output Voltage 3 Inductor Current 200.0 mA/Div 100.0 mV/Div / AC-coupled 500.0 mA/Div 1 2 3 4 V (DCEN) V (PUP) Inductor Current Output Voltage 2.000 V/Div 2.000 V/Div 500.0 mA/Div 2.000 V/Div Fig. 4–24: Startup Waveform Fig. 4–22: Load Transient-Response 3V 200 mA 2V 5.00 ms/Div Iload = 100 mA; Vout = 3 V 1 Vin 2.000 V/Div 2 Output Voltage 50.00 mV/Div / AC-coupled 3 Inductor Current 200.0 mA/Div Fig. 4–23: Line Transient-Response Micronas 39 MAS 3504D 5. Data Sheet History 1. Final data sheet: “MAS 3504D G.729 Annex A Voice Codec”, Nov. 7, 2001, 6251-522-1DS. First release of the final data sheet. Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com Printed in Germany Order No. 6251-522-1DS 40 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Micronas