19-1353; Rev 0; 4/98 KIT ATION EVALU E L B AVAILA Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD Features ♦ Dual Output Using a Single Inductor ♦ Low-Noise Output, 30mVp-p Ripple ♦ Output Voltages up to 24V and down to -9V (up to 45V and down to -16V with added components) ♦ Internal Switches in a Small Package ♦ 220kHz/400kHz Fixed-Frequency PWM Operation ♦ Frequency Can Be Synchronized to External Clock ♦ Power-OK Indicator ♦ Selectable Power-On Sequencing ♦ 0.1µA Logic-Controlled Shutdown Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX685EEE -40°C to +85°C 16 QSOP Typical Operating Circuit Applications Camcorders Digital Cameras LCDs CCD Imaging Devices INPUT 2.7V TO 5.5V Notebooks VP LXN VDD Pin Configuration POSITIVE OUTPUT UP TO 24V, 10mA FBP ON TOP VIEW LXP 1 16 LXN I.C. 2 15 I.C. 14 PGND VP 3 POK 4 MAX685 SHDN OFF MAX685 OPTIONAL LXP SEQ FBN 13 PGND POS SEQ 5 12 FBP SHDN 6 11 REF SYNC 7 10 FBN 9 VDD 8 SYNC NEGATIVE OUTPUT DOWN TO -9V, 10mA NEG POWER-OK INDICATOR POK GND REF GND QSOP I.C. = INTERNALLY CONNECTED ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX685 General Description The MAX685 DC-DC converter provides low-noise dual outputs for powering CCD imaging devices and LCDs. This device uses a single inductor to provide independently regulated positive and negative outputs. Integrated power switches are included in the small 16-pin QSOP package (same size as an 8-pin SO) to save space and reduce cost. Each output delivers up to 10mA from a +2.7V to +5.5V input voltage range. Output voltages are set independently up to 24V and down to -9V. With a few additional low-cost components, the output voltages can be set at up to 45V and down to -16V. Output ripple magnitude is 30mVp-p. The MAX685 uses a fixed-frequency, pulsewidth-modulated (PWM) control scheme at 220kHz or 400kHz to permit output noise filtering and to reduce the size of external components. The frequency can also be synchronized to an external clock signal between 200kHz and 480kHz. The MAX685 has a power-OK indicator output (POK) that signals when both outputs are within regulation. A logic-controlled shutdown completely turns off both outputs and reduces supply current to 0.1µA. The user can also set which output turns on first. The preassembled MAX685 evaluation kit is available to reduce design time. MAX685 Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD ABSOLUTE MAXIMUM RATINGS VDD, VP to GND........................................................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V VDD to VP...............................................................-0.3V to +0.3V LXN, POK to GND ..................................................-0.3V to +30V LXP to VDD..............................................................-15V to +0.3V REF, SEQ, SHDN to GND...........................-0.3V to (VDD + 0.3V) FBP, FBN, SYNC to GND .........................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C above +70°C)............667mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VP = 5V, TA = 0°C to +85°C unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Voltage Range CONDITIONS VDD = VP Positive Output Voltage Range MIN MAX UNITS 2.7 TYP 5.5 V VP 24 V -1.27 V Negative Output Voltage Range VDD = 5.5V (Note 1) -9 Output Current VDD = 4.5V, VOUT+ ≥ 14.25V, VOUT- ≤ -7.125V, Figure 3 10 LX Current Limit TA = +25°C 440 LXP, LXN On-Resistance VDD = 4.5V 0.6 Quiescent Current SYNC = VDD 0.8 Idle Quiescent Current VFBP = 1.35V, VFBN = -0.1V 300 Line Regulation VDD = 4.5V to 5.5V 0.2 %/V Load Regulation IOUT = 0 to 10mA, C1 = 10µF 0.13 %/mA Output Voltage Ripple C3 = C4 = 10µF, ILOAD = 5mA 30 mVp-p SYNC = SEQ = SHDN = GND 0.1 10 µA 2.5 2.65 V mA mA 2 Ω mA 500 µA SHUTDOWN (SHDN) Shutdown Supply Current UNDERVOLTAGE LOCKOUT UVLO Threshold VDD = rising 2.35 UVLO Hysteresis 50 mV REFERENCE VOLTAGE VREF Output Voltage No load VREF Load Regulation 0 < IREF < 50µA 1.23 1.250 1.27 -2 V mV FB INPUTS FBP Threshold Voltage No load 1.21 1.24 1.27 V FBN Threshold Voltage No load -16 10 36 mV ±0.01 ±0.1 µA FBP, FBN Input Leakage Current LOGIC INPUTS (SEQ, SHDN, SYNC) Logic-Low Input 2.7V < VDD < 5.5V Logic-High Input 2.7V < VDD < 5.5V Input Bias Current 2 0.3 x VDD 0.7 x VDD V V 0.1 _______________________________________________________________________________________ 1 µA Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD (VDD = VP = 5V, TA = 0°C to +85°C unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS 480 kHz SYNC INPUT Sync Frequency Range (external) Oscillator Frequency (internal) 200 SYNC = GND 175 220 265 SYNC = VDD 320 400 480 kHz POK COMPARATORS FBP POK Threshold FBP rising 1.090 1.122 1.150 V FBN POK Threshold FBN falling 54 79 108 mV POK Output Low Voltage IPOK = 2mA 0.4 V POK Output Off Current VPOK = 10V 1 µA MIN MAX UNITS 2.7 5.5 V VP 24 V -1.27 V ELECTRICAL CHARACTERISTICS (VDD, VP = 5V, TA = -40°C to +85°C unless otherwise noted.) (Note 2) PARAMETER Input Voltage Range CONDITIONS VDD = VP Positive Output Voltage Range Negative Output Voltage Range VDD = 5.5V (Note 1) -9 Maximum Output Current VIN = 4.5V, VOUT+ ≥ 14.25V, VOUT- ≤ -7.125V, Figure 3 10 Idle Quiescent Current SYNC = GND 500 µA SYNC = SEQ = SHDN = GND 10 µA 2.35 2.65 V mA SHUTDOWN Shutdown Supply Current UNDERVOLTAGE LOCKOUT UVLO Threshold VDD = rising FB INPUTS AND REFERENCE VOLTAGE FBP Threshold Voltage No load 1.205 1.275 V FBN Threshold Voltage No load -20 40 mV VREF Output Voltage No load 1.225 1.275 V LOGIC INPUTS (SEQ, SHDN, SYNC) Logic-Low Input 2.7V < VDD ≤ 5.5V Logic-High Input 2.7V < VDD ≤ 5.5V 0.3 x VDD 0.7 x VDD V V POK COMPARATORS FBP POK Threshold FBP rising 1.090 1.150 V FBN POK Threshold FBN falling 54 108 mV Note 1: Negative output voltage can be larger magnitude for lower values of VDD. The voltage between VDD and VOUT- must not exceed 14.5V. Note 2: Specifications to -40°C are guaranteed by design, not production tested. _______________________________________________________________________________________ 3 MAX685 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 3, VOUT+ = 15V, VOUT- = -7.5V, TA = +25°C, unless otherwise noted.) VIN = 5.0V VIN = 5.0V 80 70 80 70 65 60 2 4 6 8 10 1 2 3 4 5 6 7 8 9 10 2 4 6 8 LOAD CURRENT (mA) REFERENCE LOAD REGULATION REFERENCE VOLTAGE (V) 1.5 1.0 MAX685-06 1.250 MAX685-04 2.0 1.249 0.5 1.248 0 2.5 3.0 3.5 4.0 4.5 5.0 0 5.5 5 10 15 20 25 30 35 40 45 50 INPUT VOLTAGE (V) LOAD CURRENT (µA) LX SWITCHING FREQUENCY vs. INPUT VOLTAGE REFERENCE VOLTAGE vs. TEMPERATURE 1.254 MAX865-07 250 240 REFERENCE VOLTAGE (V) 220 210 200 190 180 VIN = 3.3V 1.252 230 MAX685-13 NO-LOAD CURRENT (mA) 0 LOAD CURRENT (mA) NO-LOAD CURRENT vs. INPUT VOLTAGE OSCILLATOR FREQUENCY (kHz) 65 50 0 LOAD CURRENT (mA) 1.250 VIN = 5.0V 1.248 1.246 1.244 170 1.242 SYNC = VDD 160 1.240 150 2.7 3.2 3.7 4.2 4.7 INPUT VOLTAGE (V) 4 70 55 50 0 VIN = 3.3V 75 60 55 60 VIN = 5.0V 85 EFFICIENCY (%) EFFICIENCY (%) VIN = 3.3V 90 VIN = 3.3V 75 80 EFFICIENCY vs. LOAD CURRENT (BOTH OUTPUTS LOADED) MAX685-02 85 MAX685-01 90 EFFICIENCY vs. LOAD CURRENT (NEGATIVE OUTPUT LOADED) MAX685-03 EFFICIENCY vs. LOAD CURRENT (POSITIVE OUTPUT LOADED) EFFICIENCY (%) MAX685 Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD 5.2 5.7 -40 -20 0 20 40 60 TEMPERATURE (°C) _______________________________________________________________________________________ 80 100 10 Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD 11mA IOUT+ MAX685-09 VOUT- LOAD-TRANSIENT RESPONSE MAX685-08 VOUT+ LOAD-TRANSIENT RESPONSE -1mA 5mA/div 1mA 5mA/div IOUT-11mA 100mV/div 100mV/div VOUT+ VOUT- 2ms/div 2ms/div MAX685-10 LINE-TRANSIENT RESPONSE VOUT+ 100mV/div VOUT- 100mV/div VDD, VP 2V/div 1ms/div INPUT 4V TO 5V, +15V AT 10mA, -7.5V AT 10mA START-UP (SEQ = HIGH) START-UP (SEQ = LOW) MAX685-12 MAX685-11 VOUT+ VOUT+ 5V/div 5V/div VOUT- 5V/div 2ms/div START-UP, SEQ = HIGH, VDD = VP = 5.0V, +15V AT 10mA, -7.5V AT 10mA 5V/div VOUT- 2ms/div START-UP, SEQ = LOW, VDD = VP = 5.0V, +15V AT 10mA, -7.5V AT 10mA _______________________________________________________________________________________ 5 MAX685 Typical Operating Characteristics (continued) (Circuit of Figure 3, VOUT+ = 15V, VOUT- = -7.5V, TA = +25°C, unless otherwise noted.) Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD MAX685 Pin Description PIN NAME FUNCTION 1 LXP P-Channel Switching Inductor Node. LXP turns off when the part enters shutdown. 2, 15 I.C. Internally Connected. Do not externally connect. 3 VP Power Input. Connect to VDD. 4 POK Open-Drain Power-OK Output. POK is high when both outputs are in regulation. Connect POK to VDD with a 100kΩ pull-up resistor to VDD. 5 SEQ Power-Up Sequence Select Input. Connect SEQ to GND to power the negative output voltage first. Connect SEQ to VDD to power the positive output first. 6 SHDN Shutdown Input. Both outputs go to 0V in shutdown. Connect to VDD for automatic startup. 7 SYNC Sync Input. This pin synchronizes the oscillator to an external clock frequency between 200kHz and 480kHz. Connect SYNC to GND (220kHz) or VDD (400kHz) for internal oscillator frequency. 8 VDD Supply Input. Bypass VDD with a 1.0µF or greater ceramic capacitor to GND. 9 GND Ground 10 FBN Feedback Input for the Negative Output Voltage. Connect a resistor-divider between the negative output and REF with the center to FBN to set the negative output voltage. 11 REF 1.25V Reference Voltage Output. Bypass with 0.22µF to GND. 12 FBP Feedback for the Positive Output Voltage. Connect a resistor-divider between the positive output and GND with the center to FBP to set the positive output voltage. 13, 14 PGND 16 LXN Power Ground. Connect PGND to GND. N-Channel Switching Inductor Node. LXN pulls to GND through the internal transistor when the part is shut down. _______________Detailed Description The MAX685 DC-DC converter accepts an input voltage between +2.7V and +5.5V and generates both a positive and negative voltage, using a single inductor (Figure 1). It alternates between acting as a step-up converter and as an inverting converter on a cycle-by-cycle basis. Both output voltages are independently regulated. Each output is separately controlled by a pulse-widthmodulated (PWM) current mode regulator. This allows the part to operate at a fixed frequency for use in noisesensitive applications. An internal oscillator runs at 220kHz or 400kHz, or can be synchronized to an external signal. Since switching alternates between the two regulators, each operates at half the oscillator frequency (110kHz, 200kHz, or half the sync frequency). The oscillator can be synchronized to a 200kHz to 480kHz clock. On the first cycle of operation, the part operates as a step-up converter. LXP connects to VDD, LXN pulls to ground, and the inductor current rises. Once the induc6 tor current rises to a level set by the positive-side error amplifier, LXN releases and the inductor current flows through D2 to the positive output. When the inductor current drops to zero (which happens each cycle under normal, discontinuous operation), LXN returns to the input voltage. On the second cycle, LXN is held at ground. LXP is pulled up to the input voltage until the current reaches the limit set by the negative error amplifier. Then LXP is released and the inductor current flows through D1 to the negative output. Once the inductor current reaches zero, the voltage at LXP returns to ground. The waveforms at LXN and LXP are shown in Figure 2 for a typical pair of cycles. The current into the LXN pin is sensed to measure the inductor current. The MAX685 controls the inductor current to regulate both the positive and negative output voltages. _______________________________________________________________________________________ Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD VDD MAX685 POK TO VOUT- VP MAX685 FBN NEGATIVE ERROR AMP P TO VOUT+ FBP POSITIVE ERROR AMP LXP D1 LXN D2 VOUT- CONTROL LOGIC VOUT+ N REF 1.25V REF GND PGND SYNC SEQ SHDN Figure 1. Functional Diagram +15V LXN 0V +5V LXP 0V -7.5V Figure 2. LXN and LXP Waveforms (see also Figure 5) SEQ and Power OK (POK) The SEQ pin controls the power-up sequence. If SEQ is low, the positive output is disabled until the negative output is within 90% of its regulation point. If SEQ is high, the negative output is disabled until the positive output is within 90% of its regulation point. The powerOK output (POK) indicates that both output voltages are in regulation. When both outputs are within 90% of their regulation points, POK becomes high impedance. Should one or both of the output voltages fall below 90% of their regulation points, POK pulls to ground. POK can sink up to 2mA. To reduce current consumption, POK is high impedance while the part is in shutdown. When coming out of shutdown, POK remains high impedance for 50ns (typ) before going low. Connect POK to VDD through a 100kΩ resistor. Synchronization/Internal Frequency Selection The MAX685 operates at a fixed switching frequency. Set the operating frequency using the SYNC pin. If SYNC is grounded, the part operates at the internally set 220kHz frequency. When SYNC is connected to VDD, the part operates at 400kHz. The MAX685 can also be synchronized to signals between 200kHz and 480kHz. Note that each output switches at half the oscillator or synchronized frequency. Since the actual switching frequency is one-half the applied clock signal, drive SYNC at twice the desired switching frequency. _______________________________________________________________________________________ 7 MAX685 Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD Applications Information Figure 3 shows the standard application circuit for the MAX685. The values shown in Table 1 will work well for output currents up to 10mA. However, this circuit can be optimized to a particular application by using different capacitors and a different inductor. Higher Output Voltages If the application requires output voltages greater than -7.5V or +24V, use the circuit of Figure 4. This circuit uses a charge pump to increase the output voltage without increasing the voltage stress on the LX_ pin. The maximum output voltages of the circuit in Figure 4 are -15V and +48V. The voltage rating on D2, D5, and D6 must be 30V or greater. For a larger negative output voltage without a larger positive output (or vice versa), use one-half of the Figure 4 circuit with one-half of the Figure 3 circuit. Inductor Selection A 22µH inductor is suitable for most applications. Larger inductances will reduce inductor ripple current and output voltage ripple, but they also typically require larger physical size if increased resistance and losses are not also allowed. Filter Capacitor Selection The output ripple voltage is a function of the peak inductor current, frequency, and type and value of the output capacitors. Capacitors with low equivalentseries resistance (ESR) and large capacitance reduce output ripple. Typically, tantalum or ceramic capacitors are optimal. Tantalum capacitors have higher ESR and higher capacitance than ceramic capacitors. Therefore the ESR of tantalum capacitors determines the output ripple, because at the frequencies used the ESR dominates the impedance of the capacitor. If ceramic capacitors are used, the capacitance determines the output ripple. VIN VIN C1 10µF C1 10µF R5 100k C2 0.22µF 11 3 REF VP R4 124k VDD POK R3 750k 4 FBP LXP GND PGND LXN 9 13, 14 16 1 R4 +15V VOUT+ D1 NBR0520 L1 22µH D2 NBR0520 Figure 3. Standard Application Circuit 10 FBN 12 R1 1.0M R2 90.9k R3 4 POK C6 1µF SHDN 7 SYNC 12 FBP R2 LXP GND PGND LXN 1 9 13, 14 16 C8 1µF R1 VOUT- C7 2.2µF C5 47pF VOUT+ D3 C4 2.2µF 8 VDD POK SYNC SYNC C5 47pF 3 MAX685 SHDN 6 SHDN 7 -7.5V VOUTC3 2.2µF 11 REF VP POK MAX685 SHDN 6 FBN R5 100k C2 0.22µF 8 SYNC 10 8 Small inductors are typically preferred because of compact design and low cost. Murata LHQ and TDK NLC types are examples of small surface-mount inductors that work for most applications. Because these small-size inductors use thinner wire, they exhibit higher resistance and have greater losses than larger ones. If the application demands higher efficiency, use larger, lower resistance coils such as the Sumida CD43 or CD54, Coilcraft DT1608 or DO1608, or Coiltronics UP1V series. D4 C3 2.2µF D1 L1 22µH D2 C4 2.2µF D5 D6 C9 2.2µF Figure 4. Circuit for Output Voltages < -9V and > +24V _______________________________________________________________________________________ Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD REF DESCRIPTION MANUFACTURER PART NUMBER C1 10µF, 10V tantalum cap Sprague 595D106X0010A2T or AVX TAJA106K010R C2 0.22µF ceramic capacitor Any manufacturer C3, C4 2.2µF ceramic capacitor Any manufacturer 47pF ceramic cap Any manufacturer 0.1A, 20V Schottky rectifier Motorola MBR0520LT1 (0.5A) or Central Semiconductor CMPSH-3 22µH, 0.4A inductor Murata LHQ4N220J04 or TDK NLC32522T-220K C5 D1, D2 L1 Damping LX LXN and LXP may ring at the conclusion of each switching cycle when the inductor current falls to zero. Typically the ringing waveform appears only on LX_ and has no effect on output ripple and noise. If LX_ ringing is still objectionable, it may be damped by connecting a series RC in parallel with L1. Typically 1kΩ in series with 100pF provides good damping with only 3% efficiency degradation. See Figure 5. +15V LXN +5V 0V +5V LXP 0V Setting the Output Voltage The resistor-divider formed by R4 and R3 sets the negative output voltage; the resistor-divider formed by R1 and R2 sets the positive output voltage. Let R4 be a value near 100kΩ to set a resistor-divider current of approximately 10µA. Determine the value of R3 by the following: R 3 = R4 -7.5V Figure 5. LXN and LXP Waveforms with a Series-Connected 1kΩ Resistor and 100pF Capacitor Connected in Parallel with L1 to Damp Ringing VOUT − 1.24 V Let R2 be a value near 100kΩ to set a resistor-divider current of approximately 10µA. Determine the value of R1 with the following formula: R1 = R2 x (VOUT+ - 1.24V) / 1.24 _______________________________________________________________________________________ 9 MAX685 Table 1. Component Values for the Typical Operating Circuit ___________________Chip Information TRANSISTOR COUNT: 902 SUBSTRATE CONNECTED TO GND Package Information QSOP.EPS MAX685 Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD 10 ______________________________________________________________________________________ Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD ______________________________________________________________________________________ MAX685 NOTES 11 MAX685 Dual-Output (Positive and Negative), DC-DC Converter for CCD and LCD NOTES 12 ______________________________________________________________________________________