19-3596; Rev 0; 2/05 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors ♦ Up to Eight Independent, Open-Drain Power-Good Outputs ♦ Enable Margining Disable and Manual Reset Controls ♦ -40°C to +85°C Operating Temperature Range ♦ Small 5mm x 5mm Thin QFN Package ♦ Few External Components ♦ ±1% Threshold Accuracy Ordering Information PART TEMP RANGE PINPACKAGE MAX6892ETJ -40°C to +85°C 32 Thin QFN T3255-4 MAX6893ETI -40°C to +85°C 28 Thin QFN T2855-8 MAX6894ETI -40°C to +85°C 28 Thin QFN T2855-8 PKG CODE 28 IN6 29 IN4 30 IN5 IN3 31 IN1 32 IN2 WDI TOP VIEW PG1 Pin Configurations 27 26 25 PG2 1 24 IN7 PG3 2 23 IN8 PG4 3 22 DBP GND 4 21 VCC 20 ENABLE 19 SRT 18 SWT 17 TH4 PG7 7 PG8 8 *EXPOSED PADDLE 9 10 11 12 13 14 15 16 TH3 6 TH1 5 PG6 TH2 PG5 MAX6892 TH0 Typical Operating Circuit appears at end of data sheet. ♦ Factory-Default Reset and Watchdog Timeout Periods MR Multimicroprocessor/Voltage Systems ♦ Capacitor-Adjustable Reset and Watchdog Timeout Periods WDO Telecommunication/Central Office Systems Networking Systems Servers/Workstations Base Stations Storage Equipment ♦ Dedicated RESET and WDO Outputs MARGIN Applications ♦ Pin-Selectable or User-Adjustable Voltage Detector Thresholds RESET The MAX6892/MAX6893/MAX6894 pin-selectable, multivoltage supply sequencers/supervisors monitor several voltage-detector inputs and one watchdog input, asserting the respective voltage detector or watchdog output when the inputs drop below the configured voltage thresholds or the watchdog timer expires. The MAX6892 features eight voltage detector inputs and 10 outputs. The MAX6893 features six voltage-detector inputs and eight outputs, while the MAX6894 features four voltage detector inputs and six outputs. A RESET output ensures all monitored inputs are above the set thresholds. The voltage detector outputs are configured as open drain. Manual reset and margin disable inputs offer additional flexibility. The thresholds of the MAX6892/MAX6893/MAX6894 are selected through five logic inputs (TH0–TH4). The logic on these five inputs selects the supply voltage tolerance (5% or 10%) and one of 32 factory-set thresholds settings. Watchdog and reset timeout periods can use factory default settings or are independently adjustable by connecting external capacitors. When any of the monitored voltages falls below its threshold, the respective output asserts and remains asserted for 6.25ms (typ) after the monitored voltage exceeds the threshold. The outputs can be connected to the shutdown or enable inputs of DC-DC regulators to provide turn-on power sequencing to ensure proper system initialization. The MAX6892 is available in a 5mm x 5mm x 0.8mm, 32-pin, thin QFN package, while the MAX6893/ MAX6894 are available in a 5mm x 5mm x 0.8mm, 28pin, thin QFN package. The MAX6892/MAX6893/ MAX6894 are specified to operate over the extended temperature range (-40°C to +85°C) Features THIN QFN *EXPOSED PAD INTERNALLY CONNECTED TO GND. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX6892/MAX6893/MAX6894 General Description MAX6892/MAX6893/MAX6894 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) PG_, RESET, WDO .................................................-0.3V to +14V IN1–IN8, TH0–TH4, ENABLE, WDI, MR, MARGIN, SRT, SWT, VCC .....................................................-0.3V to +6V DBP ..........................................................................-0.3V to +3V Input/Output Current (all pins)..........................................±20mA Continuous Power Dissipation (TA = +70°C) 28-Pin Thin QFN (derate 21.3mW/°C above +70°C).............................................................1702mW 32-Pin Thin QFN (derate 21.3mW/°C above +70°C)............................................................1702mW Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN1 = VIN6–VIN8 = GND, VIN2–VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1 and 2) PARAMETER SYMBOL Operating Voltage Range (Note 3) Undervoltage Lockout VUVLO Digital Bypass Voltage VDBP CONDITIONS MIN Voltage on either one of IN2–IN5 or VCC that guarantees the part is fully operational 2.7 For 1V < (VIN2–VIN5 or VCC ) < VUVLO, PG_ are pulled down to GND with a 10µA current No load Supply Current ICC VIN2 = 5.5V, VIN1, VIN3–VIN8 = GND, no load Threshold Accuracy (Table 2) VTH IN1–IN8, IN_ falling Threshold Hysteresis VTH-HYS Threshold Tempco ∆VTH/°C 2.48 TYP MAX UNITS 5.5 V 2.5 V 2.55 2.67 V 0.9 1.1 mA TA = +25°C to +85°C -1 +1 TA = -40°C to +85°C -2 +2 % VTH 0.3 % VTH 10 ppm/°C IN1, IN6–IN8 Input Leakage Current IN2–IN5 Input Impedance IIN RIN2–IN5 Power-Up Delay tD-PO IN_ to PG_ Delay tD-R PG_ Timeout Period tPG RESET Default Timeout Period tRP RESET Adjustable Timeout Period SRT Adjustable Timeout Current 2 -50 +50 nA 555 kΩ 3 ms IN2–IN5 set as adjustable thresholds For IN_ voltages < the highest IN_ supply or < VCC and thresholds are not set as adjustable 290 400 VCC ≥ VUVLO IN_ falling/rising, 100mV overdrive 25 µs 5.625 6.25 6.875 ms VSRT = VCC 180 200 220 ms tRP-ADJ CSRT = 47nF 135 207 280 ms ISRT VSRT = GND 180 230 280 nA _______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors (VIN1 = VIN6–VIN8 = GND, VIN2–VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SRT Default Timeout Threshold VSRT-DEF VSRT ≥ VSRT-DEF, selects reset default timeout 1.1 1.25 1.5 V SRT Adjustable Timeout Threshold VSRT-ADJ (Note 4) 0.95 1.0 1.05 V SRT Adjustable Timeout Discharge Threshold VSRT-DIS (Note 5) SRT Adjustable Timeout Output Low Discharge Current ISRT-DIS VSRT = 0.3V PG_, RESET, WDO Output Low VOL ISINK = 4mA, output asserted PG_, RESET, WDO Output Initial Pulldown Current IUV VCC < VUVLO, VPG_, RESET, WDO = 0.8V PG_, RESET, WDO Output OpenDrain Leakage Current ILKG Output high impedance 100 0.7 -1 VIL 1.4 MR Input Pulse Width T MR 1 MR Glitch Rejection tD-MR I MR MARGIN to DBP Pullup Current IMARGIN ENABLE to PG_ Delay tD-ENPG ENABLE Pulldown Current 0.4 V 40 µA +1 µA 0.6 VIH MR to DBP Pullup Current mA 10 MR, MARGIN, ENABLE, TH0–TH4, WDI Input Voltage MR to RESET Delay mV V µs 100 ns 2 µs V MR = 1.4V 5 10 15 µA V MARGIN = 1.4V 5 10 15 µA 200 V ENABLE = 0.6V 5 10 ns 15 µA _______________________________________________________________________________________ 3 MAX6892/MAX6893/MAX6894 ELECTRICAL CHARACTERISTICS (continued) MAX6892/MAX6893/MAX6894 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors ELECTRICAL CHARACTERISTICS (continued) (VIN1 = VIN6–VIN8 = GND, VIN2–VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1 and 2) PARAMETER SYMBOL CONDITIONS TH0–TH4 Input Current WDI Pulldown Current Watchdog Adjustable Timeout Period TYP -1 IWDI VWDI = 0.6V 5 WDI Input Pulse Width Watchdog Default Timeout Period MIN MAX µA 10 15 µA 50 tWD tWD-ADJ UNITS +1 ns Initial mode 92.16 102.4 112.64 Normal mode 1.44 1.6 1.76 Initial mode 53.7 82.5 111.9 Normal mode 0.93 1.43 1.94 VSWT = GND 180 230 280 nA VSWT = VCC CSWT = 0.33µF s s SWT Adjustable Timeout Current ISWT SWT Default Timeout Threshold VSWT-DEF VSWT ≥ VSWT-DEF, selects watchdog default timeout period 1.1 1.25 1.5 V SWT Adjustable Timeout Threshold VSWT-ADJ (Note 4) 0.95 1.0 1.05 V SWT Adjustable Timeout Discharge Threshold VSWT-DIS (Note 5) SWT Adjustable Timeout Output Low Discharge Current ISWT-DIS VSWT = 0.3V Note 1: Note 2: Note 3: Note 4: Note 5: 4 100 0.7 100% production tested at TA = +25°C and TA = +85°C. Specifications at TA = -40°C are guaranteed by design. Device may be supplied from any one of IN2–IN5, or VCC. The internal supply voltage, measured at VCC, equals the maximum of IN2–IN5. External capacitor is charged by IS_T when VS_T-DIS < VS_T < VS_T-ADJ. External capacitor is discharged by IS_T-DIS down to VS_T-DIS after VS_T reaches VS_T-ADJ. _______________________________________________________________________________________ mV mA Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors (VIN1 = VIN6–VIN8 = GND, VIN2–VIN5 = 2.7V to 5.5V, WDI = GND, TH0–TH4 = MARGIN = MR = DBP. Typical values are at TA = +25°C.) SUPPLY CURRENT vs. SUPPLY VOLTAGE (VCC) TA = +85°C 0.8 TA = +25°C TA = -40°C 0.6 3.0 3.5 4.0 4.5 5.0 5.5 0.9 0.8 0.7 2.5 3.0 3.5 4.0 4.5 5.0 -40 5.5 -15 10 35 85 60 TEMPERATURE (°C) IN_TO PG_ PROPAGATION DELAY vs. TEMPERATURE NORMALIZED DEFAULT RESET TIMEOUT PERIOD vs. TEMPERATURE NORMALIZED ADJUSTABLE RESET TIMEOUT PERIOD vs. TEMPERATURE 22 20 18 16 14 12 MAX6892 toc05 1.010 1.005 1.000 0.995 0.990 tRP = 200ms VSRT = VCC 0.985 0.980 -15 10 35 60 85 -15 10 35 60 NORMALIZED DEFAULT WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE NORMALIZED ADJUSTABLE WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE 1.01 1.00 0.99 0.98 tRP = 1.6s VSWT = VCC 0.97 0.96 10 35 TEMPERATURE (°C) 60 85 1.00 0.98 0.96 0.94 tRP = 200ms CSRT = 47nF MAX6892 toc08 1.15 1.10 1.05 1.00 0.95 0.90 tRP = 1.6s CSWT = 0.33µF 0.85 -40 -15 10 35 60 85 NORMALIZED IN_ THRESHOLD vs. TEMPERATURE 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 0.80 -15 1.02 TEMPERATURE (°C) 1.20 NORMALIZED WATCHDOG TIMEOUT PERIOD MAX6892 toc07 1.02 1.04 85 TEMPERATURE (°C) 1.03 1.06 0.90 -40 TEMPERATURE (°C) 1.04 1.08 0.92 NORMALIZED IN_ THRESHOLD 10 1.015 1.10 NORMALIZED RESET TIMEOUT PERIOD 24 1.020 NORMALIZED RESET TIMEOUT PERIOD MAX6892 toc04 26 -40 1.0 SUPPLY VOLTAGE (V) 100mV OVERDRIVE -40 MAX6892 toc03 MAX6892 toc02 TA = +25°C TA = -40°C 1.1 SUPPLY VOLTAGE (V) 30 IN_TO PG_ PROPAGATION DELAY (µs) 0.7 0.5 2.5 NORMALIZED WATCHDOG TIMEOUT PERIOD 0.8 0.6 0.5 28 TA = +85°C 1.2 MAX6892 toc06 0.7 0.9 1.3 MAX6892 toc09 0.9 1.0 SUPPLY CURRENT (mA) 1.0 SUPPLY CURRENT (mA) 1.1 MAX6892 toc01 1.1 NORMALIZED PG_ TIMEOUT PERIOD vs. TEMPERATURE NORMALIZED PG_ TIMEOUT PERIOD SUPPLY CURRENT vs. SUPPLY VOLTAGE (IN2–IN5) -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX6892/MAX6893/MAX6894 Typical Operating Characteristics Typical Operating Characteristics (continued) (VIN1 = VIN6–VIN8 = GND, VIN2–VIN5 = 2.7V to 5.5V, WDI = GND, TH0–TH4 = MARGIN = MR = DBP. Typical values are at TA = +25°C.) MAXIMUM IN_ TRANSIENT vs. IN_ THRESHOLD OVERDRIVE OUTPUT VOLTAGE LOW vs. SINK CURRENT 175 MAX6892 toc11 500 MAX6892 toc10 450 400 150 350 125 300 VOL (mV) MAXIMUM TRANSIENT DURATION (µs) 200 100 250 200 PG_ ASSERTION OCCURS 75 150 50 100 25 50 0 0 1 10 100 1000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IN_ THRESHOLD OVERDRIVE (mV) ISINK (mA) MR TO RESET PROPAGATION DELAY vs. TEMPERATURE RESET TIMEOUT PERIOD vs. CSRT 2.15 MAX6892 toc13 10,000 MAX6892 toc12 2.20 1000 2.10 TIMEOUT PERIOD (ms) MR TO RESET PROPAGATION DELAY (ns) 2.05 2.00 1.95 100 10 1.90 1 1.85 1.80 0.1 -40 -15 10 35 60 85 0.1 1 TEMPERATURE (°C) 10 100 1000 CSRT (nF) WATCHDOG TIMEOUT PERIOD vs. CSWT MAX6892 toc14 10,000 1000 TIMEOUT PERIOD (ms) MAX6892/MAX6893/MAX6894 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors 100 10 1 0.1 0.1 1 10 100 1000 CSWT (nF) 6 _______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors PIN NAME MAX6892 MAX6893 MAX6894 1 1 1 PG2 2 2 2 PG3 3 3 3 PG4 4 4 4 GND 5 5 — PG5 6 6 — PG6 7 — — PG7 8 — — PG8 9 7 7 RESET 10 8 8 WDO 11 9 9 MARGIN 12 10 10 MR 13 11 11 TH0 FUNCTION Open-Drain, Power-Good Output 2. PG2 asserts low when the voltage input at IN2 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG2 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 3. PG3 asserts low when the voltage input at IN3 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG3 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 4. PG4 asserts low when the voltage input at IN4 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG4 deasserts with a factory preset timeout period of 6.25ms. Ground Open-Drain, Power-Good Output 5. PG5 asserts low when the voltage input at IN5 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG5 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 6. PG6 asserts low when the voltage input at IN6 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG6 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 7. PG7 asserts low when the voltage input at IN7 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG7 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 8. PG8 asserts low when the voltage input at IN8 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG8 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Active-Low Reset Output Stage. RESET asserts low when any monitored input (IN_) is below the selected threshold or manual reset (MR) is pulled low. RESET remains low for the reset timeout period after all resetcausing conditions are cleared, and then deasserts. Open-Drain, Active-Low Watchdog Output Stage. If WDI remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and the WDO output asserts low. The internal watchdog timer clears whenever RESET is asserted or WDI sees a rising or falling edge. Connect WDO to MR to automatically assert the RESET output after each watchdog timeout fault. Margin Input. MARGIN holds PG_, RESET, and WDO in their existing states when driven low. Leave MARGIN unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same time. MARGIN is internally pulled up to DBP through a 10µA current source. Active-Low Manual Reset Input. Pull MR low to assert RESET. RESET remains asserted for its preset/adjustable reset timeout period when MR is driven/pulled high. MR is internally pulled up to DBP through a 10µA current source. Threshold Selection Input 0. Logic input to select desired thresholds. Connect TH0 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. _______________________________________________________________________________________ 7 MAX6892/MAX6893/MAX6894 Pin Description Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894 Pin Description (continued) PIN 8 NAME MAX6892 MAX6893 MAX6894 14 12 12 TH1 15 13 13 TH2 16 14 14 TH3 17 15 15 TH4 18 16 16 SWT 19 17 17 SRT 20 18 18 ENABLE 21 19 19 VCC 22 20 20 DBP 23 — — IN8 24 — — IN7 FUNCTION Threshold Selection Input 1. Logic input to select desired thresholds. Connect TH1 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Threshold Selection Input 2. Logic input to select desired thresholds. Connect TH2 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Threshold Selection Input 3. Logic input to select desired thresholds. Connect TH3 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Threshold Selection Input 4. Logic input to select desired thresholds. Connect TH4 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Watchdog Timeout Adjust Input. Connect SWT to VCC to select the default watchdog timeout period. Connect an external capacitor between SWT and GND to adjust the watchdog timeout period. The adjustable timeout period is calculated by tWP = 4.348E6 x CSWT (tWP in seconds and CSWT in Farads). Disable the watchdog timer by connecting SWT to GND. Reset Timeout Adjust Input. Connect SRT to VCC to select the default reset timeout period. Connect an external capacitor between SRT and GND to adjust the reset timeout period. The adjustable timeout period is calculated by tRP = 4.348E6 x CSWT (tRP in seconds and CSRT in Farads). Active-Low, PG_ Enable Input. Pull ENABLE high to force all PG_ outputs low. PG_ outputs remain asserted for their timeout period when ENABLE is driven/pulled low. ENABLE is internally pulled down to GND through a 10µA current sink. Internal Supply Voltage. Bypass VCC to GND with a 1µF capacitor as close to the device as possible. VCC supplies power to the internal circuitry. VCC is internally powered from the highest of the monitored IN2–IN5 voltages. Do not use VCC to supply power to external circuitry. To externally supply VCC, see the Powering the MAX6892/MAX6893/MAX6894 section). Digital Bypass Voltage. DBP supplies power to the output stages. Bypass DBP to GND with a 1µF capacitor as close to the device as possible. Do not use DBP to supply power to external circuitry. Input Voltage 8. Select undervoltage threshold using TH0–TH4. See Table 2. For improved noise immunity, bypass IN8 to GND with a 0.1µF capacitor as close to the device as possible. Input Voltage 7. Select undervoltage threshold using TH0–TH4. See Table 2. For improved noise immunity, bypass IN7 to GND with a 0.1µF capacitor as close to the device as possible. _______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors PIN NAME FUNCTION MAX6892 MAX6893 MAX6894 25 21 — IN6 26 22 — IN5 27 23 23 IN4 28 24 24 IN3 29 25 25 IN2 30 26 26 IN1 31 27 27 WDI 32 28 28 PG1 — — 5, 6, 21, 22 N.C. No Connection. Not internally connected. EP EP EP GND Exposed Paddle. Internally connected to GND. Connect EP to GND or leave floating. Input Voltage 6. Select undervoltage threshold using TH0–TH4. See Table 2. For improved noise immunity, bypass IN6 to GND with a 0.1µF capacitor as close to the device as possible. Input Voltage 5. Select undervoltage threshold using TH0–TH4. See Table 2. Power the device through IN2–IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN5 to GND with a 0.1µF capacitor as close to the device as possible. Input Voltage 4. Select undervoltage threshold using TH0–TH4. See Table 2. Power the device through IN2–IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN4 to GND with a 0.1µF capacitor as close to the device as possible. Input Voltage 3. Select undervoltage threshold using TH0–TH4. See Table 2. Power the device through IN2–IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN3 to GND with a 0.1µF capacitor as close to the device as possible. Input Voltage 2. Select undervoltage threshold using TH0–TH4. See Table 2. Power the device through IN2–IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN2 to GND with a 0.1µF capacitor as close to the device as possible. Input Voltage 1. Select undervoltage threshold using TH0–TH4. See Table 2. For improved noise immunity, bypass IN1 to GND with a 0.1µF capacitor as close to the device as possible. Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is not strobed with a valid low-to-high or high-to-low transition within the watchdog timeout period, the watchdog output asserts low. The watchdog timeout period is externally adjustable with capacitor CSWT or selectable for a fixed internal timeout period. The watchdog has a long timeout period (92.16s minimum fixed or 64x the adjusted short timeout period) after each reset event and a short timeout period (1.44s minimum or an adjusted timeout period) after the first valid WDI transition. Open-Drain, Power-Good Output 1. PG1 asserts low when the voltage input at IN1 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG1 deasserts with a factory preset timeout period of 6.25ms. _______________________________________________________________________________________ 9 MAX6892/MAX6893/MAX6894 Pin Description (continued) Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors ENABLE WOI MARGIN MR MAX6892/MAX6893/MAX6894 Functional Diagram IN_ DETECTOR IN2 PG_ OUTPUT OPEN-DRAIN ACTIVE-LOW PG1 10µA POWER-UP PULLDOWN VREF SWT IN2 DETECTOR IN3 IN3 DETECTOR IN4 IN4 DETECTOR IN5* IN5 DETECTOR IN6* IN6 DETECTOR IN7** IN7 DETECTOR IN8** IN8 DETECTOR (VIRTUAL DIODES) 2.55V LDO DBP LOGIC ARRAY IN1 PG2 OUTPUT SRT DBP PG2 PG3 OUTPUT PG3 PG4 OUTPUT PG4 PG5 OUTPUT PG5* PG6 OUTPUT PG6* PG7 OUTPUT PG7** PG8 OUTPUT PG8 WDO OUTPUT WDO RESET OUTPUT RESET TH0 DBP TH1 1µF VCC 1µF MAX6892 MAX6893 MAX6894 GND 10 THRESHOLD SELECTION LOGIC TH2 TH3 TH4 * FOR MAX6892/MAX6893 ONLY. ** FOR MAX6892 ONLY. ______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors The MAX6892/MAX6893/MAX6894 pin-selectable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and one watchdog input, asserting the outputs when the respective input thresholds have been reached or a timeout occurs. All versions have an enable manual reset and margin input disable. The MAX6892/MAX6893/MAX6894 voltage thresholds are selected by logic inputs and/or an external voltage-divider. A RESET output ensures all monitored inputs are above the pin-selected/adjustable thresholds. Watchdog and reset timeout periods can use factory default settings or are independently adjustable by connecting external capacitors. In addition, all devices can be powered through the voltage detector inputs alone, or externally supplied from a constant supply on the VCC pin (see the Powering the MAX6892/MAX6893/MAX6894 section). The outputs are factory configured as open drain. Powering the MAX6892/MAX6893/MAX6894 The MAX6892/MAX6893/MAX6894 derive power from the voltage detector inputs: IN2–IN5 (MAX6892/ MAX6893), IN2–IN4 (MAX6894), or through an externally supplied VCC. A virtual diode-ORing scheme selects the positive input that supplies power to the device (see the Functional Diagram). The highest input voltage on IN2–IN5 (MAX6892/MAX6893)/IN2–IN4 (MAX6894) supplies power to the device. One of IN2–IN5 (MAX6889/MAX6890)/IN2–IN4 (MAX6891) or VCC must be at least 2.7V to ensure proper operation. Internal hysteresis ensures that the supply input that initially powered the device continues to power the device when multiple input voltages are within 50mV of each other. VCC powers the analog circuitry and is the bypass connection for the MAX6892/MAX6893/MAX6894 internal supply. Bypass VCC to GND with a 1µF ceramic capacitor installed as close to the device as possible. The internal supply voltage, measured at VCC, equals the maximum of IN2–IN5. If VCC is externally supplied, VCC must be at least 200mV higher than any voltage applied to IN2–IN5 and VCC must be brought up first. VCC always powers the device when all IN_ are factory set as “ADJ.” Do not use the internally generated VCC to provide power to external circuitry. The MAX6892/MAX6893/MAX6894 also generate a digital supply voltage (DBP) for the internal logic circuitry and the output stages. Bypass DBP to GND with a 1µF ceramic capacitor installed as close to the device as possible. The nominal DBP output voltage is 2.55V. Do not use DBP to provide power to external circuitry. Inputs The MAX6892/MAX6893/MAX6894 contain multiple logic and voltage detector inputs. Each voltage detector input is monitored for undervoltage thresholds. Voltage Detector Inputs (IN_) The MAX6892/MAX6893/MAX6894 offer several monitor options with both pin-selectable and adjustable reset thresholds. The threshold voltage at each adjustable IN_ input is typically 0.6V. To monitor a voltage >0.6V, connect a resistor-divider network to the circuit as shown in Figure 1: VIN_TH = VTH (R1 + R2) / R2 (Equation 1) where VIN_TH is the desired reset threshold voltage for the respective IN_ and V TH is the input threshold (0.6V). Resistors R1 and R2 can have high values to minimize current consumption due to low-leakage currents. Set R2 to some conveniently high value (10kΩ, for example) and calculate R 1 based on the desired reset threshold voltage, using the following formula: R1 = R2 x (VIN_TH/VTH - 1) VIN_TH VCC R1 IN_ R2 MAX6892 MAX6893 MAX6894 VCC GND VIN_TH = 0.6 x (R1 + R2) / R2 Figure 1. Adjusting the Monitored Threshold ______________________________________________________________________________________ 11 MAX6892/MAX6893/MAX6894 Detailed Description MAX6892/MAX6893/MAX6894 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors Threshold Logic Inputs (TH0–TH4) The TH0–TH4 logic inputs select the undervoltage thresholds and tolerance of the IN1–IN8 inputs (MAX6892), IN1–IN6 inputs (MAX6893), and IN1–IN4 inputs (MAX6894). TH0–TH4 define 32 unique options for the supervisor functionality. Connect the respective TH_ to GND for a logic 0 or to DBP for a logic 1. Tables 1 and 2 show the 32 unique threshold options available. TH4 sets the threshold tolerance of the undervoltage threshold. A logic 1 selects a 5% supply tolerance and a logic 0 selects 10% supply tolerance. The MAX6892/MAX6893/ MAX6894 logic determines which thresholds should be used for the IN inputs only at power-up. Use the voltagedivider circuit of Figure 1 and Equation 1 to set the threshold for the user-adjustable inputs as described in the Voltage Detector Inputs (IN_) section. Table 1. Nominal Monitored Supply Voltages IN2 IN3 IN4 IN5 IN6 IN7 IN8 SUPPLY TOLERANCE (%) 11111 ADJ 5 3.3 2.5 1.8 ADJ ADJ ADJ 5 2 11110 ADJ 5 3 2.5 1.8 ADJ ADJ ADJ 5 3 11101 ADJ 5 3.3 2.5 ADJ ADJ ADJ ADJ 5 4 11100 ADJ 5 3 2.5 ADJ ADJ ADJ ADJ 5 5 11011 ADJ 5 3.3 1.8 ADJ ADJ ADJ ADJ 5 6 11010 ADJ 5 3 1.8 ADJ ADJ ADJ ADJ 5 7 11001 ADJ 5 3.3 ADJ ADJ ADJ ADJ ADJ 5 8 11000 ADJ 5 3 ADJ ADJ ADJ ADJ ADJ 5 9 10111 ADJ 3.3 2.5 1.8 ADJ ADJ ADJ ADJ 5 10 10110 ADJ 3 2.5 1.8 ADJ ADJ ADJ ADJ 5 TH4–TH0 1 12 MONITORED SUPPLY VOLTAGES (V) IN1 SELECTION 11 10101 ADJ 3.3 2.5 ADJ ADJ ADJ ADJ ADJ 5 12 10100 ADJ 3 2.5 ADJ ADJ ADJ ADJ ADJ 5 13 10011 ADJ 3.3 1.8 ADJ ADJ ADJ ADJ ADJ 5 14 10010 ADJ 3 1.8 ADJ ADJ ADJ ADJ ADJ 5 15 10001 ADJ 3.3 2.5 1.8 1.5 ADJ ADJ ADJ 5 16 10000 ADJ 3 2.5 1.8 1.5 ADJ ADJ ADJ 5 17 01111 ADJ 5 3.3 2.5 1.8 ADJ ADJ ADJ 10 18 01110 ADJ 5 3 2.5 1.8 ADJ ADJ ADJ 10 19 01101 ADJ 5 3.3 2.5 ADJ ADJ ADJ ADJ 10 20 01100 ADJ 5 3 2.5 ADJ ADJ ADJ ADJ 10 21 01011 ADJ 5 3.3 1.8 ADJ ADJ ADJ ADJ 10 22 01010 ADJ 5 3 1.8 ADJ ADJ ADJ ADJ 10 23 01001 ADJ 5 3.3 ADJ ADJ ADJ ADJ ADJ 10 24 01000 ADJ 5 3 ADJ ADJ ADJ ADJ ADJ 10 25 00111 ADJ 3.3 2.5 1.8 ADJ ADJ ADJ ADJ 10 26 00110 ADJ 3 2.5 1.8 ADJ ADJ ADJ ADJ 10 27 00101 ADJ 3.3 2.5 ADJ ADJ ADJ ADJ ADJ 10 28 00100 ADJ 3 2.5 ADJ ADJ ADJ ADJ ADJ 10 29 00011 ADJ 3.3 1.8 ADJ ADJ ADJ ADJ ADJ 10 30 00010 ADJ 3 1.8 ADJ ADJ ADJ ADJ ADJ 10 31 00001 ADJ 3.3 2.5 1.8 1.5 ADJ ADJ ADJ 10 32 00000 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ — ______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894 Table 2. Threshold Options SELECTION TH4–TH0* 1 THRESHOLD VOLTAGES (V) IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 11111 0.60 4.62 3.06 2.31 1.67 0.60 0.60 0.60 2 11110 0.60 4.62 2.78 2.31 1.67 0.60 0.60 0.60 3 11101 0.60 4.62 3.06 2.31 0.60 0.60 0.60 0.60 4 11100 0.60 4.62 2.78 2.31 0.60 0.60 0.60 0.60 5 11011 0.60 4.62 3.06 1.67 0.60 0.60 0.60 0.60 6 11010 0.60 4.62 2.78 1.67 0.60 0.60 0.60 0.60 7 11001 0.60 4.62 3.06 0.60 0.60 0.60 0.60 0.60 8 11000 0.60 4.62 2.78 0.60 0.60 0.60 0.60 0.60 9 10111 0.60 3.06 2.31 1.8 0.60 0.60 0.60 0.60 10 10110 0.60 2.78 2.31 1.8 0.60 0.60 0.60 0.60 11 10101 0.60 3.06 2.31 0.60 0.60 0.60 0.60 0.60 12 10100 0.60 2.78 2.31 0.60 0.60 0.60 0.60 0.60 13 10011 0.60 3.06 1.67 0.60 0.60 0.60 0.60 0.60 14 10010 0.60 2.78 1.67 0.60 0.60 0.60 0.60 0.60 15 10001 0.60 3.06 2.31 1.67 1.39 0.60 0.60 0.60 16 10000 0.60 2.78 2.31 1.67 1.39 0.60 0.60 0.60 17 01111 0.60 4.38 2.88 2.19 1.58 0.60 0.60 0.60 18 01110 0.60 4.38 2.62 2.19 1.58 0.60 0.60 0.60 19 01101 0.60 4.38 2.88 2.19 0.60 0.60 0.60 0.60 20 01100 0.60 4.38 2.62 2.19 0.60 0.60 0.60 0.60 21 01011 0.60 4.38 2.88 1.58 0.60 0.60 0.60 0.60 22 01010 0.60 4.38 2.62 1.58 0.60 0.60 0.60 0.60 23 01001 0.60 4.38 2.88 0.60 0.60 0.60 0.60 0.60 24 01000 0.60 4.38 2.62 0.60 0.60 0.60 0.60 0.60 25 00111 0.60 2.88 2.19 1.8 0.60 0.60 0.60 0.60 26 00110 0.60 2.62 2.19 1.8 0.60 0.60 0.60 0.60 27 00101 0.60 2.88 2.19 0.60 0.60 0.60 0.60 0.60 28 00100 0.60 2.62 2.19 0.60 0.60 0.60 0.60 0.60 29 00011 0.60 2.88 1.58 0.60 0.60 0.60 0.60 0.60 30 00010 0.60 2.62 1.58 0.60 0.60 0.60 0.60 0.60 31 00001 0.60 2.88 2.19 1.58 1.31 0.60 0.60 0.60 32 00000 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 *TH4 = ‘1’ selects 7.5% threshold tolerance, TH4= ‘0’ selects 12.5% threshold tolerance. Contact factory for alternative thresholds. ______________________________________________________________________________________ 13 MAX6892/MAX6893/MAX6894 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors Watchdog Timer The MAX6892/MAX6893/MAX6894s’ watchdog circuit monitors the microprocessor’s (µP’s) activity. If the µP does not toggle the watchdog input (WDI) within the watchdog timeout period, the watchdog output (WDO) asserts. The internal watchdog timer is cleared by RESET, or by a transition at WDI (which can detect pulses as short as 50ns). The watchdog timer remains cleared while reset is asserted. The timer starts counting as soon as WDO is released (see Figure 2). The MAX6892/MAX6893/MAX6894 feature two modes of watchdog timer operation: normal mode and initial mode. At power-up, after a reset event, or after the watchdog timer expires, the initial watchdog timeout is active. After the first transition on WDI, the normal watchdog timeout is active. The initial and normal watchdog timeouts are determined by the value of the capacitor connected between SWT and ground or by connecting SWT to VCC (see the Selecting the Reset and Watchdog Timeout Capacitor section). The initial watchdog timeout is approximately 64 times the normal watchdog timeout. For example, in initial mode a 1µF capacitor gives a watchdog timeout period of about 5min. If WDO is connected to MR, the WDO asserts for a short duration (~5µs), long enough to assert the RESET output. Asserting RESET clears the watchdog timer and WDO goes high. The reset output remains asserted for its timeout period after a watchdog fault. The watchdog timer stays cleared as long as RESET is low. The watchdog timeout period is determined by the value of the capacitor connected between SWT and ground (see the Selecting the Reset/Watchdog Timeout Capacitor section). Connect SWT to DBP to select factory-programmed watchdog timeout. To disable the watchdog timer connect SWT to GND. 2.5V VCC OR IN2–IN5 WDO RESET WDI tD-PO tRP *tWDI tWD WDO NOT CONNECTED TO MR *tWDI tD-PO tRP *tWDI tWD WDO CONNECTED TO MR. *tWDI 2.5V VCC OR IN2–IN5 WDO RESET WDI *tWDI IS THE INITIAL WATCHDOG TIMEOUT PERIOD. tRP Figure 2. Watchdog, Reset, and Power-Up Timing Diagram 14 ______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors Margin Output Disable (MARGIN) MARGIN allows system-level testing while power supplies exceed the normal ranges. Driving MARGIN low forces PG_, RESET, and WDO to hold the last state while system-level testing occurs. Leave MARGIN unconnected or connect to DBP if unused. An internal 10µA current source pulls MARGIN to DBP. The state of each programmable output, RESET, and WDO does not change while MARGIN = GND. Enable Input ENABLE is an active-high, logic input. Driving ENABLE high pulls all PG_ low. Drive ENABLE high or leave floating for normal operation. ENABLE is internally pulled down to GND through a 10µA current sink. Power-Good Outputs The MAX6892 features eight power-good outputs, the MAX6893 features six power-good outputs, and the MAX6894 features four power-good outputs. Each output (PG_) responds to its respective input (IN_). Each PG_ is open drain. During power-up, the outputs pull down to GND with an internal 10µA current sink for 1V < VCC < VUVLO. RESET changes from high to low whenever one or more input voltage (IN1–IN8) monitors drop below their respective reset threshold voltage or when MR is pulled low for a minimum of 1µs. Once the affected input voltage monitor(s) exceeds its respective reset threshold voltage(s), RESET remains low for the reset timeout period, then deaaserts. Applications Information Selecting the Reset/Watchdog Timeout Capacitor The reset timeout period can be adjusted to accommodate a variety of µP applications. Adjust the reset timeout period (t RP ) by connecting a capacitor (CSRT ) between SRT and ground. Calculate the reset timeout capacitor as follows: CSRT = tRP / (4.348 x 106) with tRP in seconds and CSRT in Farads. Connect SRT to V CC for a factory-programmed reset timeout of 200ms (typ). The watchdog timeout period can be adjusted to accommodate a variety of µP applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWD) by connecting a specific value capacitor (C SWT) between SWT and GND. For normal mode operation, calculate the watchdog timeout capacitor as follows: CSWT = tWD / (4.348 x 106) with tWD in seconds and CSWT in Farads. Connect SWT to VCC for a factory-programmed watchdog timeout of 1.6s (normal mode) and 102.4s (initial mode). CSRT and CSWT must be a low-leakage (<10nA) type capacitor. Ceramic capacitors are recommended. RESET Output Layout and Bypassing The reset output is typically connected to the reset input of a µP. A µP’s reset input starts or restarts the µP in a known state. The MAX6892/MAX6893/MAX6894 supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions. For better noise immunity, bypass each of the voltage detector inputs to GND with 0.1µF capacitors installed as close to the device as possible. Bypass VCC and DBP to GND with 1µF capacitors installed as close to the device as possible. ______________________________________________________________________________________ 15 MAX6892/MAX6893/MAX6894 Manual Reset (MR) Many µP-based products require manual reset capability to allow an operator or external logic circuitry to initiate a reset. The manual reset input (MR) can connect directly to a switch without an external pullup resistor or debouncing network. MR is internally pulled up to DBP through a 10µA current source and, therefore, can be left unconnected if unused. MR is designed to reject fast falling transients (typically 100ns pulses) and it must be held low for a minimum of 1µs to assert RESET. After MR transitions from low to high, RESET remains asserted for the duration of the reset timeout period. Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors 22 N.C. IN5 23 IN4 IN4 24 IN3 IN3 25 IN2 IN2 26 IN1 IN1 27 WDI WDI 28 TOP VIEW PG1 PG1 TOP VIEW 28 27 26 25 24 23 22 1 21 IN6 PG2 1 21 N.C. 2 20 DBP PG3 2 20 DBP 3 19 VCC PG4 3 19 VCC GND 4 18 ENABLE GND 4 18 ENABLE PG5 5 17 SRT N.C. 5 17 SRT PG6 6 16 SWT N.C. 6 16 SWT RESET 7 15 TH4 8 9 10 11 12 13 14 TH3 14 TH2 13 TH1 12 TH0 11 MR 10 TH3 9 TH2 8 TH4 *EXPOSED PADDLE MARGIN 15 7 MAX6894 WDO *EXPOSED PADDLE TH1 RESET MAX6893 TH0 PG4 MR PG3 MARGIN PG2 WDO MAX6892/MAX6893/MAX6894 Pin Configuration (continued) THIN QFN THIN QFN *EXPOSED PAD INTERNALLY CONNECTED TO GND. *EXPOSED PAD INTERNALLY CONNECTED TO GND. Chip Information PROCESS: BiCMOS 16 ______________________________________________________________________________________ Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors 5V 5V DC-DC 1 3.3V DC-DC 2 VCC IN1 IN2 IN3 PG2 PG3 2.5V DC-DC 3 IN4 PG4 1.8V DC-DC 4 IN5 PG5 1.5V IN6 RESET WDI WDO DBP TH0 MAX6893 µP RESET LOGIC OUTPUT LOGIC INPUT MARGIN TH1 TH2 TH3 MR TH4 ENABLE SRT SWT CSRT tPG2 3.3V OUTPUT tPG3 ENABLE 2.5V DC-DC CONVERTER 2.5V OUTPUT 2.5V SUPPLY tPG4 PG4 1.8V SUPPLY 1.5V SUPPLY RESET ENABLE 1.8V DC-DC CONVERTER 1.8V OUTPUT tPG5 PG5 CSWT ENABLE 3.3V DC-DC CONVERTER 3.3V SUPPLY PG3 GND 5V BUS INPUT 5V SUPPLY PG2 PG1 PG6 ENABLE 1.5V DC-DC CONVERTER 1.5V OUTPUT tRESET SYSTEM RESET ______________________________________________________________________________________ 17 MAX6892/MAX6893/MAX6894 Typical Operating Circuit Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX6892/MAX6893/MAX6894 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors D2 D MARKING b C L 0.10 M C A B D2/2 D/2 k L XXXXX E/2 E2/2 C L (NE-1) X e E DETAIL A PIN # 1 I.D. E2 PIN # 1 I.D. 0.35x45∞ e (ND-1) X e DETAIL B e L1 L C L C L L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 18 21-0140 ______________________________________________________________________________________ G 1 2 Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors COMMON DIMENSIONS EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 A3 b D E L1 0 0.02 0.05 0 0.20 REF. 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 e k L 0.02 0.05 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 - - - - - N ND NE 16 4 4 20 5 5 JEDEC WHHB WHHC - - - - - 28 7 7 WHHD-1 - - 32 8 8 WHHD-2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. D2 L E2 PKG. CODES MIN. NOM. MAX. MIN. NOM. MAX. ±0.15 T1655-1 T1655-2 T1655N-1 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 3.10 3.20 T2055-2 T2055-3 T2055-4 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 3.10 3.20 ** ** ** ** T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 ** ** 0.40 DOWN BONDS ALLOWED NO YES NO NO YES NO Y ** NO NO YES YES NO ** ** 0.40 ** ** ** ** ** NO YES Y N NO YES NO NO ** ** ** ** ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- G 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX6892/MAX6893/MAX6894 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)