MAXIM MAX9476

19-3530; Rev 0; 1/05
KIT
ATION
EVALU
E
L
B
AVAILA
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
The MAX9476 low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six
buffered LVTTL clock outputs at 35.328MHz. The clock
synthesizer can be used to generate the clocks for systems using T1, E1, T3, E3, and xDSL.
The MAX9476 features a phase-lock loop (PLL) that uses
a voltage-controlled crystal oscillator (VCXO). The internal PLL phase locks the external crystal (35.328MHz) to
the 8kHz input reference clock. In addition, this device
generates a jitter-suppressed output that provides a better source for the reference clock relay.
The MAX9476 is available in a 24-pin TSSOP package
and operates over the extended operating temperature
range of -40°C to +85°C and a single +3V to +3.6V
power-supply range. For using lower value external
crystals, refer to the MAX9486 data sheet.
Features
♦ 8kHz Input-Reference CLK
♦ 4psRMS (typ) Output Jitter
♦ High-Jitter Rejection on the Reference CLK
♦ Synthesizer Locks to the 8kHz Reference with a
±100ppm Range
♦ Output Frequency: 35.328MHz
♦ Six Buffered LVTTL Low-Jitter Outputs
♦ One 8kHz Reference CLK Relay Output
♦ +3.3V Supply Operation
♦ 24-Pin TSSOP Package
Ordering Information
Applications
Telecom Equipment Using T1, E1, T3, E3, and
ISDN Protocols
xDSL Equipment in CO with Interface to the
Telecom Protocols
PART
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX9476EUG
-40°C to +85°C
24 TSSOP
U24-1
Pin Configuration
Typical Application Circuit
TOP VIEW
C1
R1
SHDN 1
24 CLK1
REO 2
23 GND
REIN 3
22 CLK2
VDDP 4
GNDP 5
C2
LP1
21 VDD
MAX9476
20 CLK3
X1 6
19 VDD
VDD 7
18 GND
X2 8
17 CLK4
LP2
X1
X2
VDDP
VDD
SETI
CLK1
CLK2
RSET
MAX9476
GNDP
GND 9
16 VDD
LP2 10
15 CLK5
LP1 11
14 GND
SHDN
SETI 12
13 CLK6
REIN
CLK3
CLK4
CLK5
VDD
CLK6
GND
REO
TSSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9476
General Description
MAX9476
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +4.0V
VDDP to GNDP.......................................................-0.3V to +4.0V
SHDN, REO, REIN, X1, X2, CLK_ to GND ...-0.3V to (VDD + 0.3V)
LP1, SETI to GNDP.....................................-0.3V to (VDD + 0.3V)
LP2 Internally Connected to GNDP
Short-Circuit Duration of Outputs ...............................Continuous
Continuous Power Dissipation (TA = +70°C)
24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......976mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
ESD Rating (Human Body Model) .......................................±2kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDD = VDDP = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDP = +3.3V, TA =
+25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
DIGITAL INPUTS (REIN, SHDN)
Input-High Logic Level
VIH
Input-Low Logic Level
VIL
2.0
Input-Current High Level
IIH
VIN = VDD
Input-Current Low Level
IIL
VIN = 0
V
20
µA
-20
µA
VDD 0.6V
V
DIGITAL OUTPUT CLOCKS (CLK1–CLK6, REO)
Output-High Logic Level
VOH
IOH = -4mA
Output-Low Logic Level
VOL
IOL = 4mA
0.4
V
3.6
V
POWER SUPPLY (VDD, VDDP)
Power-Supply Range
PLL Power-Supply Range
Power-Supply Current
Shutdown Supply Current
2
VDD
3.0
VDDP
IDD + IDDP
ISHDN
3.0
(Note 2)
3.6
V
9
16
mA
7.5
30
µA
_______________________________________________________________________________________
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
(VDD = VDDP = +3.0V to +3.6V, CL = 20pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDP = +3.3V,
TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUT CLOCKS (CLK1–CLK6)
Frequency Range
fOUT
Clock Rise Time
tR1
20% to 80% VDD
Clock Fall Time
tF1
80% to 20% VDD
Duty Cycle
Period Jitter
Output Skew
Peak-to-peak
JP2
RMS
tS
MHz
1.8
ns
1.8
40
JP1
35.328
Peak-to-peak
50
ns
60
%
83
ps
4
psRMS
185
ps
REFERENCE CLOCK OUTPUT (REO)
Frequency
fREF
8
kHz
Clock Rise Time
tR2
1.8
ns
Clock Fall Time
tF2
1.8
ns
Duty Cycle
40
50
60
%
VCXO
Crystal Frequency
fXTL
Crystal Accuracy
Including frequency accuracy and
temperature range
VCXO Pulling Range
(Note 4)
Input Reference CLK Pulse Width
Note 1:
Note 2:
Note 3:
Note 4:
tW
Measured at high or low states
-100
10
35.328
MHz
±25
ppm
+100
ppm
ns
Specifications are 100% tested at TA = +25°C. Specifications over temperature are guaranteed by design and characterization.
No load on clock outputs.
Guaranteed by design.
Crystal loading capacitance is 14pF.
_______________________________________________________________________________________
3
MAX9476
AC ELECTRICAL CHARACTERISTICS
Typical Operating Characteristics
(VDD = VDDP = +3.3V, TA = +25°C, unless otherwise noted.)
OUTPUT CLOCK JITTER (P-P)
vs. TEMPERATURE
7
MAX9476 toc02
140
130
120
6
OUTPUT CLOCK JITTER (ps)
OUTPUT CLOCK JITTER (ps)
150
110
100
90
80
70
60
50
40
60
50
60
40
-40
85
3.1
3.2
3.3
3.4
3.5
3.6
MAX9476 toc05
4
3
2
3.1
SUPPLY VOLTAGE (V)
125
3.2
3.3
3.4
SUPPLY CURRENT (IDD + IDDP)
vs. SUPPLY VOLTAGE
75
25
0
-50
-75
-100
-125
7.9990
3.6
TA = +25°C
10
7.9994 7.9998 8.0002 8.0006 8.0010
INPUT REFERENCE FREQUENCY (kHz)
8
TA = -40°C
MAX9476 toc08
11
TA = +85°C
10
TA = +25°C
9
8
7
TA = -40°C
6
6
5
4
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
4
3.5
3.6
3.0
3.1
3.2
3.3
85
-25
12
SUPPLY CURRENT (µA)
TA = +85°C
3.0
60
CENTERED AT
35.328MHz
50
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9476 toc07
14
SUPPLY CURRENT (mA)
3.5
100
SUPPLY VOLTAGE (V)
12
35
OUTPUT FREQUENCY VARIATION
vs. INPUT REFERENCE FREQUENCY
5
3.0
10
OUTPUT CLOCK JITTER (RMS)
vs. SUPPLY VOLTAGE
0
3.0
-15
TEMPERATURE (°C)
1
30
2
TEMPERATURE (°C)
6
OUTPUT CLOCK JITTER (ps)
70
35
7
MAX9476 toc04
80
10
OUTPUT FREQUENCY VARIATION (ppm)
OUTPUT CLOCK JITTER (P-P)
vs. SUPPLY VOLTAGE
90
3
0
-15
-40
100
4
1
30
10ns/div
5
MAX9476 toc06
MAX9476 toc01
OUTPUT CLOCK JITTER (RMS)
vs. TEMPERATURE
MAX9476 toc03
OUTPUT WAVEFORM
OUTPUT CLOCK JITTER (ps)
MAX9476
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
PIN
NAME
FUNCTION
1
SHDN
2
REO
Reference Clock Output. REO is an 8kHz reference clock output with jitter suppression.
3
REIN
Reference Input
4
VDDP
Phase-Lock Loop (PLL) Power Supply. Bypass VDDP with 0.1µF and 0.001µF capacitors to GNDP.
5
GNDP
6
X1
7, 16, 19,
21
VDD
8
X2
9, 14, 18,
23
GND
Ground
10
LP2
External Filter 2. Connect the loop filter capacitors and a resistor between LP1 and LP2 (see the Typical
Application Circuit). LP2 is internally connected to GNDP.
11
LP1
External Filter 1. Connect the loop filter capacitors and a resistor between LP1 and LP2 (see the Typical
Application Circuit).
12
SETI
Charge-Pump Current-Setting Input. Connect a resistor from SETI to GNDP to set PLL charge-pump current
(see the Detailed Description section).
13
CLK6
Clock Output 6 at 35.328MHz
15
CLK5
Clock Output 5 at 35.328MHz
17
CLK4
Clock Output 4 at 35.328MHz
20
CLK3
Clock Output 3 at 35.328MHz
22
CLK2
Clock Output 2 at 35.328MHz
24
CLK1
Clock Output 1 at 35.328MHz
Active-Low Shutdown Input
PLL Ground
Crystal Input 1. Connect X1 to a fundamental mode crystal for the VCXO.
Digital Power Supply. Bypass VDD with 0.1µF and 0.001µF capacitors to GND.
Crystal Input 2. Connect X2 to a fundamental mode crystal for the VCXO.
_______________________________________________________________________________________
5
MAX9476
Pin Description
MAX9476
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
Functional Diagram
LP1
X1
LP2
X2
VDDP
GNDP
CLK1
SETI
REIN
PHASE DETECTOR
AND
CHARGE PUMP
CLK2
VCXO
CLK3
PLL
CLK4
/4416
CLK5
CLK6
SHDN
REFERENCE CLK
MONITOR
MAX9476
REO
VDD
GND
Detailed Description
The MAX9476 is a high-performance clock synthesizer
with an 8kHz input reference clock. This device generates six identical buffered LVTTL clock outputs at
35.328MHz. The internal PLL phase locks the external
crystal (35.328MHz) to the 8kHz input reference clock.
This device features a low-jitter output that provides a
better source for the reference clock relay (see the
Functional Diagram).
Power-Up
At power-up, all the outputs are disabled and pulled low
(to GND) for at least 256ms. After 256ms, the crystal
oscillator starts oscillation. If the reference clock is not
present at power-up, the outputs are forced to the center frequency of the crystal oscillator.
Reference CLK Monitor
The MAX9476 features internal clock (CLK) monitor circuitry to detect the presence of the external 8kHz reference clock. The internal CLK monitor continuously
monitors the number of low-to-high transitions within a
three-cycle (at 8kHz) time window. If the transition number is less than two, the internal CLK monitor states loss
6
of the reference CLK. However, if in a three-cycle time
window the monitor counts two or three transitions, it
considers the input reference clock as present. When
the monitor detects the absence of the 8kHz reference
clock, the outputs are operating at the center frequency
of the crystal oscillator. However, when the monitor
detects the return of the reference clock, the PLL locks
to the reference clock. The ratio between the external
crystal and the input reference clock is 4416.
Clock Outputs (CLK1 to CLK6) and REO
The MAX9476 uses a 35.328MHz crystal and a reference clock (REIN) to generate six identical outputs,
CLK1 to CLK6, at 35.328MHz. All CLK_ outputs are
LVTTL with a typical skew of 185ps. The MAX9476 also
regenerates the 8kHz reference CLK at REO output.
Voltage-Controlled Crystal
Oscillator (VCXO)
The MAX9476’s internal VCXO takes an external
35.328MHz crystal as the base frequency and has a
pulling range of approximately ±100ppm. This configuration also makes the VCXO PLL become a narrowband
filter to reject high-frequency jitter on the input reference
and eliminate it from the REO and CLK_ outputs.
SHDN Mode
The MAX9476 features a shutdown mode with a supply
current of 7.5µA (typ). Drive SHDN low to get the
device into shutdown mode. In this mode, all the outputs go low and the PLL is powered down. After SHDN
goes high, the outputs still stay low for an additional
256ms to allow the PLL to be stabilized before the outputs are enabled again.
Applications Information
Crystal Selection
The MAX9476 uses a 35.328MHz crystal as the base
frequency for the VCXO. It is important to use a correct
type of quartz crystal to avoid reducing frequency
pulling range, or excessive output phase jitter.
Choose an AT-cut crystal that oscillates at 35.328MHz
on its fundamental mode with a variation of ±25ppm
including frequency accuracy and operating temperature range. The crystal’s load capacitance should be
14pF. Pulling range may vary depending on the crystal
used. Refer to the MAX9476 evaluation kit for details.
_______________________________________________________________________________________
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
Use the following equation to calculate a PLL loop
bandwidth in Hz:
BW = (R1 x ISETI x 1405) / N
where R1 (Ω) is the resistor in the PLL loop filter (Figure
1), ISETI (A) is the charge-pump current calculated from
the equation in the Charge-Pump Current Setting section,
and N is the crystal PLL frequency divider equal to 4416.
The loop-damping factor is calculated by:
R
DampingFactor = 1 ×
2
8832 × ISETI × C1
N
where C1 (F) and R1 (Ω) are the values of the capacitor
and the resistor in the PLL loop filter shown in
Figure 1; ISETI is calculated as shown in the ChargePump Current Setting section and N = 4416.
The following equation shows the relationship between
components C1 and C2 in the loop filter:
C2 ≤ C1 / 20
Charge-Pump Current Setting
The MAX9476 also allows external setting of the chargepump current in the PLL. Connect a resistor from SETI
to GNDP to set the PLL charge-pump current:
Charge-Pump Current = 2.4 x 1000 / (RSET(kΩ) + 1)
MAX9476
PLL Loop Filter
The PLL contains an integrated VCXO that uses an
external crystal to track the input reference signal and
attenuate input jitter. Figure 1 shows the external loop
filter of the PLL containing resistor R1 and two capacitors, C1 and C2. This loop filter is connected between
LP1 and LP2 as shown in the Typical Operating Circuit.
The loop-filter bandwidth is determined by C1, C2, R1,
and RSET where RSET is used to set the value of the
charge-pump current. The typical values of C1, C2, R1,
and RSET are 22nF, 560pF, 1000kΩ, and 13kΩ, respectively.
LP1
R1
C2
C1
LP2
Figure 1. Typical Loop Filter
where RSET is in kΩ and the value of the charge-pump
current is in µA.
The loop response can be adjusted to meet individual
application requirements since the charge-pump current and all the filter components for the VCXO loop
can be set externally.
Board Layout and Bypassing
The MAX9476’s high oscillator frequency makes proper
layout important to ensure stability. For best performance,
place components as close as possible to the device.
Digital or AC transient signals on GND can create noise
at the clock outputs. Return GND to the highest quality
ground available. Bypass V DD and VDDP with 0.1µF
and 0.001µF capacitors, placed as close to the device
as possible. Careful PC board ground layout minimizes
crosstalk between the outputs and digital inputs.
Traces must be as short as possible on LP1 and LP2
and connect the capacitors and the resistor as close as
possible to the device.
Chip Information
TRANSISTOR COUNT: 7512
PROCESS: CMOS
_______________________________________________________________________________________
7
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9476
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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Printed USA
is a registered trademark of Maxim Integrated Products, Inc.