19-3942; Rev 0; 1/06 Factory-Programmable, Single PLL Clock Generator The MAX9491 multipurpose clock generator is ideal for communication applications. It offers a factory-programmable PLL output that can be set to almost any frequency, ranging from 4MHz to 200MHz. The MAX9491 uses a one-time-programmable (OTP) ROM to program the PLL output. The MAX9491 also features an integrated voltage-controlled crystal oscillator (VCXO) that is tuned by a DC voltage. The VCXO output is used as the PLL input. The VCXO has a wide ±200ppm (typ) tuning range. The OTP on the MAX9491 is factory preset, based upon the customer request. Contact the factory for samples with preferred frequencies. The device operates from a 3.3V supply and is specified over the -40°C to +85°C extended temperature range. The MAX9491 is available in 14-pin TSSOP and 20-pin TQFN (5mm x 5mm) packages. Features ♦ 5MHz to 35MHz for Crystal-Clock Reference ♦ 5MHz to 50MHz for a Driver Clock Reference ♦ One Fractional-N PLL with Buffered Output ♦ 4MHz to 200MHz Output Frequency Range ♦ Low RMS Jitter PLL (< 13ps) at 197 MHz ♦ Integrated VCXO with ±200ppm Tuning Range ♦ Available in 14-Pin TSSOP and 20-Pin TQFN Packages ♦ +3.3V Supply ♦ -40°C to +85°C Temperature Range Ordering Information Applications Telecommunications PART Data Networking Systems Home Entertainment Centers SOHO TEMP RANGE PINPACKAGE MAX9491ETP -40°C to +85°C 20 TQFN-EP** MAX9491EUD* -40°C to +85°C 14 TSSOP PKG CODE T2055-5 U14-2 *Future product—contact factory for availability. **EP = Exposed pad. VDD I.C. VDD VDD GND TOP VIEW PD Pin Configurations 15 14 13 12 11 16 X2 17 X1 18 TOP VIEW GND X1 1 14 X2 9 I.C. I.C. 2 13 PD 8 I.C. I.C. 3 12 VDD 10 MAX9491 20 6 I.C. TUNE 5 1 2 3 4 5 CLK_OUT I.C. GND I.C. VDDA 7 AGND 19 TUNE I.C. VDD 4 MAX9491 11 GND 10 I.C. GND 6 9 GND CLK_OUT 7 8 I.C. TSSOP TQFN (5mm x 5mm) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9491 General Description MAX9491 Factory Programmable Single PLL Clock Generator ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +4.0V VDDA to AGND ......................................................-0.3V to +4.0V All Other Pins to GND ..................................-0.3V to VDD + 0.3V Short-Circuit Duration (all LVCMOS outputs)..............................................Continuous ESD Protection (Human Body Model)..................................±2kV Continuous Power Dissipation (TA = +70°C) 20-Lead TQFN (derate 21.3mW/°C above +70°C) ....2758mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......796.8mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VDD = VDDA = +3.0V to +3.6V and TA = -40°C to +85°C. Typical values at VDD = VDDA = 3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS INPUTS (PD, X1 as a reference INPUT CLK) Input High Level VIH 2.0 VDD V Input Low Level VIL 0 0.8 V High-Level Input Current IIH VIN = VDD Low-Level Input Current IIL VIN = 0 20 µA -20 µA VDD 0.6 V CLOCK OUTPUT (CLK_OUT) Output High Level VOH IOH = -4mA Output Low Level VOL IOL = 4mA 0.4 V POWER SUPPLIES Digital Power-Supply Voltage VDD 3.0 3.6 V Analog Power-Supply Voltage VDDA 3.0 3.6 V Total Current for Digital and Analog Supplies IDC fOUT = 45MHz, no load fIN = 13MHz 10 mA Power-Down Current IDC2 PD = low 60 µA 2 _______________________________________________________________________________________ Factory Programmable Single PLL Clock Generator (VDD = VDDA = +3.0V to +3.6V, CL = 10pF and TA = -40°C to +85°C. Typical values are at VDD = VDDA = 3.3V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUT CLOCK (CLK_OUT) Minimum Frequency Range Maximum Frequency Range fOUT fIN = 5MHz to 50MHz CL < 5pF 4 133 MHz 200 Clock Rise Time tR 20% to 80% of VDD, fOUT = 80MHz, fIN = 13MHz 1.5 ns Clock Fall Time tF 80% to 20% of VDD, fOUT = 80MHz, fIN = 13MHz 1.3 ns Duty Cycle fOUT = 45MHz, fIN = 13MHz Output Period Jitter JP 44 50 fOUT = 45MHz, fIN = 13MHz 14 fOUT = 80MHz, fIN = 13MHz 22 fOUT = 197MHz, fIN = 13MHz 13 56 % ps RMS Soft Power-On Time tPO2 PD from low to high, fOUT = 45MHz, fIN = 13MHz, see Figure 2 1 ms Hard Power-On Time tPO1 See Figure 2 15 ms VCXO CLOCK Crystal Frequency fXTL 27 MHz ±30 ppm Crystal Accuracy Tuning Voltage Range VTUNE VCXO Tuning Range TUNE Input Impedance Output CLK Accuracy 0 VTUNE = 0 to 3V, C1 = C2 = 4pF ZTUNE VTUNE = 1.5V, C1 = C2 = 4pF ±150 3 ±200 V ppm 95 kΩ ±50 ppm Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design and characterization. Note 2: Guaranteed by design and characterization; limits are set at ±6 sigma. _______________________________________________________________________________________ 3 MAX9491 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VDD = VDDA = +3.3V, TA = +25°C, fIN = 13MHz clock, CL = 10pF, 27MHz, unless otherwise noted.) RISE TIME vs. TEMPERATURE 9 1.4 1.0 10 35 60 85 -15 TEMPERATURE (°C) 10 35 60 85 -40 MAX9491 toc04 JITTER (ps) 25 20 15 10 fIN = 13MHz fOUT = 80MHz 32 30 35 60 85 JITTER vs. TEMPERATURE 40 fIN = 27MHz fOUT = 197MHz 30 24 JITTER (ps) fIN = 13MHz fOUT = 45MHz 10 TEMPERATURE (°C) JITTER vs. TEMPERATURE 40 MAX9491 toc03 -15 TEMPERATURE (°C) JITTER vs. TEMPERATURE 35 1.0 0.2 -40 MAX9491 toc05 -15 1.4 0.6 0.2 -40 40 1.8 0.6 8 fIN = 13MHz fOUT = 45MHz MAX9491 toc06 10 FALL TIME vs. TEMPERATURE 2.2 FALL TIME (ns) 11 fIN = 13MHz fOUT = 45MHz 1.8 RISE TIME (ns) 12 SUPPLY CURRENT (mA) 2.2 MAX9491 toc01 fIN = 13MHz fOUT = 45MHz MAX9491 toc02 SUPPLY CURRENT vs. TEMPERATURE 13 JITTER (ps) 16 20 10 8 5 0 0 -40 -15 10 35 60 85 0 -40 -15 10 35 85 -40 -15 10 35 60 85 TYPICAL CLK_OUT WAVEFORM AT 45MHz TYPICAL CLK_OUT WAVEFORM AT 80MHz TYPICAL CLK_OUT WAVEFORM AT 197MHz VDD = VDDA = 3.0V CLK1 1V/div 4ns/div MAX9491 toc09 TEMPERATURE (°C) MAX9491 toc08 TEMPERATURE (°C) VDD = VDDA = 3.0V 4 60 TEMPERATURE (°C) MAX9491 toc07 MAX9491 Factory Programmable Single PLL Clock Generator VDD = VDDA = 3.0V CLK1 1V/div CLK1 1V/div 4ns/div 4ns/div _______________________________________________________________________________________ Factory Programmable Single PLL Clock Generator 6pF 100 4pF 0 5pF -100 fIN = 13MHz 80 DUTY CYCLE (%) 60 40 20 -200 -300 0 0.5 1.0 1.5 2.0 2.5 3.0 45 50 55 60 65 70 VCXO TUNING RANGE (V) FREQUENCY (MHz) 45MHz OUTPUT 80MHz OUTPUT 10dB/REF = 0dBm RBW = 3kHz VBW = 3kHz ATN = 20dB CENTER = 45MHz SPAN = 2MHz MAX9491 toc12 0 10dB/REF = 0dBm RBW = 3kHz VBW = 3kHz ATN = 20dB CENTER = 80MHz SPAN = 2MHz 75 80 MAX9491 toc13 VCXO ACCURACY (PP/M) 200 DUTY CYCLE vs. OUTPUT FREQUENCY 100 MAX9491 toc10 fIN = 27MHz fOUT = 45MHz MAX9491 toc11 VCXO ACCURACY vs. VCXO TUNING RANGE 300 _______________________________________________________________________________________ 5 MAX9491 Typical Operating Characteristics (continued) (VDD = VDDA = +3.3V, TA = +25°C, fIN = 13MHz clock, CL = 10pF, 27MHz, unless otherwise noted.) Factory Programmable Single PLL Clock Generator MAX9491 Typical Operating Circuit/Block Diagram +3.3V +3.3V 0.1µF 0.1µF x 3 VDD VDDA X1 OR REFERENCE INPUT VDD MAX9491 C1 VDD VCXO C2 X2 PLL CLK_OUT TUNE AGND OTP PD GND Pin Description PIN NAME FUNCTION TQFN TSSOP 1 5 2 3 4, 10, 11 6, 9, 11 GND 5 7 CLK_OUT 6–9, 14, 19, 20 2, 3, 8, 10 I.C. 12, 13, 16 4, 12 VDD Power Supply. Bypass to GND with a 0.1µF capacitor. TUNE VCXO Tune Voltage Input. If using a reference clock input or VCXO is not used, connect TUNE to VDD. — VDDA Analog Power Supply. Bypass to GND with a 0.1µF capacitor. — AGND Analog Ground Ground Output Clock. Internally pulled down. Internally Connected. Leave unconnected for normal operation. 15 13 PD Active-Low Power-Down Input. Pull high for normal operation. Drive PD low to place MAX9491 in power-down mode. Internally pulled down. 17 14 X2 Crystal Connection 2. Leave unconnected if using a reference clock. 18 1 X1 Crystal Connection 1 or Reference Clock Input EP — EP Exposed Paddle (TQFN Only). Connect EP to GND or leave unconnected. Detailed Description The MAX9491 features a programmable fractional-N PLL, so frequencies between 4MHz to 200MHz can be generated. The device provides a buffered PLL clock output. The crystal input frequency can be between 5MHz and 35MHz, and the clock input between 5MHz and 50MHz. The internal VCXO has a fine-tuning range of ±200ppm. Power-Down Driving PD low places the MAX9491 in power-down mode. PD then sets CLK_OUT to high impedance and 6 shuts down the PLL. CLK_OUT has an 80kΩ (typ) internal pulldown resistor. Voltage-Controlled Crystal Oscillator (VCXO) The MAX9491’s internal VCXO produces a reference clock for the PLL used to generate the CLK_OUT. The oscillator uses a crystal as the base frequency reference and has a voltage-controlled tuning input for micro adjustment in a ±200ppm range. The tuning voltage, VTUNE, can vary from 0 to 3V as shown in Figure 1. The crystal should be AT-cut and oscillate on its fundamental mode with ±30ppm. The crystal shunt capacitor _______________________________________________________________________________________ Factory Programmable Single PLL Clock Generator with an internal POR signal and can be disabled by PD. When VCXO is not used, connect TUNE to VDD. Applications Information Using an Input Clock as the Reference When an input clock is used as the reference, connect the input clock to X1, leave X2 unconnected, and connect TUNE to VDD. 27.0405 Crystal Selection VCXO OUTPUT FREQUENCY (MHz) +150ppm 27.00 -150ppm 26.99595 3V 0 VTUNE When using a crystal with the MAX9491’s internal oscillator, connect the crystal to X1 and X2. Choose an ATcut crystal that oscillates on its fundamental mode with ±30ppm and loading capacitance less than 14pF. To achieve a wide VCXO tuning range, select a crystal with motional capacitance greater than 7fF and connect 6pF or less shunt capacitors at both X1 and X2 to ground. When the VCXO is used as an oscillator, select both shunt capacitors to approximately 13pF. The optimal shunt capacitors for achieving minimum frequency offset can be determined experimentally. Figure 1. VCXO Tuning Range for a 27MHz Crystal VDD 2.2V t CLK_IN PD CLK_OUT tPO1 tPO2 Figure 2. PLL Settling Time _______________________________________________________________________________________ 7 MAX9491 should be less than 10pF, including board parasitic capacitance. To achieve up to ±200ppm pullability, make sure the crystal-loading capacitance is less than 14pF. The VCXO is a free-running oscillator. It starts oscillating MAX9491 Factory Programmable Single PLL Clock Generator Board Layout Considerations and Bypassing The MAX9491’s high-frequency oscillator requires proper layout to ensure stability. For best performance, place components as close as possible to the device. Digital or AC transient signals on GND can create noise at the clock output. Return GND to the highest quality ground available. Bypass each VDD and VDDA with a 0.1µF capacitor, placed as close as possible to the device. Careful PC board ground layout minimizes crosstalk between the output and digital inputs. 8 Chip Information PROCESS: CMOS _______________________________________________________________________________________ Factory Programmable Single PLL Clock Generator TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 G 1 1 _______________________________________________________________________________________ 9 MAX9491 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX9491 Factory Programmable Single PLL Clock Generator D2 D MARKING b CL 0.10 M C A B D2/2 D/2 k L AAAAA E/2 E2/2 CL (NE-1) X e E DETAIL A PIN # 1 I.D. e/2 E2 PIN # 1 I.D. 0.35x45° e (ND-1) X e DETAIL B e L1 L CL CL L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 10 21-0140 ______________________________________________________________________________________ I 1 2 Factory Programmable Single PLL Clock Generator COMMON DIMENSIONS EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e PKG. CODES 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 T1655-2 T1655-3 T1655N-1 T2055-3 D2 3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.80 BSC. 0.50 BSC. - 0.25 - 0.25 - 0.25 0.35 0.45 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 40 16 N 20 28 32 ND 10 4 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC k L NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. L E2 exceptions MIN. NOM. MAX. MIN. NOM. MAX. ±0.15 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 33.00 33.00 3.00 3.00 3.20 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 ** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** ** DOWN BONDS ALLOWED YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES ** SEE COMMON DIMENSIONS TABLE 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05. PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- I 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2006 Maxim Integrated Products Springer Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX9491 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)