19-3345; Rev 0; 8/04 KIT ATION EVALU E L B AVAILA 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz The MAX9486 low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six buffered LVTTL clock outputs at 35.328MHz. The clock synthesizer can be used to generate the clocks for T1, E1, T3, E3, and xDSL. The MAX9486 has two phase-lock loops (PLLs). The first PLL uses a voltage-controlled crystal oscillator (VCXO). The second PLL is a frequency multiplier. With the two PLLs, the MAX9486 generates the output frequency at 35.328MHz. In addition, this device generates a jitter-suppressed 8kHz output that provides a better source for the reference clock relay. The MAX9486 is available in a 24-pin TSSOP package and operates over the extended operating temperature range of -40°C to +85°C and a single +3V to +3.6V power-supply range. Features ♦ 8kHz Input Reference CLK ♦ High-Jitter Rejection on the Reference CLK ♦ Synthesizer Locks to the 8kHz Reference with a ±200ppm Range ♦ Output Frequency: 35.328MHz ♦ Six Buffered LVTTL Low-Jitter Outputs ♦ One 8kHz Reference CLK Relay Output ♦ +3.3V Supply Operation ♦ 24-Pin TSSOP Package Ordering Information Applications Telecom Equipment Using T1, E1, T3, E3, and ISDN Protocols PART MAX9486EUG TEMP RANGE PIN-PACKAGE -40°C to +85°C 24 TSSOP xDSL Equipment in CO with Interface to the Telecom Protocols Pin Configuration Typical Application Circuit C1 R1 TOP VIEW SHDN 1 24 CLK1 REO 2 23 GND REIN 3 22 CLK2 VDDP 4 21 VDD GNDP 5 MAX9486 C2 LP1 20 CLK3 X1 6 19 VDD VDD 7 18 GND X2 8 17 CLK4 X1 X2 VDDP VDD SETI CLK1 CLK2 RSET MAX9486 GNDP GND 9 16 VDD LP2 10 15 CLK5 LP1 11 14 GND SHDN 13 CLK6 REIN SETI 12 LP2 CLK3 CLK4 CLK5 VDD CLK6 GND REO TSSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9486 General Description MAX9486 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +4.0V VDDP to GNDP.......................................................-0.3V to +4.0V SHDN, REO, REIN, X1, X2, CLK_ to GND ...-0.3V to (VDD + 0.3V) LP1, SETI to GNDP.....................................-0.3V to (VDD + 0.3V) LP2 Internally Connected to GNDP Short-Circuit Duration of Outputs ...............................Continuous Continuous Power Dissipation (TA = +70°C) 24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......976mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C ESD Rating (Human Body Model) .......................................±2kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VDD = VDDP = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDP = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.8 V DIGITAL INPUTS (REIN, SHDN) Input High Logic Level VIH Input Low Logic Level VIL 2.0 Input-Current High Level IIH VIN = VDD Input-Current Low Level IIL VIN = 0 V 20 µA -20 µA VDD 0.6V V DIGITAL OUTPUT CLOCKS (CLK1–CLK6, REO) Output High Logic Level VOH IOH = -4mA Output Low Logic Level VOL IOL = 4mA 0.4 V 3.6 V POWER SUPPLY (V DD, V DDP) Power-Supply Range PLL Power-Supply Range Power-Supply Current Shutdown Supply Current 2 VDD 3.0 VDDP IDD + IDDP ISHDN 3.0 (Note 2) 3.6 V 13 25 mA 8 30 µA _______________________________________________________________________________________ 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz (VDD = VDDP = +3.0V to +3.6V, CL = 20pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = VDDP = +3.3V, TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT CLOCKS (CLK1–CLK6) Frequency Range fOUT 35.328 MHz Clock Rise Time TR1 20% to 80% VDD 1.8 ns Clock Fall Time TF1 80% to 20% VDD 1.8 ns Period Jitter JPP1 Peak-to-peak 120 ps Output Skew tS Peak-to-peak 185 ps Duty Cycle 40 50 60 % REFERENCE CLOCK OUTPUT (REO) Frequency fREF 8 kHz Clock Rise Time TR2 1.8 ns Clock Fall Time TF2 1.8 Duty Cycle 40 50 ns 60 % VCXO Crystal Frequency fXTL Including frequency accuracy and temperature range Crystal Accuracy VCXO Pulling Range Input Reference CLK Pulse Width Note 1: Note 2: Note 3: Note 4: (Note 4) tW Measured at high or low states -200 10 17.664 MHz ±25 ppm +200 ppm ns Specifications are 100% tested at TA = +25°C. Specifications over temperature are guaranteed by design and characterization. No load on clock outputs. Guaranteed by design. Crystal loading capacitance is 14pF. _______________________________________________________________________________________ 3 MAX9486 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VDD = VDDP = +3.3V, TA = +25°C, unless otherwise noted.) OUTPUT CLOCK JITTER (P-P) vs. TEMPERATURE OUTPUT CLOCK JITTER (ps) 130 120 110 100 140 135 90 50 0 -50 -100 120 115 110 60 85 3.0 3.1 3.2 3.3 3.4 3.5 TEMPERATURE (°C) SUPPLY VOLTAGE (V) SUPPLY CURRENT (IDD + IDDP) vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 12 MAX9486 toc05 14 12 TA = -40°C TA = +25°C 3.6 11 TA = +85°C 10 TA = +25°C 9 TA = -40°C 8 10 -150 7 -200 -250 7.998 4 CENTERED AT 35.328MHz 35 SUPPLY CURRENT (µA) 100 10 TA = +85°C SUPPLY CURRENT (mA) 150 -15 16 MAX9486 toc04 200 125 100 -40 OUTPUT FREQUENCY VARIATION vs. INPUT REFERENCE FREQUENCY 250 130 105 80 10ns/div MAX9486 toc03 MAX9486 toc02 140 MAX9486 toc06 MAX9486 toc01 OUTPUT CLOCK JITTER (P-P) vs. SUPPLY VOLTAGE OUTPUT CLOCK JITTER (ps) OUTPUT WAVEFORM OUTPUT FREQUENCY VARIATION (ppm) MAX9486 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz 6 8 7.999 8.000 8.001 INPUT REFERENCE FREQUENCY (kHz) 8.002 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.5 3.6 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz PIN NAME FUNCTION 1 SHDN 2 REO Reference Clock Output. REO is an 8kHz reference clock output with jitter suppression. 3 REIN Reference Input 4 VDDP Phase-Lock Loop (PLL) Power Supply. Bypass VDDP with 0.1µF and 0.001µF capacitors to GNDP. 5 GNDP 6 X1 7, 16, 19, 21 VDD 8 X2 9, 14, 18, 23 GND Ground 10 LP2 External Filter 2. Connect the loop filter capacitors and a resistor between LP1 and LP2 (see the Typical Application Circuit). LP2 is internally connected to GNDP. 11 LP1 External Filter 1. Connect the loop filter capacitors and a resistor between LP1 and LP2 (see the Typical Application Circuit). 12 SETI Charge-Pump Current-Setting Input. Connect a resistor from SETI to GNDP to set PLL charge-pump current (see the Detailed Description section). 13 CLK6 Clock Output 6 at 35.328MHz 15 CLK5 Clock Output 5 at 35.328MHz 17 CLK4 Clock Output 4 at 35.328MHz 20 CLK3 Clock Output 3 at 35.328MHz 22 CLK2 Clock Output 2 at 35.328MHz 24 CLK1 Clock Output 1 at 35.328MHz Active-Low Shutdown Input PLL Ground Crystal Input 1. Connect X1 to a fundamental mode crystal for the VCXO. Digital Power Supply. Bypass VDD with 0.1µF and 0.001µF capacitors to GND. Crystal Input 2. Connect X2 to a fundamental mode crystal for the VCXO. _______________________________________________________________________________________ 5 MAX9486 Pin Description MAX9486 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz Functional Diagram LP1 LP2 X1 VDDP X2 GNDP CLK1 SETI REIN PHASE DETECTOR AND CHARGE PUMP CLK2 PHASE DETECTOR, CHARGE PUMP, AND LOOP FILTER VCXO VCO CLK3 PLL2 PLL1 CLK4 /2 /2208 CLK5 CLK6 SHDN REFERENCE CLK MONITOR REO MAX9486 VDD Detailed Description The MAX9486 is a high-performance clock synthesizer with an 8kHz input reference clock. This device generates six identical buffered LVTTL clock outputs at 35.328MHz. The MAX9486 features two PLLs. The first PLL (PLL1) uses an internal VCXO, locked to the 8kHz reference CLK, to generate a 17.664MHz CLK output for the second PLL (PLL2). PLL2 multiplies the VCXO frequency by a factor of 2 to produce the 35.328MHz outputs. In addition, this device features a low-jitter 8kHz output that provides a better source for the reference clock relay (see the Functional Diagram). Power-Up At power-up, all the outputs are disabled and pulled low (to GND) for at least 256ms. After 256ms, the crystal oscillator starts oscillation. The input reference clock for PLL1 is 8kHz and its output frequency, 17.664MHz, is also the reference clock for PLL2. If the 8kHz reference clock is not present at power-up, the output frequency of PLL1 is locked to the center frequency of the crystal oscillator. 8kHz Reference CLK Monitor The MAX9486 features an internal clock (CLK) monitor circuitry to detect the presence of the external 8kHz reference clock. The internal CLK monitor continuously monitors the number of low-to-high transitions within a 6 GND three-cycle (at 8kHz) time window. If the transition number is less than two, the internal CLK monitor states loss of the reference CLK. However, if in a three-cycle time window the monitor counts two or three transitions, it considers the input reference clock as present. When the monitor detects the absence of the 8kHz reference clock, PLL2 is forced to lock to the crystal oscillator frequency. However, when the monitor detects the return of the reference clock, PLL1 locks to the reference clock again. Clock Outputs (CLK1 to CLK6) and REO The MAX9486 uses a 17.664MHz crystal and a reference clock (REIN) to generate six identical outputs, CLK1 to CLK6, at 35.328MHz. All CLK_ outputs are LVTTL with a skew of 185ps. The MAX9486 also regenerates the 8kHz reference CLK at REO output. Voltage-Controlled Crystal Oscillator (VCXO) The MAX9486’s internal VCXO takes an external 17.664MHz crystal as the base frequency and has a pulling range of approximately ±200ppm. This configuration also makes the VCXO PLL become a narrowband filter to reject high-frequency jitter on the input reference and eliminate it from the REO and CLK_ outputs. _______________________________________________________________________________________ 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz Setting section, and N is the crystal PLL frequency divider equal to 2208. The loop-damping factor is calculated by: 5900 × ISETI × C1 N R DampingFactor = 1 × 2 Crystal Selection where C1 (F) and R1 (Ω) are the values of the capacitor and the resistor in the PLL1 loop filter shown in Figure 1; ISETI is calculated as shown in the ChargePump Current Setting section and N = 2208. The MAX9486 uses a 17.664MHz crystal as the base frequency for the VCXO. It is important to use a correct type of quartz crystal to avoid reducing frequency pulling range, or excessive output phase jitter. The following equation shows the relationship between components C1 and C2 in the loop filter: C2 ≤ C1/20 Applications Information Choose an AT-cut crystal that oscillates at 17.664MHz on its fundamental mode with a variation of ±25ppm including frequency accuracy and operating temperature range. The crystal’s load capacitance should be 14pF. Pulling range may vary depending on the crystal used. Refer to the MAX9486 evaluation kit for details. PLL1 Loop Filter The MAX9486 features two PLLs: PLL1 and PLL2. The first phased-lock loop, PLL1, contains an integrated VCXO that uses an external crystal to track the input reference signal and attenuate input jitter. Figure 1 shows the external loop filter of the PLL containing resistor R1 and two capacitors, C1 and C2. This loop filter is connected between LP1 and LP2 as shown in the Typical Operating Circuit. The loop-filter bandwidth is determined by C1, C2, R1, and RSET where RSET is used to set the value of the charge-pump current. The typical values of C1, C2, R1, and R SET are 22nF, 560pF, 1000kΩ, and 13kΩ, respectively. Use the following equation to calculate a PLL loop bandwidth in Hz: BW = (R1 x ISETI x 940) / N where R1 (Ω) is the resistor in the PLL1 loop filter (Figure 1), ISETI (A) is the charge-pump current calculated from the equation in the Charge-Pump Current Charge-Pump Current Setting The MAX9486 also allows external setting of the chargepump current in PLL1. Connect a resistor from SETI to GNDP to set the PLL1 charge-pump current: Charge-Pump Current = 2.4 x 1000 / (RSET(kΩ) + 1) where RSET is in kΩ and the value of the charge-pump current is in µA. The loop response can be adjusted to meet individual application requirements since the charge-pump current and all the filter components for the VCXO loop can be set externally. Board Layout and Bypassing The MAX9486’s high-oscillator frequency makes proper layout important to ensure stability. For best performance, place components as close as possible to the device. Digital or AC transient signals on GND can create noise at the clock outputs. Return GND to the highest quality ground available. Bypass V DD and VDDP with 0.1µF and 0.001µF capacitors, placed as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the outputs and digital inputs. Traces must be as short as possible on LP1 and LP2 and connect the capacitors and the resistor as close as possible to the device. Chip Information LP1 R1 C2 TRANSISTOR COUNT: 7512 PROCESS: CMOS C1 LP2 Figure 1. Typical Loop Filter _______________________________________________________________________________________ 7 MAX9486 SHDN Mode The MAX9486 features a shutdown mode with a supply current less than 8µA (typ). Drive SHDN low to get the device into shutdown mode. In this mode, all the outputs go low and both PLLs are powered down. After SHDN goes high, the outputs still stay low for an additional 256ms to allow both PLLs to be stabilized before the outputs are enabled again. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) TSSOP4.40mm.EPS MAX9486 8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.