FUJITSU MB91F345BPFT-GE1

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16704-1E
32-bit Microcontroller
CMOS
FR60 Lite MB91345 Series
MB91F345B/F346B
■ DESCRIPTION
The MB91345 series is the microcontrollers based on 32-bit high-perform RISC-CPU while integrating a variety
of I/O resources for embedded control applications which require high-performance, high-speed CPU processing.
It is suitable for the embedded control in digital home appliances or audio visual equipment, requiring highperformance CPU processing power.
This product compactly integrates a variety of peripheral functions for single chip and is FR60 applicable to fasterspeed application.
Note : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURE
• FR CPU
• 32-bit RISC, load/store architecture, with a five-stage pipeline
• Maximum operating frequency : 50 MHz [PLL used : original oscillation 12.5 MHz]
• 16-bit fixed length instruction (basic instructions) ; 1 instruction per cycle
• Instruction set optimized for embedded applications : Memory-to-Memory transfer, bit manipulation, barrel shift
instructions
• Instructions adapted for high-level programming languages : Function entry/exit instructions, multiple-register
load/store instructions
• Register interlock function : Facilitating coding in assembles
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB91345 Series
• On-chip multiplier supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction set compatible with FR family
• External bus interface
• Operating frequency : Max 25 MHz
• 24-bit address full output (16 Mbytes area)
• 8/16-bit data output
• Capable of chip-select signal output for completely independent four areas settable in 64 Kbytes minimum
• Support for various memory interfaces : SRAM and ROM/Flash
• Basic bus cycle : 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
• External wait cycles generated by RDY input
• Unused data/address pins can serve for general-purpose I/O
• Internal memory
Flash
D-bus RAM
F-bus RAM
MB91F345B
512 Kbytes
24 Kbytes
8 Kbytes
MB91F346B
1 Mbyte
24 Kbytes
8 Kbytes
• DMAC (DMA Controller)
• 5 channels
• Two transfer factors (internal peripheral / software)
• Addressing mode : 20/24-bit full-address selection (increment/decrement/fixed)
• Transfer modes (burst transfer/step transfer/and block transfer)
• Selectable transfer data sizes : 8, 16, or 32 bits
• Bit search module (for REALOS)
Search for the position of the bit I/O-changed first in one word from the MSB
• Reload timer : 3 channels (including 1channel for REALOS)
• 16-bit timer
• The internal clock is optional from 2/8/32 division
• Multi function serial interface
• 11 channels
• Full duplex double buffer
• 2 channels out of 11 channels with 16-byte FIFO
• Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication, clock
synchronous communication (Max 8.25 Mbps) , I2C* standard mode (Max 100 kbps) , high-speed mode (Max
400 kbps)
• Parity on/off selectable
• Baud rate generator per channel
• Abundant error detection functions are provided (Parity, frame, and overrun)
• External clock can be used as transfer clock
• ch.0, ch.1, ch.2, and ch.10 is tolerant of 5 V
(Continued)
2
MB91345 Series
(Continued)
• Interrupt controller
• A total of 24 external interrupt lines (external interrupt pins INT23 to INT0)
• Interrupt from internal peripheral
• Programmable 16 priority levels
• Available for wakeup from STOP mode
• A/D converter :
• 10-bit resolution, 8 channels + 8 channels 2unit
• Successive approximation type : Conversion time : min. 1.2 µs (at 16 MHz)
• Conversion mode (Shingle-shot conversion mode, scan conversion mode)
• Startup source (software/external trigger)
• PPG timer : up to 16 channels (at 8 bits)
• 8/16-bit PPG timer : 8 bits × 16 channels or 16 bits × 8 channels
• The internal clock is optional from 1/4/16/64 division
• PWC timer : 1 channel
16-bit up counter 1 channel (1 input)
• Input capture and output compare : up to 8 channels (ch.0 to ch.3; 16-bit ICU, OCU, ch.4 to ch.7; 32-bit ICU,
OCU)
• 16-bit free-run counter × 1 channel + 16-bit input capture × 4 channels + 16-bit output compare × 4 channels
• 32-bit free-run counter × 1 channel + 32-bit input capture × 4 channels + 32-bit output compare × 4 channels
• MIN/MAX/ABS
• MIN/MAX/ABS is performed and the result is accumulated and added.
• Other interval timer and counter
• 8/16-bit up down counter :
8-bit × 4 channels or 16-bit × 2 channels
• 16-bit timebase timer/watchdog timer
• I/O port
• Max 71 ports
• Other features
• Internal oscillation circuit as a clock source and PLL multiplier
• INIT is prepared as a reset terminal
• Watchdog timer reset and software reset are also available
• Stop and sleep mode supported as low-power-consumption modes
• Gear function
• Built-in time base timer
• Memory patch function
• Package : TQFP-100
• CMOS technology (0.18 µm)
• Power supply voltage : 3.3 V ± 0.3 V (single power supply)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
3
MB91345 Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VCC
P23/A03/SIN1
P22/A02/SCK0
P21/A01/SOT0
P20/A00/SIN0
P17/D15/ADTRG0
P16/D14/SCK7/ADTRG1
P15/D13/SOT7/TOT2
P14/D12/SIN7/TIN2
P13/D11/SCK6/TOT1
P12/D10/SOT6/TIN1
P11/D09/SIN6/TOT0
P10/D08/SCK5/TIN0
P07/D07/SOT5/INT15
P06/D06/SIN5/INT14
P05/D05/SCK4/INT13
P04/D04/SOT4/INT12
P03/D03/SIN4/INT11
P02/D02/SCK3/INT10
P01/D01/SOT3/INT9
P00/D00/SIN3/INT8
P63/SYSCLK/RT3
P62/RDY/RT2/ADTRG1-2
P61/RT1/PWC0/ADTRG0-2
VCC
(TOP VIEW)
VSS
C
P24/A04/SOT1
P25/A05/SCK1
P26/A06/SIN2
P27/A07/SOT2
P30/A08/SCK2
P31/A09/AIN0/TOT0-2
P32/A10/BIN0/TOT1-2
P33/A11/ZIN0/TOT2-2
P34/A12/AIN2
P35/A13/BIN2/IC4
P36/A14/ZIN2/IC5
P37/A15/FRCK1
P40/A16/PPG9/INT16
P41/A17/PPGB/INT17
P42/A18/PPGD/INT18
P43/A19/PPGF/INT19
P44/A20/IC0/INT20
P45/A21/IC1/INT21/SIN10
P46/A22/IC2/INT22/SOT10
P47/A23/IC3/INT23/SCK10
VSS
X1
X0
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
PC2/IC7/SCK9
PC1/IC6/SOT9
PC0/FRCK0/SIN9
PE7/AN15/INT7/SCK8
PE6/AN14/INT6/SOT8
PE5/AN13/INT5/SIN8
PE4/AN12/INT4/PPGE
PE3/AN11/INT3/PPGC
PE2/AN10/INT2/PPGA
PE1/AN9/INT1/PPG8
PE0/AN8/INT0/PPG6
AVSS
AVRL
AVRH
AVCC
PD7/AN7/PPG4
PD6/AN6/PPG2
PD5/AN5/ZIN3/PPG0
PD4/AN4/BIN3
PD3/AN3/AIN3
PD2/AN2/ZIN1
PD1/AN1/BIN1
PD0/AN0/AIN1
VCC
(FPT-100P-M18)
Note : TOTx and TOTx-2 have same function. Also ADTRGx and ADTRGx-2 have
same function. Use either of the two depending on the combined resource.
4
VSS
P60/RT0
P57/WR1/RT7
P56/WR0/RT6
P55/RD/RT5
P54/AS/RT4
P53/CS3/PPG7
P52/CS2/PPG5
P51/CS1/PPG3
P50/CS0/PPG1
MD2
MD1
MD0
INIT
TRST
IBREAK
ICS2
ICS1
ICS0
ICD3
ICD2
ICD1
ICD0
ICLK
VCC
MB91345 Series
■ PIN DESCRIPTION
Pin No.
Pin name
I/O Circuit
type*
1
VSS
⎯
GND pin
2
C
⎯
Power stabilization capacitance pin
P24
3
A04
General-purpose I/O port
B
SOT1
A05
General-purpose I/O port. Enabled in single-chip mode.
B
SCK1
6
A06
General-purpose I/O port. Enabled in single-chip mode.
B
Multi function serial 2 serial data input pin
P27
General-purpose I/O port. Enabled in single-chip mode.
A07
B
A08
General-purpose I/O port. Enabled in single-chip mode.
B
SCK2
Bit 8 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 2 clock I/O pin
P31
General-purpose I/O port. Enabled in single-chip mode.
A09
Bit 9 of external address bus output pin.
Enabled when external bus is effective.
B
AIN0
Up down counter input pin
TOT0-2
9
Bit 7 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 2 serial data output pin
P30
8
Bit 6 of external address bus output pin.
Enabled when external bus is effective.
SIN2
SOT2
7
Bit 5 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 1 clock I/O pin
P26
5
Bit 4 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 1 serial data output pin
P25
4
Function
Reload timer output pin
P32
General-purpose I/O port. Enabled in single-chip mode.
A10
Bit 10 of external address bus output pin.
Enabled when external bus is effective.
BIN0
TOT1-2
B
Up down counter input pin
Reload timer output pin
(Continued)
5
MB91345 Series
Pin No.
10
Pin name
I/O Circuit
type*
P33
General-purpose I/O port. Enabled in single-chip mode.
A11
Bit 11 of external address bus output pin.
Enabled when external bus is effective.
B
ZIN0
Up down counter input pin
TOT2-2
Reload timer output pin
P34
11
12
A12
General-purpose I/O port. Enabled in single-chip mode.
B
Up down counter input pin
P35
General-purpose I/O port. Enabled in single-chip mode.
A13
Bit 13 of external address bus output pin.
Enabled when external bus is effective.
B
Up down counter input pin
IC4
Input capture ICU 4 data sample input pin
P36
General-purpose I/O port. Enabled in single-chip mode.
A14
Bit 14 of external address bus output pin.
Enabled when external bus is effective.
B
ZIN2
14
Up down counter input pin
IC5
Input capture ICU 5 data sample input pin
P37
General-purpose I/O port. Enabled in single-chip mode.
A15
B
FRCK1
A16
General-purpose I/O port
B
Bit 16 of external address bus output pin.
Enabled when external bus is effective.
PPG9
PPG output pin
INT16
External interrupt request 16 input pin
P41
16
Bit 15 of external address bus output pin.
Enabled when external bus is effective.
16-bit free-run timer input pin
P40
15
Bit 12 of external address bus output pin.
Enabled when external bus is effective.
AIN2
BIN2
13
Function
A17
General-purpose I/O port
B
Bit 17 of external address bus output pin.
Enabled when external bus is effective.
PPGB
PPG output pin
INT17
External interrupt request 17 input pin
(Continued)
6
MB91345 Series
Pin No.
17
18
19
Pin name
I/O Circuit
type*
P42
General-purpose I/O port
A18
Bit 18 of external address bus output pin.
Enabled when external bus is effective.
B
PPGD
PPG output pin
INT18
External interrupt request 18 input pin
P43
General-purpose I/O port
A19
Bit 19 of external address bus output pin.
Enabled when external bus is effective.
B
PPGF
PPG output pin
INT19
External interrupt request 19 input pin
P44
General-purpose I/O port
A20
Bit 20 of external address bus output pin.
Enabled when external bus is effective.
B
IC0
Input capture ICU0 data sample input pin
INT20
20
21
22
Function
External interrupt request 20 input pin
P45
General-purpose I/O port
A21
Bit 21 of external address bus output pin.
Enabled when external bus is effective.
IC1
B
Input capture ICU1 data sample input pin
INT21
External interrupt request 21 input pin
SIN10
Multi function serial 10 serial data input pin
P46
General-purpose I/O port
A22
Bit 22 of external address bus output pin.
Enabled when external bus is effective.
IC2
B
Input capture ICU2 data sample input pin
INT22
External interrupt request 22 input pin
SOT10
Multi function serial 10 serial data output pin
P47
General-purpose I/O port
A23
Bit 23 of external address bus output pin.
Enabled when external bus is effective.
IC3
B
Input capture ICU3 data sample input pin
INT23
External interrupt request 10 input pin
SCK10
Multi function serial 10 clock I/O pin
(Continued)
7
MB91345 Series
Pin No.
Pin name
I/O Circuit
type*
23
VSS
⎯
GND pin
24
X1
A
Main clock I/O pin
25
X0
A
Main clock input pin
26
VCC
⎯
Power supply input pin (3.3 V)
PD0
27
28
29
30
31
32
AN0
General-purpose I/O port
E
Up down counter input pin
PD1
General-purpose I/O port
AN1
E
A/D converter analog input pin
BIN1
Up down counter input pin
PD2
General-purpose I/O port
AN2
E
A/D converter analog input pin
ZIN1
Up down counter input pin
PD3
General-purpose I/O port
AN3
E
A/D converter analog input pin
AIN3
Up down counter input pin
PD4
General-purpose I/O port
AN4
E
A/D converter analog input pin
BIN3
Up down counter input pin
PD5
General-purpose I/O port
AN5
ZIN3
E
AN6
E
A/D converter analog input pin
PPG output pin
PD7
PPG4
Up down counter input pin
General-purpose I/O port
PPG2
AN7
A/D converter analog input pin
PPG output pin
PD6
34
A/D converter analog input pin
AIN1
PPG0
33
Function
General-purpose I/O port
E
A/D converter analog input pin
PPG output pin
(Continued)
8
MB91345 Series
Pin No.
Pin name
I/O Circuit
type*
35
AVCC
⎯
A/D converter analog power supply input pin
36
AVRH
⎯
A/D converter standard voltage input pin
Be sure to turn on/off this power supply when potential of AVRH or
more is applied to AVCC.
37
AVRL
⎯
A/D converter standard low voltage input pin
38
AVSS
⎯
A/D converter analog GND pin
PE0
39
AN8
INT0
General-purpose I/O port
E
PPG6
AN9
INT1
E
INT2
E
INT3
E
INT4
E
INT5
SIN8
A/D converter analog input pin
External interrupt request 4 input pin
PPG output pin
PE5
AN13
External interrupt request 3 input pin
General-purpose I/O port
PPGE
44
A/D converter analog input pin
PPG output pin
PE4
AN12
External interrupt request 2 input pin
General-purpose I/O port
PPGC
43
A/D converter analog input pin
PPG output pin
PE3
AN11
External interrupt request 1 input pin
General-purpose I/O port
PPGA
42
A/D converter analog input pin
PPG output pin
PE2
AN10
External interrupt request 0 input pin
General-purpose I/O port
PPG8
41
A/D converter analog input pin
PPG output pin
PE1
40
Function
General-purpose I/O port
E
A/D converter analog input pin
External interrupt request 5 input pin
Multi function serial 8 serial data input pin
(Continued)
9
MB91345 Series
Pin No.
Pin name
I/O Circuit
type*
PE6
45
AN14
INT6
General-purpose I/O port
E
SOT8
AN15
INT7
E
48
External interrupt request 7 input pin
General-purpose I/O port
C
16-bit free-run timer input pin
SIN9
Multi function serial 9 serial data input pin
PC1
General-purpose I/O port
IC6
C
SOT9
IC7
Input capture ICU6 data sample input pin
Multi function serial 9 serial data output pin
PC2
49
A/D converter analog input pin
Multi function serial 8 clock I/O pin
PC0
FRCK0
External interrupt request 6 input pin
General-purpose I/O port
SCK8
47
A/D converter analog input pin
Multi function serial 8 serial data output pin
PE7
46
Function
General-purpose I/O port
C
SCK9
Input capture ICU7 data sample input pin
Multi function serial 9 clock I/O pin
50
VSS
⎯
GND pin
51
VCC
⎯
Power supply input pin (3.3 V)
52
ICLK
H
Development tool clock pin
53
ICD0
K
Development tool data pin
54
ICD1
K
Development tool data pin
55
ICD2
K
Development tool data pin
56
ICD3
K
Development tool data pin
57
ICS0
J
Development tool status pin
58
ICS1
J
Development tool status pin
59
ICS2
J
Development tool status pin
60
IBREAK
I
Development tool break pin
61
TRST
G
Development tool reset pin
62
INIT
G
Initial reset pin
(Continued)
10
MB91345 Series
Pin No.
Pin name
I/O Circuit
type*
63
MD0
F
Mode input pin
64
MD1
F
Mode input pin
65
MD2
F
Mode input pin
P50
66
CS0
General-purpose I/O port
C
PPG1
CS1
General-purpose I/O port
C
PPG3
CS2
General-purpose I/O port
C
PPG5
CS3
General-purpose I/O port
C
PPG7
71
72
AS
External chip select pin. Enabled when external bus is effective.
PPG output pin
P54
70
External chip select pin. Enabled when external bus is effective.
PPG output pin
P53
69
External chip select pin. Enabled when external bus is effective.
PPG output pin
P52
68
External chip select 0. Enabled when external bus is effective.
PPG output pin
P51
67
Function
General-purpose I/O port
C
External address strobe output pin. Enabled when external bus is
effective.
RT4
Output compare OCU4 waveform output pin
P55
General-purpose I/O port
RD
C
External read strobe output pin. Enabled when external bus is
effective.
RT5
Output compare OCU5 waveform output pin
P56
General-purpose I/O port
WR0
RT6
D
External data bus upper 8-bit write strobe output pin.
When external bus is effective, high 8 bits of data during 16-bit
access or 8 bits of data during 8-bit access is used as write strobe.
Output compare OCU6 waveform output pin
(Continued)
11
MB91345 Series
Pin No.
Pin name
I/O Circuit
type*
P57
73
WR1
General-purpose I/O port
D
RT7
74
P60
RT0
Function
External data bus lower 8-bit write strobe output pin.
Enabled when external bus is effective and external bus 16-bit mode
is selected.
Output compare OCU7 waveform output pin
C
General-purpose I/O port
Output compare OCU0 waveform output pin
75
VSS
⎯
GND pin
76
VCC
⎯
Power supply input pin (3.3 V)
P61
77
RT1
PWC0
General-purpose I/O port
C
ADTRG0-2
78
P62
General-purpose I/O port
RDY
External ready input pin.
Enabled when both external bus and bus request are effective.
C
Output compare OCU2 waveform output pin
ADTRG1-2
A/D converter trigger input pin
P63
80
81
PWC input pin
A/D converter trigger input pin
RT2
79
Output compare OCU1 waveform output pin
SYSCLK
General-purpose I/O port
C
External clock output pin.
Enabled when external bus is effective.
RT3
Output compare OCU3 waveform output pin
P00
General-purpose I/O port
D00
C
Bit 0 of external address/data bus I/O pin.
Enabled when external bus is effective.
SIN3
Multi function serial 3 serial data input pin
INT8
External interrupt request 8 input pin
P01
General-purpose I/O port
D01
C
Bit 1 of external address/data bus I/O pin.
Enabled when external bus is effective.
SOT3
Multi function serial 3 serial data output pin
INT9
External interrupt request 9 input pin
(Continued)
12
MB91345 Series
Pin No.
82
83
84
85
86
87
88
Pin name
I/O Circuit
type*
Function
P02
General-purpose I/O port
D02
Bit 2 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SCK3
Multi function serial 3 clock I/O pin
INT10
External interrupt request 10 input pin
P03
General-purpose I/O port
D03
Bit 3 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SIN4
Multi function serial 4 serial data input pin
INT11
External interrupt request 11 input pin
P04
General-purpose I/O port
D04
Bit 4 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SOT4
Multi function serial 4 serial data output pin
INT12
External interrupt request 12 input pin
P05
General-purpose I/O port
D05
Bit 5 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SCK4
Multi function serial 4 clock I/O pin
INT13
External interrupt request 13 input pin
P06
General-purpose I/O port
D06
Bit 6 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SIN5
Multi function serial 5 serial data input pin
INT14
External interrupt request 14 input pin
P07
General-purpose I/O port
D07
Bit 7 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SOT5
Multi function serial 5 serial data output pin
INT15
External interrupt request 12 input pin
P10
General-purpose I/O port
D08
Bit 8 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SCK5
Multi function serial 5 clock I/O pin
TIN0
Reload timer event input pin
(Continued)
13
MB91345 Series
Pin No.
89
90
91
92
93
94
Pin name
I/O Circuit
type*
P11
General-purpose I/O port
D09
Bit 9 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SIN6
Multi function serial 6 serial data input pin
TOT0
Reload timer output pin
P12
General-purpose I/O port
D10
Bit 10 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SOT6
Multi function serial 6 serial data output pin
TIN1
Reload timer event input pin
P13
General-purpose I/O port
D11
Bit 11 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SCK6
Multi function serial 6 clock I/O pin
TOT1
Reload timer output pin
P14
General-purpose I/O port
D12
Bit 12 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SIN7
Multi function serial 7 serial data input pin
TIN2
Reload timer event input pin
P15
General-purpose I/O port
D13
Bit 13 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SOT7
Multi function serial 7 serial data output pin
TOT2
Reload timer output pin
P16
General-purpose I/O port
D14
Bit 14 of external address/data bus I/O pin.
Enabled when external bus is effective.
C
SCK7
Multi function serial 7 clock I/O pin
ADTRG1
A/D converter trigger input pin
P17
95
Function
D15
ADTRG0
General-purpose I/O port
C
Bit 15 of external address/data bus I/O pin.
Enabled when external bus is effective.
A/D converter trigger input pin
(Continued)
14
MB91345 Series
(Continued)
Pin No.
Pin name
I/O Circuit
type*
P20
96
97
A00
General-purpose I/O port
C
Multi function serial 0 serial data input pin
P21
General-purpose I/O port
A01
C
A02
General-purpose I/O port
C
SCK0
General-purpose I/O port
C
SIN1
100
VCC
Bit 2 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 0 clock I/O pin
P23
A03
Bit 1 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 0 serial data output pin
P22
99
Bit 0 of external address bus output pin.
Enabled when external bus is effective.
SIN0
SOT0
98
Function
Bit 3 of external address bus output pin.
Enabled when external bus is effective.
Multi function serial 1 serial data input pin
⎯
Power supply input pin (3.3 V)
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
15
MB91345 Series
■ I/O CIRCUIT TYPE
Classification
Circuit type
Remarks
X1
Clock input
A
Oscillation circuit
Feedback resistor
X0 : 1 MΩ
X0
STANDBY CONTROL
P-ch
Open drain control
N-ch
Digital output
B
• CMOS level output
IOH = 4 mA
• With open drain output control
• CMOS level hysteresis input
VIH = 0.7 × VCC
• With standby control
• 5V tolerance
Digital input
STANDBY CONTROL
P-ch
P-ch
Open drain control
N-ch
Digital output
C
• CMOS level output
IOH = 4 mA
• With open drain output control
• CMOS level hysteresis input
VIH = 0.8 × VCC
• With standby control
• With pull-up resistor (33 kΩ)
Digital input
STANDBY CONTROL
(Continued)
16
MB91345 Series
Classification
Circuit type
Remarks
P-ch
Digital output
N-ch
Digital output
D
• CMOS level output
IOH = 4 mA
• CMOS level hysteresis input
VIH = 0.8 × VCC
Standby control provided
Without pull-up resistor
Digital input
STANDBY CONTROL
P-ch
P-ch
Open drain control
N-ch
Digital output
E
• CMOS level output
IOH = 4 mA
• With open drain output control
• CMOS level hysteresis input
VIH = 0.8 × VCC
With standby control
• With analog input switch
• With pull-up resistor (33 kΩ)
Analog input
CONTROL
Digital input
STANDBY CONTROL
• CMOS level input
• Without standby control
P-ch
N-ch
F
Digital input
(Continued)
17
MB91345 Series
Classification
Circuit type
P-ch
Remarks
• CMOS hysteresis input
• With pull-up resistor
P-ch
N-ch
G
Digital input
CMOS level output
P-ch
Digital output
H
N-ch
Digital output
• CMOS hysteresis input
• With pull-down resistor
• Without standby control
P-ch
I
N-ch
N-ch
Digital input
P-ch
Digital output
• CMOS level output
• CMOS level hysteresis input
• Without standby control
N-ch
J
Digital output
Digital input
(Continued)
18
MB91345 Series
(Continued)
Classification
Circuit type
Remarks
P-ch
Digital output
N-ch
K
•
•
•
•
CMOS level output
CMOS level hysteresis input
Without standby control
With pull-down resistor
N-ch
Digital output
Digital input
19
MB91345 Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a COMS IC if a voltage greater than VCC pin, or less than VSS pin is applied to input
and output pins, or if an above-rating voltage is applied between VCC pin and VSS pin. If the latch-up occurs,
the significantly increases the power supply current and may cause thermal destruction of an element. Thus,
When you use a CMOS IC, be very careful not to exceed maximum voltage rating.
• Treatment of Unused input pins
Do not leave an unused input pin open, since it may cause a malfunction. Thus, use pull-up or pull-down resistor.
• About power supply pins
If there are multiple VCC pin or VSS pin, from the point of view of device design, pins to be of the same level
are connected the inside of the device to prevent such malfunctioning as latch-up. Be sure to connect all of them
to the power supply and ground externally for reducing unnecessary radiation, prevent malfunctioning of the
strobe signal due to the rise of ground level, and observe the total output current standard. In addition, consideration should be given to connecting VCC/VSS of this device with as low an impedance as possible from the
current supply source. Also, we recommend connecting a ceramic capacitor of about 0.1 µF as a bypass capacitor
between VCC and VSS near this device.
• About crystal oscillator circuit
Noise near the X0 and X1 pins can cause this device to malfunction. Design the PC board such that X0 and X1
pins, crystal oscillator (or ceramic oscillator) , and bypass capacitor to the ground are placed as near one another
as possible. It is strongly recommended to design the PC board artwork with the X0/X1 pins surrounded by a
ground plane, as it expects stable operations.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• About mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to
test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS
pins is as short as possible and the connection impedance is low.
• About operation at power-on
Be sure to set initialized reset (INIT) with INIT pin immediately after power-on.
Immediately after turning on the power, be sure to continue connecting the Low level input to the INIT pin for
the stabilization wait time required for oscillator circuit, to secure the stabilization wait time of the oscillator and
regulator (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value) .
• About oscillation input at power on
When turning on the power, be sure that clock input is maintained until the device is released from the oscillation
stabilization wait state.
• Note on power-on/off sequences
When turning on the power, the output pin may be indeterminate until the internal power supply stabilizes.
20
MB91345 Series
• Note when using external clock
In principle, when using external clock, supply a clock to the X0 pin and an opposite-phase clock signal to the
X1 pin simultaneously. However in this case, the STOP mode (oscillator stop mode) must not be used, because
the X1 pin stops with the “H” output in the STOP mode. At 12.5 MHz or less, the device can be used with the
clock signal supplied only to the X0 pin.
Using an External Clock (Normal Method)
X0
X1
MB91345 series
[The STOP mode (oscillation stop mode) cannot be used.]
Using an External (enabled at 12.5 MHz or lower)
X0
MB91345 series
OPEN X1
Note : The X1 pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0 pin.
• About C pin
MB91345 series has an internal regulator. A bus condenser of 4.7 µF or above should be connected to the C
pin for the regulator.
C
4.7 µF
VSS
• About AVCC pin
MB91345 series has an internal A/D converter. A condenser of approximately 0.1 µF should be connected
between the AVCC pin and AVSS pin.
AVCC
0.1 µF
AVSS
• Treatment of NC pin and OPEN pin
The NC and OPEN pins should always be open.
21
MB91345 Series
• Note when not using emulator
If evaluation MCU on user system is operated without emulator, each input pin on evaluation MCU connected
to the emulator interface on the user system should be handled, as described in the following table. Note that
the switch circuit or other function may be required on user system when designing the MCU.
Emulator Interface Pin Treatment
Evaluation MCU pin name
TRST
Connect to the reset output circuit on the user system.
INIT
Connect to the reset output circuit on the user system.
Others
22
Pin processing
Open.
MB91345 Series
■ RESTRICTIONS
• Common in the series
• Clock control block
Take the oscillation stabilization wait time during Low level input to INIT pin.
• Bit search module
The bit search data register for 0-detection (BSD0) , and bit search data register for 1-detection (BSD1) , and
bit search data register for change point detection (BSDC) are only word-accessible.
• I/O port
Ports are accessed only in bytes.
• Low power consumption mode
• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit8 in TBCR, or
timebase counter control register) and be sure to use the following sequence :
(ldi
#value_of_standby, r0)
(ldi
#_STCR, r12)
stb
r0, @r12
// set STOP/SLEEP bit
ldub
@r12, r0
// Must read STCR
ldub
@r12, r0
// after reading, go into standby mode
nop
// Must insert NOP *5
nop
nop
nop
nop
• Please do not do the following when the monitor debugger is used
• Setting of the break point to the above instructions.
• Execution of the single-stepping for the above instructions.
23
MB91345 Series
• Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated. In either case, the operations before and after an EIT are performed as specified as the device
is designed such that the recovery from the EIT is followed by correct re-processing.
• The instruction just before the DIV0U/DIV0S instruction may cause the following operation, if a user interrupt
or NMI occurs, single-stepping is performed or a break is caused by a data event or emulator menu :
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as shown in (1) .
• If the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt
or NMI trigger even has occurred, the following operations are performed.
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the instructions shown above are executed and the PS register is updated
to the same value as shown in (1) .
• About watchdog timer
MB91345 series has an internal function called “watchdog timer”. This function monitors a program to perform
the reset defer operation within a certain period of time. The watchdog timer resets the CPU if the program
runs out of controls and the reset defer operation is not executed. Thus, once enabled, the watchdog timer
will be up and running until it resets the CPU. However, with one exception, the watchdog timer automatically
defers a reset timing under the condition in which the CPU stops program execution. Refer to the section
describing the watchdog timer functions for the exceptional condition. If the system runs out of control and
develops the above condition, a watchdog reset may not be generated. In that case, please reset (INIT) from
external INIT terminal.
• Note on using the A/D converter
MB91345 series has an internal A/D converter. The AVCC pin should not be supplied with higher voltage than
VCC pin.
• Software reset in synchronous mode
When using the software reset in the synchronous mode, the following two conditions should be satisfied
before setting “0” to the SRST bit in STCR (Standby control register) .
• Set the interrupt enable flag (I-Flag) to interrupt disable (I-Flag = 0) .
• Do not use NMI.
• Debug control when using ICE
• Single-stepping of the RETI instruction
If an interrupt occurs frequently during single stepping, only the relevant interrupt processing routine is executed
repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from
being executed. Do not single-step the RETI instruction for escape. When the debugging of the relevant
interrupt routine no longer requires, perform debugging with that interrupt disabled.
• About operand break
Do not apply a data event break to access to the area containing the address of a stack pointer.
24
MB91345 Series
• Execution of an unused area of Flash memory
Accidently if an unused area (data at 0XFFFF) of Flash memory is executed in an instruction, no break can
be accepted. To avoid this, it is recommended to use the code event address mask feature of the debugger
to break at instruction access to the unused area.
• Interrupt handler for NMI request (tool)
Add the following program to the interrupt handler to prevent the device from malfunctioning when the source
flag is set accidentlly with no ICE connected, for example, due to noise to the DSU pin, which is to be set only
at the break request of the ICE. can be used normally with this program added.
Add place :
Next interrupt handler
Interrupt source : NMI request (tool)
Interrupt number : 13 (decimal) , 0D (hexadecimal)
Offset : 3C8H
TBR default address : 000FFFC8H
Add program
STM (R0, R1)
LDI #0B00H, R0
; 0B00H is the address of DSU break source register
LDI #0, R1
STB R1, @R0
; Clear the break source register
LDM (R0, R1)
RETI
25
MB91345 Series
■ BLOCK DIAGRAM
FR60 Lite
CPU core
Operating macro
for absolute value
32
32
Bit search
DMAC
5 channels
RAM 24 Kbytes (data)
Bus
Converter
Flash 512 Kbytes
D15 ~ D00
A23 ~ A00
RAM 8 Kbytes
X0, X1
MD2 ~ MD0
INIT
32
32 ↔16
Adapter
16
SIN10 ~ SIN0
SOT10 ~ SOT0
SCK10 ~ SCK0
24 channels
External interrupt
11 channels
Multi function serial interface.
(including 2 channels
with built-in FIFO)
AN7 ~ AN0
ADTRG0, ADTRG0-2
8 channels × 1 unit
10-bit A/D Converter
AVRH, AVCC
AVSS/AVRL
ADTRG1, ADTRG1-2
AN15 ~ AN8
8 channels × 1 unit
10-bit A/D Converter
AIN3 ~ AIN0,
BIN3 ~ BIN0,
External
memory
I/F
RD, WR1, WR0
CS3 ~ CS0
PORT
PORT
Clock
control
Interrupt
controller
INT23 ~ INT0
32
2 channels
8/16-bit up down counter
3 channels
16-bit Reload timer
16-bit
Free-run timer
RDY
SYSCLK
TOT2 ~ TOT0
TIN2 ~ TIN0
FRCK0
4 channels
16-bit Input capture
IC3 ~ IC0
4 channels
16-bit Output compare
RT3 ~ RT0
32-bit
Free-run timer
FRCK1
4 channels
32-bit Input capture
IC7 ~ IC4
4 channels
32-bit Output compare
RT7 ~ RT4
ZIN3 ~ ZIN0
PPGF ~ PPGF0
26
16 channels
8/16-bit PPG
MB91345 Series
■ CPU AND CONTROL UNIT
The FR family CPU is a line of high-performance cores based on a RISC architecture while incorporating
advanced instructions for embedded controller applications.
1. Features
• RISC architecture adopted.
Basic instructions : Executed at 1 instruction per cycle
• 32-bit architecture
General purpose registers : 32 bit × 16
• 4G bytes of linear memory space
• Multiplier integrated.
32-bit × 32-bit multiplication : 5 cycles.
16-bit × 16-bit multiplication : 3 cycles
• Enhanced interrupt servicing.
High-speed response (6 cycles) .
Multi-level interrupts support.
Level mask feature (16 levels)
• Enhanced I/O manipulation instructions.
Memory-to-memory transfer instructions
Bit manipulation instructions
• High code efficiency. Basic instruction word length : 16-bit
• Low-power consumption.
Sleep mode / stop mode
• Gear function
27
MB91345 Series
2. Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction bus and data buses are separated. The
32-bit←→16-bit bus converter is connected to a 32-bit bus (F-bus) , providing an interface between the CPU
and peripheral resources. The Harvard←→Princeton bus converter is connected to both of the I-bus and D-bus,
providing an interface between the CPU and the bus controller.
FR CPU
D-bus
I-bus
32
I address
32
External address
24
32
External data
16
Harvard
I data
D address
Data
RAM
D data
32
Address
32
Data
32
32-bit
16-bit
bus converter
Princeton
bus
converter
16
R-bus
Peripherals resource
28
F-bus
Internal I/O
bus controller
MB91345 Series
3. Programming model
Basic programming model
32-bit
Initial Value
R0
XXXX XXXXH
R1
GENERAL
PURPOSE
REGISTERS
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000 H
Program counter
PC
program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
⎯
ILM
⎯
SCR
CCR
Multiply and divide result MDH
register
MDL
29
MB91345 Series
4. Register
General purpose registers
32 bit
Initial Value
R0
XXXX XXXXH
R1
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000 H
Registers R0 to R15 are general purpose registers. The registers are used as the accumulator and memory
access pointers for CPU operations.
Of these 16 registers, the registers listed below are intended for special applications, for which some instructions
are enhanced.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value) .
• PS (Program Status)
This register holds the program status and is divided into the ILM, SCR, and CCR.
All of undefined bits are reserved bits. Reading these bits always returns “0”.
Writing to them has no effect.
bit31
bit20
bit16
bit10 bit8 bit7
⎯
bit0
⎯
ILM
SCR
CCR
PS
• CCR (Condition Code Register)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial Value
⎯
⎯
S
I
N
Z
V
C
- - 00XXXXB
S : Stack flag. Cleared to “0” at a reset.
30
MB91345 Series
I
N
Z
V
C
: Interrupt Enable flag. Cleared to “0” at a reset.
: Negative flag. Initial State at a reset is unspecified.
: Zero flag. Initial State at a reset is unspecified.
: Overflow flag. Initial State at a reset is unspecified.
: Carry flag. Initial State at a reset is unspecified.
• SCR (System Condition code Register)
bit10 bit9
D1
D0
bit8
Initial Value
T
XX0B
Flag for step dividing
Stores intermediate data for stepwise multiplication operations.
Step trace trap flag
A flag specifying whether the step trace trap function is enabled or not.
Emulator uses step trace trap function. The function cannot be used by the user program when using the
emulator.
• ILM (Interrupt Level Mask Register)
bit20 bit19 bit18 bit17 bit16
Initial Value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.
Initialized to “15” (01111B) by a reset.
• PC (Program Counter)
bit31
bit0
Initial Value
XXXXXXXXH
The program counter contains the address of the instruction currently being executed.
The initial value after a reset is indeterminate.
• TBR (Table Base Register)
bit31
bit0
Initial Value
0 0 0 FFC0 0 H
The table base register contains the start address of the vector table used for servicing EIT events.
The initial value after a reset is 000FFC00H.
31
MB91345 Series
• RP (Return Pointer)
bit31
bit0
Initial Value
XXXXXXXXH
The return pointer contains the address to which to return from a subroutine.
When the CALL instruction is executed, the value in the PC is transferred to the RP.
When the RET instruction is executed, the value in the RP is transferred to the PC.
The initial value after a reset is indeterminate.
• SSP (System Stack Pointer)
bit31
bit0
Initial Value
00000000H
The SSP is the system stack pointer and functions as R15 when the S flag is “0”.
The SSP can be explicitly specified.
The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event
occurs.
The initial value after a reset is 00000000H.
• USP (User Stack Pointer)
bit31
bit0
Initial Value
XXXXXXXXH
The USP is the user stack pointer and functions as R15 when the S flag is “1”.
The USP can be explicitly specified.
The initial value after a reset is indeterminate.
This pointer cannot be used by the RETI instruction.
• MDH, MDL (Multiply and Divide register)
bit31
bit0
MDH
MDL
Multiplication and division result register
These registers hold the results of a multiplication or division. Each of them is 32-bit long.
The initial value after a reset is indeterminate.
32
MB91345 Series
■ MODE SETTING
In the FR family, operation mode is set by the mode setting pins (MD2, MD1, MD0) and the mode register
(MODR) .
1. Mode pins
They are three pins of MD2, MD1 and MD0, and specify the contents of the mode vector fetch.
Mode pins
Mode name
Reset vector Access area
MD2
MD1
MD0
0
0
0
Internal ROM mode vector
Internal
Note : In the FR family, external mode vector fetch by multiplex bus is not supported.
2. Mode register (MODR)
The data that are written in the mode register by mode vector fetch is called mode data.
After the mode register (MODR) is set, it operates in the operation mode set by this register.
The mode register is set by all reset source. And Mode data is not written in by the user program.
Note : Conventionally, the address (0000 07FFH) of the mode register for the FR family holds nothing.
Details of the mode register
MODR
0007FDH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
ROMA
WTH1
WTH0
Initial Value
XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits
Be sure to set these bits to “00000B”.
Setting the bits to any value other than “00000B” may result in an unpredictable operation .
[bit2] ROMA (Internal ROM enable bit)
This bit sets to make internal F-bus RAM and F-bus ROM areas valid or not.
ROMA
Function
Remarks
0
External ROM mode
1
Internal ROM mode Embedded F-bus RAM and F-bus ROM become valid.
Embedded F-bus RAM becomes valid, and internal ROM area
(50000H to 100000H) becomes external area.
33
MB91345 Series
[bit1, bit0] WTH1, WTH0 (Bus width specifying bits)
These bits specify bus widths for the external bus mode.
In case of the external bus mode, this value is set in the DBW0 bit of ACR0 (CS0 area) .
34
WTH1
WTH0
Function
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
1
1
⎯
Single chip mode
Remarks
Setting disabled
Single chip mode
MB91345 Series
■ MEMORY SPACE
1. Memory Space
The FR family has 4 Gbytes of logical address space (232 addresses) linearly accessible to the CPU .
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The direct area varies depending on the size of data to be accessed as follows :
→ byte data access
: 000H to 0FFH
→ half word data access : 000H to 1FFH
→ word data access
: 000H to 3FFH
2. Memory Map (MB91F345B/F346B)
Single chip mode
Internal ROM external
bus mode
I/O
I/O
Direct addressing
area
I/O
I/O
Refer to “3. I/O Map”
Access
prohibited
Access
prohibited
Internal
RAM 8 Kbytes
(Data/instruction)
Internal
RAM 8 Kbytes
(Data/instruction)
Internal
RAM 24 Kbytes
(Data)
Internal
RAM 24 Kbytes
(Data)
0000 0000H
0000 0400H
0001 0000H
0003 E000H
0004 0000H
0004 6000H
0005 0000H
Access
prohibited
Access
prohibited
External area
Internal Flash*
512 Kbytes
Internal Flash*
512 Kbytes
0008 0000H
0010 0000H
0020 0000H
FFFF FFFFH
Access
prohibited
Access
prohibited
External area
* : Internal Flash area of MB91F346B is 0008 0000H to 0018 0000H (1 Mbyte.)
35
MB91345 Series
■ I/O MAP
The following table shows the correspondence between the memory space area and each register of the peripheral resource.
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
T-unit
Port Data Register
Read/write attribute, Access unit
(B : Byte, H : Half Word, W : Word)
Initial value after a reset
Register name (First-column register at address 4n; second-column register at
address 4n + 1...)
Location of left-most register (When using word access, the register
in column 1 is in the MSB side of the data.)
Note : Initial values of register bits are represented as follows :
“1” : Initial value is “1”.
“0” : Initial value is “0”.
“X” : Initial value is “indeterminate”.
“−” : No physical register at this location
Access is barred with an undefined data access attribute.
36
MB91345 Series
Address
Register
0
1
2
3
000000H
PDR0 [R/W] B, H PDR1 [R/W] B, H PDR2 [R/W] B, H PDR3 [R/W] B, H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000004H
PDR4 [R/W] B, H PDR5 [R/W] B, H PDR6 [R/W] B, H
XXXXXXXX
XXXXXXXX
----XXXX
PDRC [R/W] B, H PDRD [R/W] B, H PDRE [R/W] B, H
-----XXX
XXXXXXXX
XXXXXXXX
000010H
to
00001CH
ADCS01 [R/W]
00000000
ADERH0 [R/W]
11111111
ADCS00 [R, R/W]
00000000
ADCT0 [R/W]
00010000 00101100
00002CH
ADCR0M [R]
------XX XXXXXXXX
000030H
⎯
000038H
Reserved
⎯
000028H
000034H
⎯
⎯
000020H
000024H
Port Data Registers
⎯
000008H
00000CH
⎯
Block
ADCS11 [R/W]
00000000
ADCR0 [R]
------XX XXXXXXXX
ADSCH0 [R/W]
0---0000
ADECH0 [R/W]
----0000
ADCR1M [R]
------XX XXXXXXXX
AD mirror data
register
ADERH1 [R/W]
11111111
ADCS10 [R, R/W]
00000000
ADCT1 [R/W]
00010000 00101100
ADCR1 [R]
------XX XXXXXXXX
ADSCH1 [R/W]
0----000
A/D converter 1
ADECH1 [R/W]
-----000
⎯
00003CH
A/D converter 0
Reserved
000040H
EIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
INT 0 to INT7
000044H
DICR [R/W]
00000000
HRCL [R, R/W]
0--11111
⎯
DLY / I-unit
000048H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
TMR0 [R]
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R, RW]
00000000 00000000
000050H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
TMR1 [R]
XXXXXXXX XXXXXXXX
⎯
TMCSR1 [R, RW]
00000000 00000000
000054H
Reload Timer 0
Reload Timer 1
(Continued)
37
MB91345 Series
Address
Register
0
1
2
3
000058H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
TMR2 [R]
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R, RW]
00000000 00000000
000060H
000064H
SCR0/IBCR0
[R, R/W]
*
SMR0 [W, R/W]
*
RDR0/TDR0 [R/W]
*
000068H
ISMK0 [R/W]
*
IBSA [R/W]
*
00006CH
FBYTE02 [R/W]
*
FBYTE01 [R/W]
*
000070H
SCR1/IBCR1
[R, R/W]
*
SMR1 [W, R/W]
*
000074H
ISMK1 [R/W]
*
IBSA1 [R/W]
*
00007CH
FBYTE12 [R/W]
*
FBYTE11 [R/W]
*
000080H
SCR2/IBCR2
[R, R/W]
*
SMR2 [W, R/W]
*
000084H
000088H
000094H
000098H
00009CH
BGR00 [R/W]
*
FCR01 [R/W]
*
FCR00 [R/W]
*
SSR1 [R, R/W]
*
ESCR1/IBSR1
[R/W]
*
BGR11 [R/W]
*
BGR10 [R/W]
*
FCR11 [R/W]
*
FCR10 [R/W]
*
SSR2 [R, R/W]
*
ESCR2/IBSR2
[R/W]
*
BGR21 [R/W]
*
BGR20 [R/W]
*
IBSA2 [R/W]
*
Multi function
Serial Interface 0
FIFO 0
Multi function
Serial Interface 1
FIFO 1
Multi function
Serial Interface 2
⎯
⎯
00008CH
000090H
BGR01 [R/W]
*
⎯
RDR2/TDR2 [R/W]
*
ISMK2 [R/W]
*
ESCR0/IBSR0
[R/W]
*
Reload Timer 2
⎯
RDR1/TDR1 [R/W]
*
000078H
SSR0 [R, R/W]
*
Block
SCR3/IBCR3
[R, R/W]
*
SMR3 [W, R/W]
*
RDR3/TDR3 [R/W]
*
ISMK3 [R/W]
*
IBSA3 [R/W]
*
SSR3 [R, R/W]
*
ESCR3/IBSR3
[R/W]
*
BGR31 [R/W]
*
BGR30 [R/W]
*
Multi function
Serial Interface 3
⎯
⎯
(Continued)
38
MB91345 Series
Address
0000A0H
0000A4H
0000A8H
Register
0
1
2
3
SCR4/IBCR4
[R, R/W]
*
SMR4 [W, R/W]
*
SSR4 [R, R/W]
*
ESCR4/IBSR4
[R/W]
*
BGR41 [R/W]
*
BGR40 [R/W]
*
RDR4/TDR4 [R/W]
*
ISMK4 [R/W]
*
IBSA4 [R/W]
*
0000B4H
0000B8H
Multi function
Serial Interface 4
⎯
⎯
0000ACH
0000B0H
Block
SCR5/IBCR5
[R, R/W]
*
SMR5 [W, R/W]
*
RDR5/TDR5 [R/W]
*
ISMK5 [R/W]
*
SSR5 [R, R/W]
*
ESCR5/IBSR5
[R/W]
*
BGR51 [R/W]
*
BGR50 [R/W]
*
IBSA5 [R/W]
*
Multi function
Serial Interface 5
⎯
⎯
0000BCH
0000C0H
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
INT 8 to INT15
0000C4H
EIRR2 [R/W]
00000000
ENIR2 [R/W]
00000000
ELVR2 [R/W]
00000000 00000000
External interrupt
INT 16 to INT 23
0000C8H
to
0000CCH
0000D0H
0000D4H
⎯
CPCLRB/CPCLR [R/W] H
11111111 11111111
TCCSH [R/W] B
00000000
Reserved
TCDT [R/W] H
00000000 00000000
TCCSL [R/W] B
01000000
⎯
⎯
0000D8H
Reserved
0000DCH
IPCPH0/IPCPL0 [R]
XXXXXXXX XXXXXXXX
IPCPH1/IPCPL1 [R]
XXXXXXXX XXXXXXXX
0000E0H
IPCPH2/IPCPL2 [R]
XXXXXXXX XXXXXXXX
IPCPH3/IPCPL3 [R]
XXXXXXXX XXXXXXXX
0000E4H
ICSH01 [R/W]
------00
ICSL01 [R/W]
00000000
16-bit
Free Run Timer 0
ICSH23 [R/W]
------00
16-bit Input Capture
ICSL23 [R/W]
00000000
0000E8H
OCCPH0/OCCPL0 [R/W]
XXXXXXXX XXXXXXXX
OCCPH1/OCCPL1 [R/W]
XXXXXXXX XXXXXXXX
Output Compare
0, 1
0000ECH
OCCPH2/OCCPL2 [R/W]
XXXXXXXX XXXXXXXX
OCCPH3/OCCPL3 [R/W]
XXXXXXXX XXXXXXXX
Output Compare
2, 3
0000F0H
OCS01 [R/W]
11101100 00001100
OCS23 [R/W]
11101100 00001100
Output Compare
0 to 3
Control
(Continued)
39
MB91345 Series
Address
0000F4H
0000F8H
Register
0
1
OCMOD [R/W] B
00000000
2
3
Output Compare
Mode Select
⎯
PWCSR0 [R/W, R] B, H, W
0000000X 00000000
Block
PWCR0 [R] H, W
00000000 00000000
PWC
0000FCH
⎯
PDIVR0 [R/W]
B, H, W
XXXXX000
000100H
PRLH0 [R/W]
B, H, W
XXXXXXXX
PRLL0 [R/W]
B, H, W
XXXXXXXX
PRLH1 [R/W]
B, H, W
XXXXXXXX
PRLL1 [R/W]
B, H, W
XXXXXXXX
000104H
PRLH2 [R/W]
B, H, W
XXXXXXXX
PRLL2 [R/W]
B, H, W
XXXXXXXX
PRLH3 [R/W]
B, H, W
XXXXXXXX
PRLL3 [R/W]
B, H, W
XXXXXXXX
000108H
PPGC0 [R/W]
B, H, W
0000000X
PPGC1 [R/W]
B, H, W
0000000X
PPGC2 [R/W]
B, H, W
0000000X
PPGC3 [R/W]
B, H, W
0000000X
00010CH
PRLH4 [R/W]
B, H, W
XXXXXXXX
PRLL4 [R/W]
B, H, W
XXXXXXXX
PRLH5 [R/W]
B, H, W
XXXXXXXX
PRLL5 [R/W]
B, H, W
XXXXXXXX
000110H
PRLH6 [R/W]
B, H, W
XXXXXXXX
PRLL6 [R/W]
B, H, W
XXXXXXXX
PRLH7 [R/W]
B, H, W
XXXXXXXX
PRLL7 [R/W]
B, H, W
XXXXXXXX
000114H
PPGC4 [R/W]
B, H, W
0000000X
PPGC5 [R/W]
B, H, W
0000000X
PPGC6 [R/W]
B, H, W
0000000X
PPGC7 [R/W]
B, H, W
0000000X
000118H
PRLH8 [R/W]
B, H, W
XXXXXXXX
PRLL8 [R/W]
B, H, W
XXXXXXXX
PRLH9 [R/W]
B, H, W
XXXXXXXX
PRLL9 [R/W]
B, H, W
XXXXXXXX
00011CH
PRLHA [R/W]
B, H, W
XXXXXXXX
PRLLA [R/W]
B, H, W
XXXXXXXX
PRLHB [R/W]
B, H, W
XXXXXXXX
PRLLB [R/W]
B, H, W
XXXXXXXX
000120H
PPGC8 [R/W]
B, H, W
0000000X
PPGC9 [R/W]
B, H, W
0000000X
PPGCA [R/W]
B, H, W
0000000X
PPGCB [R/W]
B, H, W
0000000X
000124H
PRLHC [R/W]
B, H, W
XXXXXXXX
PRLLC [R/W]
B, H, W
XXXXXXXX
PRLHD [R/W]
B, H, W
XXXXXXXX
PRLLD [R/W]
B, H, W
XXXXXXXX
000128H
PRLHE [R/W]
B, H, W
XXXXXXXX
PRLLE [R/W]
B, H, W
XXXXXXXX
PRLHF [R/W]
B, H, W
XXXXXXXX
PRLLF [R/W]
B, H, W
XXXXXXXX
00012CH
PPGCC [R/W]
B, H, W
0000000X
PPGCD [R/W]
B, H, W
0000000X
PPGCE [R/W]
B, H, W
0000000X
PPGCF [R/W]
B, H, W
0000000X
⎯
PPG 0 to PPG F
(Continued)
40
MB91345 Series
Address
Register
0
1
000130H
PPGTRG [R/W] B, H, W
00000000 00000000
000134H
PPGREVC [R/W] B, H, W
00000000 00000000
2
3
⎯
PPGGATEC
[R/W] B
XXXXXX00
⎯
000150H
CPCLRB/CPCLR [R/W] W
11111111 11111111 11111111 11111111
000154H
TCDT [R/W] W
00000000 00000000 00000000 00000000
TCCSH [R/W] B
00000000
Reserved
TCCSL [R/W] B
01000000
32 bit
Free Run Timer 0
⎯
00015CH
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000160H
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000164H
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000168H
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00016CH
ICS45 [R/W]
00000000
⎯
⎯
OCCP4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000174H
OCCP5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000178H
OCCP6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00017CH
OCCP7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCS45 [R/W]
11101100 00001100
32 bit Input Capture
Unit 4 to 7
ICS67 [R/W]
00000000
000170H
000180H
PPG 0-F
⎯
000138H
to
00014CH
000158H
Block
32 bit Output
Compare 4 to 7
OCS67 [R/W]
11101100 00001100
000184H
RCRH1 [W] B, H
00000000
RCRL0 [W] B, H
00000000
UDCR1 [R] B, H
00000000
UDCR0 [R] B, H
00000000
000188H
CCRH0 [R/W]
B, H
00000000
CCRL0 [R/W]
B, H
00000000
⎯
CSR0 [R/W]
B
00000000
00018CH
CCRH1 [R/W]
B, H
00000000
CCRL1 [R/W]
B, H
00000000
⎯
CSR1 [R/W]
B
00000000
Up/Down Counter
0, 1
(Continued)
41
MB91345 Series
Address
Register
0
1
2
3
⎯
000190H
Reserved
000194H
RCRH3 [W] B, H
00000000
RCRL2 [W] B, H
00000000
UDCR3 [R] B, H
00000000
UDCR2 [R] B, H
00000000
000198H
CCRH2 [R/W]
B, H
00000000
CCRL2 [R/W]
B, H
00000000
⎯
CSR2 [R/W]
B
00000000
00019CH
CCRH3 [R/W]
B, H
00000000
CCRL3 [R/W]
B, H
00000000
⎯
CSR3 [R/W]
B
00000000
0001A0H
to
0001ACH
0001B0H
0001B4H
0001B8H
⎯
SCR6/IBCR6
[R, R/W]
*
SMR6 [W, R/W]
*
RDR6/TDR6 [R/W]
*
ISMK6 [R/W]
*
0001C4H
0001C8H
0001D4H
0001D8H
0001DCH
SSR6 [R, R/W]
*
ESCR6/IBSR6
[R/W]
*
BGR61 [R/W]
*
BGR60 [R/W]
*
Multi function
Serial Interface 6
⎯
⎯
SCR7/IBCR7
[R, R/W]
*
SMR7 [W, R/W]
*
RDR7/TDR7 [R/W]
*
ISMK7 [R/W]
*
SSR7 [R, R/W]
*
ESCR7/IBSR7
[R/W]
*
BGR71 [R/W]
*
BGR70 [R/W]
*
IBSA7 [R/W]
*
Multi function
Serial Interface 7
⎯
⎯
0001CCH
0001D0H
Up/Down Counter
2, 3
Reserved
IBSA6 [R/W]
*
0001BCH
0001C0H
Block
SCR8/IBCR8
[R, R/W]
*
SMR8 [W, R/W]
*
RDR8/TDR8 [R/W]
*
ISMK8 [R/W]
*
IBSA8 [R/W]
*
SSR8 [R, R/W]
*
ESCR8/IBSR8
[R/W]
*
BGR81 [R/W]
*
BGR80 [R/W]
*
Multi function
Serial Interface 8
⎯
⎯
(Continued)
42
MB91345 Series
Address
0001E0H
0001E4H
0001E8H
Register
0
1
2
3
SCR9/IBCR9
[R, R/W]
*
SMR9 [W, R/W]
*
SSR9 [R, R/W]
*
ESCR9/IBSR9
[R/W]
*
BGR91 [R/W]
*
BGR90 [R/W]
*
RDR9/TDR9 [R/W]
*
ISMK9 [R/W]
*
IBSA9 [R/W]
*
0001F4H
0001F8H
Multi function
Serial Interface 9
⎯
⎯
0001ECH
0001F0H
Block
SCRA/IBCRA
[R, R/W]
*
SMRA [W, R/W]
*
RDRA/TDRA [R/W]
*
ISMKA [R/W]
*
IBSAA [R/W]
*
SSRA [R, R/W]
*
ESCRA/IBSRA
[R/W]
*
BGRA1 [R/W]
*
BGRA0 [R/W]
*
Multi function
Serial Interface 10
⎯
0001FCH
⎯
000200H
DMACA0 [R/W]
00000000 00000000 00000000 00000000
000204H
DMACB0 [R/W]
00000000 00000000 00000000 00000000
000208H
DMACA1 [R/W]
00000000 00000000 00000000 00000000
00020CH
DMACB1 [R/W]
00000000 00000000 00000000 00000000
000210H
DMACA2 [R/W]
00000000 00000000 00000000 00000000
000214H
DMACB2 [R/W]
00000000 00000000 00000000 00000000
000218H
DMACA3 [R/W]
00000000 00000000 00000000 00000000
00021CH
DMACB3 [R/W]
00000000 00000000 00000000 00000000
000220H
DMACA4 [R/W]
00000000 00000000 00000000 00000000
000224H
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000228H
to
00023CH
⎯
Reserved
000240H
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
DMAC
(Continued)
43
MB91345 Series
Address
Register
0
1
2
3
000244H
to
0003BCH
⎯
0003A0H
DATA_A [-/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003A4H
DATA_B [-/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003A8H
MIN [R/W]
00000000 00000000 00000000 00000000
0003ACH
MAX [R/W]
00000000 00000000 00000000 00000000
0003B0H
ABS [R/W]
00000000 00000000 00000000 00000000
0003B4H
to
0003ECH
⎯
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
DDR0 [R/W] B, H DDR1 [R/W] B, H DDR2 [R/W] B, H DDR3 [R/W] B, H
00000000
00000000
00000000
00000000
000404H
DDR4 [R/W] B, H DDR5 [R/W] B, H DDR6 [R/W] B, H
00000000
00000000
----0000
000408H
00040CH
Reserved
MIN/MAX/ABS
Reserved
Bit Search
⎯
Data Direction
Registers
⎯
DDRC [R/W] B, H DDRD [R/W] B, H DDRE [R/W] B, H
-----000
00000000
00000000
000410H
⎯
000414H
to
00041CH
⎯
Block
⎯
Reserved
(Continued)
44
MB91345 Series
Address
Register
0
1
2
3
000420H
PFR0 [R/W] B, H
00000000
PFR1 [R/W] B, H
00000000
PFR2 [R/W] B, H
00000000
PFR3 [R/W] B, H
00000000
000424H
PFR4 [R/W] B, H
00000000
PFR5 [R/W] B, H
00000000
PFR6 [R/W] B, H
----0000
⎯
00042CH
Registers
⎯
000428H
PFRC [R/W] B, H PFRD [R/W] B, H PFRE [R/W] B, H
-----000
00000000
00000000
000430H
⎯
000434H
to
00043CH
⎯
⎯
Reserved
000440H
ICR00 [R, R/W]
---11111
ICR01 [R, R/W]
---11111
ICR02 [R, R/W]
---11111
ICR03 [R, R/W]
---11111
000444H
ICR04 [R, R/W]
---11111
ICR05 [R, R/W]
---11111
ICR06 [R, R/W]
---11111
ICR07 [R, R/W]
---11111
000448H
ICR08 [R, R/W]
---11111
ICR09 [R, R/W]
---11111
ICR10 [R, R/W]
---11111
ICR11 [R, R/W]
---11111
00044CH
ICR12 [R, R/W]
---11111
ICR13 [R, R/W]
---11111
ICR14 [R, R/W]
---11111
ICR15 [R, R/W]
---11111
000450H
ICR16 [R, R/W]
---11111
ICR17 [R, R/W]
---11111
ICR18 [R, R/W]
---11111
ICR19 [R, R/W]
---11111
000454H
ICR20 [R, R/W]
---11111
ICR21 [R, R/W]
---11111
ICR22 [R, R/W]
---11111
ICR23 [R, R/W]
---11111
000458H
ICR24 [R, R/W]
---11111
ICR25 [R, R/W]
---11111
ICR26 [R, R/W]
---11111
ICR27 [R, R/W]
---11111
00045CH
ICR28 [R, R/W]
---11111
ICR29 [R, R/W]
---11111
ICR30 [R, R/W]
---11111
ICR31 [R, R/W]
---11111
000460H
ICR32 [R, R/W]
---11111
ICR33 [R, R/W]
---11111
ICR34 [R, R/W]
---11111
ICR35 [R, R/W]
---11111
000464H
ICR36 [R, R/W]
---11111
ICR37 [R, R/W]
---11111
ICR38 [R, R/W]
---11111
ICR39 [R, R/W]
---11111
000468H
ICR40 [R, R/W]
---11111
ICR41 [R, R/W]
---11111
ICR42 [R, R/W]
---11111
ICR43 [R, R/W]
---11111
00046CH
ICR44 [R, R/W]
---11111
ICR45 [R, R/W]
---11111
ICR46 [R, R/W]
---11111
ICR47 [R, R/W]
---11111
000470H
to
00047CH
⎯
Block
Interrupt Control Unit
Reserved
(Continued)
45
MB91345 Series
Address
Register
0
1
2
3
000480H
RSRR [R, R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXXX00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
OSCCR [R/W]
XXXXXXXX
⎯
⎯
000488H
⎯
00048CH
000490H
OSCR [R/W]
00000000
000500H
000504H
Stb. Wait Timer
Reserved
PCR0 [R/W] B, H PCR1 [R/W] B, H
00000000
00000000
⎯
PCR5 [R/W] B, H PCR6 [R/W] B, H
00000000
----0000
⎯
Port Pull-up Control
Registers
⎯
000508H
00050CH
⎯
⎯
⎯
PCRC [R/W] B, H PCRD [R/W] B, H PCRE [R/W] B, H
-----000
00000000
00000000
000510H
⎯
000514H
to
00051CH
⎯
⎯
Reserved
000520H
EPFR0 [R/W]
B, H
00000000
EPFR1 [R/W]
B, H
00000000
EPFR2 [R/W]
B, H
11111111
EPFR3 [R/W]
B, H
11111111
000524H
EPFR4 [R/W]
B, H
11111111
EPFR5 [R/W]
B, H
11111111
EPFR6 [R/W]
B, H
----1000
⎯
EPFRE [R/W]
B, H
00000000
⎯
00052CH
Extra Port Function
Registers
⎯
000528H
EPFRC [R/W]
B, H
-----000
Clock Control Unit
Reserved
OSCT [R/W]
XXXXXXXX
000494H
to
0004FCH
Block
EPFRD [R/W]
B, H
00000000
000530H
⎯
000534H
to
000550H
⎯
Reserved
(Continued)
46
MB91345 Series
Address
Register
0
1
2
3
000554H
TTCR0 [R/W]
B, H, W 11110000
000558H
COMP0 [R/W]
COMP2 [R/W]
COMP4 [R/W]
COMP6 [R/W]
B, H, W 00000000 B, H, W 00000000 B, H, W 00000000 B, H, W 00000000
00055CH
TTCR1 [R/W]
B, H, W 11110000
000560H
COMP8 [R/W]
COMP10 [R/W]
COMP12 [R/W]
COMP14 [R/W]
B, H, W 00000000 B, H, W 00000000 B, H, W 00000000 B, H, W 00000000
000564H
to
000574H
⎯
000578H
00057CH
to
00063CH
TSTPR0 [R]
B, H, W 00000000
⎯
TSTPR1 [R]
B, H, W 00000000
⎯
ADTGS [R/W] B
------00
AD Trigger Select
⎯
Reserved
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
00110X00 00000000
000644H
ASR1 [R/W]
00000000 XXXXXXXX
ACR1 [R/W]
0XXX0X00 00X0XXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXX0X00 00X0XXXX
00064CH
ASR3 [R/W]
00000000 XXXXXXXX
ACR3 [R/W]
01XX0X00 00X0XXXX
⎯
000654H
to
00065CH
⎯
T-Unit
000660H
AWR0 [R/W] B, H, W
01111111 11111111
AWR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000668H
to
00067CH
000680H
Timing Generator
Reserved
⎯
000650H
Block
⎯
CSER [R/W] B, H,
W
00000001
⎯
000684H
⎯
000688H
to
0007F8H
⎯
TCR [W] B, H, W
0000XXXX
Not Used
(Continued)
47
MB91345 Series
Address
0007FCH
Register
0
1
⎯
MODR [W]
XXXXXXXX
000800H
to
000AFCH
2
3
⎯
⎯
⎯
Not Used
000B00H
ESTS0 [R/W] B
X0000000
ESTS1 [R/W] B
XXXXXXXX
ESTS2 [R] B
1XXXXXXX
⎯
000B04H
ECTL0 [R/W] B
0X000000
ECTL1 [R/W] B
00000000
ECTL2 [W] B
000X0000
ECTL3 [R/W] B
00X00X11
000B08H
ECNT0 [W] B
XXXXXXXX
ECNT1 [W] B
XXXXXXXX
EUSA [W] B
XXX00000
EDTC [W] B
0000XXXX
ECTL4 [R]
([R/W]) B
-0X00000
ECTL5 [R]
([R/W]) B
----000X
000B0CH
EWPT [R] H
00000000 00000000
000B10H
EDTR0 [W] H
XXXXXXXX XXXXXXXX
Block
EDTR1 [W] H
XXXXXXXX XXXXXXXX
000B14H
to
000B1CH
⎯
000B20H
EIA0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B34H
EIA5 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B48H
EOA0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DSU
(Evaluation
Chip Only)
(Continued)
48
MB91345 Series
Address
Register
0
1
2
000B4CH
EOA1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B64H
EOAM1/EODM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B68H
EOD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B70H
to
000FFCH
⎯
001000H
DMASA0 [R/W]
00000000 00000000 00000000 00000000
001004H
DMADA0 [R/W]
00000000 00000000 00000000 00000000
001008H
DMASA1 [R/W]
00000000 00000000 00000000 00000000
00100CH
DMADA1 [R/W]
00000000 00000000 00000000 00000000
001010H
DMASA2 [R/W]
00000000 00000000 00000000 00000000
001014H
DMADA2 [R/W]
00000000 00000000 00000000 00000000
001018H
DMASA3 [R/W]
00000000 00000000 00000000 00000000
00101CH
DMADA3 [R/W]
00000000 00000000 00000000 00000000
001020H
DMASA4 [R/W]
00000000 00000000 00000000 00000000
001024H
DMADA4 [R/W]
00000000 00000000 00000000 00000000
001028H
to
006FFCH
⎯
3
Block
DSU
(Evaluation
Chip Only)
Reserved
DMAC
Reserved
(Continued)
49
MB91345 Series
(Continued)
Address
Register
0
1
007000H
FLCR [R/W]
01101000
⎯
007004H
FLWC [R/W]
00110011
⎯
007008H
to
007019H
007020H
3
Block
Flash Interface
⎯
WREN [R/W]
00000000
⎯
007024H
to
00702CH
⎯
007030H
WA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007034H
WD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007038H
WA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00703CH
WD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007040H
WA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007044H
WD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007048H
WA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00704CH
WD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007050H
WA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007054H
WD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007058H
WA5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00705CH
WD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007060H
WA6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007064H
WD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007068H
WA7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00706CH
WD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
* : Refer to “Hardware manual” for initial value.
50
2
Reserved
Flash Interface
Flash Interface
MB91345 Series
■ VECTOR TABLE
Interrupt No.
Interrupt factor
HexaDecimal decimal
Interrupt
Offset
level
Address of
TBR default
DMA
transfer
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction
exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (FH)
fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
⎯
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
⎯
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
⎯
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
⎯
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART0 RX/I C0 status
27
1B
ICR11
390H
000FFF90H
UART0 TX
28
1C
ICR12
38CH
000FFF8CH
UART1 RX/I C1 status
29
1D
ICR13
388H
000FFF88H
UART1 TX
30
1E
ICR14
384H
000FFF84H
UART2 RX/I2C2 status
31
1F
ICR15
380H
000FFF80H
UART2 TX
32
20
ICR16
37CH
000FFF7CH
2
2
DMAC
STOP factor
STOP
STOP
STOP
(Continued)
51
MB91345 Series
Interrupt No.
Interrupt factor
HexaDecimal decimal
Interrupt
level
Offset
Address of
TBR default
DMA
DMAC
transfer STOP factor
UART3 RX/TX/SX
33
21
ICR17
378H
000FFF78H
⎯
UART4 RX/TX/SX
34
22
ICR18
374H
000FFF74H
⎯
UART5 RX/TX/SX
35
23
ICR19
370H
000FFF70H
⎯
UART6 RX/TX/SX
36
24
ICR20
36CH
000FFF6CH
⎯
UART7 RX/TX/SX
37
25
ICR21
368H
000FFF68H
⎯
UART8 RX/TX/SX
38
26
ICR22
364H
000FFF64H
⎯
UART9 RX/TX/SX
39
27
ICR23
360H
000FFF60H
⎯
UART10 RX/TX/SX
40
28
ICR24
35CH
000FFF5CH
⎯
A/D Converter 0
41
29
ICR25
358H
000FFF58H
A/D Converter 1
42
2A
ICR26
354H
000FFF54H
PWC (measurement completed, overflow)
43
2B
ICR27
350H
000FFF50H
⎯
System reserved
44
2C
ICR28
34CH
000FFF4CH
⎯
Up/Down Counter 1
45
2D
ICR29
348H
000FFF48H
⎯
Up/Down Counter 2, 3
46
2E
ICR30
344H
000FFF44H
⎯
Timebase Timer Overflow
47
2F
ICR31
340H
000FFF40H
⎯
PPG 0/PPG 1/PPG 4/PPG 5
48
30
ICR32
33CH
000FFF3CH
⎯
PPG 2/PPG 3/PPG 6/PPG 7
49
31
ICR33
338H
000FFF38H
⎯
PPG 8/PPG 9/PPG C/PPG D
50
32
ICR34
334H
000FFF34H
⎯
PPG A/PPG B/PPG E/PPG F
51
33
ICR35
330H
000FFF30H
⎯
Free Running Timer 0
52
34
ICR36
32CH
000FFF2CH
⎯
Free Running Timer 1
53
35
ICR37
328H
000FFF28H
⎯
Input Capture 0/
Input Capture 1/
Input Capture 2/
Input Capture 3
54
36
ICR38
324H
000FFF24H
⎯
Input Capture 4/
Input Capture 5/
Input Capture 6/
Input Capture 7
55
37
ICR39
320H
000FFF20H
⎯
Output Compare 0/
Output Compare 1/
Output Compare 2/
Output Compare 3
56
38
ICR40
31CH
000FFF1CH
⎯
Output Compare 4/
Output Compare 5/
Output Compare 6/
Output Compare 7
57
39
ICR41
318H
000FFF18H
⎯
(Continued)
52
MB91345 Series
(Continued)
Interrupt No.
Interrupt
level
Offset
Address of
TBR default
3A
ICR42
314H
000FFF14H
⎯
59
3B
ICR43
310H
000FFF10H
⎯
External interrupt 16 to
External interrupt 23
60
3C
ICR44
30CH
000FFF0CH
⎯
Up/Down Counter 0
61
3D
ICR45
308H
000FFF08H
⎯
DMA (0 channel to 4 channels)
62
3E
ICR46
304H
000FFF04H
⎯
Delayed interrupt activation
63
3F
ICR47
300H
000FFF00H
⎯
System reserved
(Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved
(Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
System reserved
66
42
⎯
2F4H
000FFEF4H
⎯
System reserved
67
43
⎯
2F0H
000FFEF0H
⎯
System reserved
68
44
⎯
2ECH
000FFEECH
⎯
System reserved
69
45
⎯
2E8H
000FFEE8H
⎯
System reserved
70
46
⎯
2E4H
000FFEE4H
⎯
System reserved
71
47
⎯
2E0H
000FFEE0H
⎯
System reserved
72
48
⎯
2DCH
000FFEDCH
⎯
System reserved
73
49
⎯
2D8H
000FFED8H
⎯
System reserved
74
4A
⎯
2D4H
000FFED4H
⎯
System reserved
75
4B
⎯
2D0H
000FFED0H
⎯
System reserved
76
4C
⎯
2CCH
000FFECCH
⎯
System reserved
77
4D
⎯
2C8H
000FFEC8H
⎯
System reserved
78
4E
⎯
2C4H
000FFEC4H
⎯
System reserved
79
4F
⎯
2C0H
000FFEC0H
⎯
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
Interrupt factor
Decimal
Hexadecimal
System reserved
58
External interrupt 8 to
External interrupt 15
DMA
DMAC
transfer STOP factor
53
MB91345 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Min
Max
VCC
VSS−0.5
VSS + 4.0
V
AVCC
VSS−0.3
VSS + 4.0
V
Input voltage *
VI
VSS−0.3
VSS + 4.0
V
Analog pin input voltage *
VIA
VSS−0.3
AVcc + 0.5
V
Tstg
−40
+125
°C
Power supply voltage *
Analog power supply voltage *
Storage temperature
* : The parameter is based on VSS = AVSS = 0.0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(VSS = AVSS = 0)
Parameter
Symbol
Value
Min
Max
Unit
Operating temperature
Ta
− 40
+ 85
°C
Power supply voltage
VCC
3.0
3.6
V
AVCC
3.0
VCC
V
Analog power supply voltage
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
54
MB91345 Series
3. DC Characteristics
Parameter
Power
supply
current
Symbol
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Pin
Conditions
Value
Unit
Min
Typ
Max
ICC
During normal
operation
Ta = + 25 °C
fcp = 50 MHz,
fcpp = 25 MHz
⎯
65
80
mA
ICCS
SLEEP mode during
normal operation
Ta = + 25 °C
fcp = 50 MHz,
fcpp = 25 MHz
⎯
30
35
mA
In STOP mode
Ta = + 25 °C,
fclk = 0
⎯
66
390
µA
In STOP mode
Ta = + 45 °C,
fclk = 0
⎯
140
760
µA
VCC
ICCH
Remarks
“H” level
input voltage
VIH
⎯
⎯
VCC × 0.7
⎯
VCC
V
P20 to P27,
P30 to P37,
P40 to P47
“L” level
input voltage
VIL
⎯
⎯
VSS
⎯
VCC × 0.3
V
P20 to P27,
P30 to P37,
P40 to P47
“H” level
input voltage
VIH
⎯
⎯
VCC × 0.8
⎯
VCC
V
“L” level
input voltage
VIL
⎯
⎯
VSS
⎯
VCC × 0.2
V
“H” level output
voltage
VOH
⎯
IOH = −4 mA
VCC − 0.5
⎯
VCC
V
“L” level output
voltage
VOL
⎯
IOL = 4 mA
VSS
⎯
0.4
V
Input leak current
IIL
⎯
⎯
−5
⎯
+5
µA
A/D power
supply current
(analog + digital)
⎯
⎯
⎯
⎯
7.2
⎯
mA
At operating A/D
2 unit
⎯
⎯
⎯
⎯
⎯
5
µA
At power down
operation*
A/D reference
power supply
current
(AVRH to VSS)
⎯
⎯
⎯
⎯
940
⎯
µA
At operating A/D
2 unit
AVRH = 3.0 V,
VSS = 0.0 V
⎯
⎯
⎯
⎯
⎯
10
µA
At power down
operation*
* : Current when A/D converter is not operating and the CPU is in stop mode.
55
MB91345 Series
4. AC Characteristics
(1) Main Clock Input Standard
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
Symbol
Pin
Conditions
Value
Min
Typ
Unit
Max
Clock frequency
fC
⎯
Input clock cycle
tCYL
⎯
⎯
80
⎯
ns
Input clock pulse
width
⎯
PWH/tCYL
PWL/tCYL
40
⎯
60
%
Input clock rise time
and fall time
tCF
tCR
⎯
⎯
⎯
5
ns
Internal operating
clock frequency
fCP
⎯
⎯
⎯
50
Peripheral clock cycle
time
tCYCP
X0
⎯
⎯
⎯
12.5
⎯
30
Remarks
MHz
In external clock
MHz CPU core operation clock
⎯
ns
Peripheral clock is
derived from internal
operating clock divided
by 1/1 to 1/16.
tCYL
0.8 × VCC
0.8 × VCC
X0
VSS + 0.4
PWH
VSS + 0.4
PWL
tCF
56
0.8 × VCC
tCR
MB91345 Series
(2) PLL Oscillation Stabilization Wait Time (LOCK UP Time)
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
Symbol
PLL oscillation stabilization wait time
(LOCK UP time)
tLOCK
Value
Min
Max
500
⎯
Unit
Remarks
µs
Wait time until the PLL
oscillation is stable.
(3) Reset Input Standard
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
Reset input time (except power-on)
Value
Symbol
Pin
Conditions
Min
Max
tINTL
INIT
⎯
tCP × 10
⎯
Unit
Remarks
ns
Notes : • tCP is cycle time for CPU operation clock (CLKB) .
• For power-on, input INIT = “L” more than regulator voltage stabilization wait time. If the oscillation
stabilization wait time of used oscillator takes more time than regulator voltage stabilization wait time, input
INIT = “L” until the oscillation is stable.
tINTL
INIT
VIL
VIL
57
MB91345 Series
(4) UART Timing
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK0 to SCK10
SCK ↓ → SOT delay time
tSLOV
SCK0 to SCK10,
SOT0 to SOT10
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK10,
SIN0 to SIN10
SCK ↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
Parameter
Value
Unit
Min
Max
4 tCYCP
⎯
ns
− 20
+ 20
ns
30
⎯
ns
SCK0 to SCK10,
SIN0 to SIN10
20
⎯
ns
tSHSL
SCK0 to SCK10
2 tCYCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK10
2 tCYCP
⎯
ns
SCK ↓ → SOT delay time
tSLOV
⎯
30
ns
Valid SIN → SCK ↑
tIVSH
20
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
20
⎯
ns
Internal shift
clock
operation
SCK0 to SCK10,
External shift
SOT0 to SOT10
clock
SCK0 to SCK10,
operation
SIN0 to SIN10
SCK0 to SCK10,
SIN0 to SIN10
Notes : • AC rating in CLK synchronous mode
• tCYCP is the peripheral clock cycle time.
58
Conditions
MB91345 Series
• Internal shift clock mode
tSCYC
SCK0 to SCK10
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT10
tIVSH
tSHIX
VOH
VOL
VOH
VOL
SIN0 to SIN10
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK10
VOH
VOL
VOL
tSLOV
SOT0 to SOT10
VOH
VOL
tIVSH
SIN0 to SIN10
VOH
VOL
tSHIX
VOH
VOL
59
MB91345 Series
(5) Free-run timer clock, Reload timer event Input , up down counter Input , Input capture Input, Interrupt
Input Timing
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
Input pulse width
Symbol
tTIWH
tTIWL
Pin
Conditions
FRCK0, FRCK1,
TIN0, TIN1,
TIN2,
IC0, IC1,
AIN0, AIN1,
BIN0, BIN1,
ZIN0, ZIN1
Value
Unit
Remarks
⎯
ns
*1
tCYCP × 3
⎯
ns
*2
1.0
⎯
µs
*3
Min
Max
tCYCP × 2
⎯
INT0 to INT23
*1 : tCYCP is cycle time for peripheral clock.
*2 : Except in stop time
*3 : In stop time
FRCK0, FRCK1,
TIN0, TIN1, TIN2,
IC0, IC1,
AIN0, AIN1,
BIN0, BIN1,
ZIN0, ZIN1,
INT0 to INT23
60
tTIWL
tTIWH
VIH
VIL
VIL
VIH
MB91345 Series
(6) A/D Trigger Input Timing
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
A/D trigger input (falling time)
Symbol
Pin
Conditions
tTADTG
ADTRG0,
ADTRG0-2,
ADTRG1,
ADTRG1-2
⎯
Value
Min
Max
tCYCP × 2
⎯
Unit
ns
Remarks
*
* : tCYCP is the peripheral clock cycle time.
tTADTG
ADTRG0, ADTRG0-2,
ADTRG1, ADTRG1-2
VIH
VIL
VIL
61
MB91345 Series
(7) I2C timing
• At master mode operating
Parameter
Symbol
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Conditions
Typical mode
High-speed
mode*3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” period of SCL
clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” period of SCL
clock
tHIGH
4.0
⎯
0.6
⎯
µs
SCL↓ → SDA output
delay time
tDLDAT
⎯
5 × M*1
⎯
5 × M*1
ns
tBUS
4.7
⎯
1.3
⎯
µs
2 × M*1
⎯
2 × M*1
⎯
µs
Bus free time
between [STOP
condition] and
[START condition]
SDA data input hold
time (vs. SCL↓)
tHDDAT
SDA data input setup
time (vs. SCL↑)
tSUDAT
250
⎯
100*2
⎯
ns
Setup time of
[repeat START
condition]
SCL↑ → SDA↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Hold time of [repeat
START condition]
SDA↓ → SCL↓
tHDSTA
4.0
⎯
0.6
⎯
µs
Setup time of [STOP
condition]
SCL↑ → SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
R = 1 kΩ
C = 50 pF*4
Remarks
After that, the
first clock pulse
is generated.
*1 : M = Resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies
a requirement of “tSUDAT ≥ 250 ns”.
When a device does not extend the “L” period of the SCL signal, the next data must be outputted to the SDA
line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
62
MB91345 Series
• At slave mode operating
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
Symbol
Conditions
High-speed
mode*3
Typical mode
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” period of SCL
clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” period of SCL
clock
tHIGH
4.0
⎯
0.6
⎯
µs
SCL ↓ → SDA
output delay time
tDLDAT
⎯
5 × M*1
⎯
5 × M*1
ns
Bus free time between [STOP condition and START
condition]
tBUS
4.7
⎯
1.3
⎯
µs
SDA data input hold
time (vs. SCL↓)
tHDDAT
2 × M*1
⎯
2 × M*1
⎯
µs
SDA data input setup
time (vs. SCL↑)
tSUDAT
250
⎯
100*2
⎯
ns
Setup time of [repeat
START condition]
SCL ↑ → SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Hold time of [repeat
START condition]
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
Setup time of [STOP
condition]
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
µs
R = 1 kΩ
C = 50 pF*4
Remarks
After that, the
first clock pulse
is generated.
*1 : M = Resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies
a requirement of “tSUDAT ≥ 250 ns”.
When the device does not extend the “L” period of the SCL signal, the next data must be outputted to the SDA
line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
63
MB91345 Series
(8) Regulator Voltage Wait Time
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = −40 °C to + 85 °C)
Parameter
Regulator voltage wait time
64
Symbol
tREG
Value
Min
Max
250
⎯
Unit
µs
Remarks
Wait time until the regulator
voltage is stable
MB91345 Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, AVRH = 3.0 V to 3.6 V, Ta = −40 °C to + 85 °C)
Value
Parameter
Unit
Min
Typ
Max
⎯
⎯
10
bit
−3.0
⎯
+3.0
LSB
Nonlinear error*1
−2.5
⎯
+2.5
LSB
Differential linear error*1
−1.9
⎯
+1.9
LSB
Zero transition voltage*1
−1.5
+0.5
+2.5
LSB
AVRH−3.5
AVRH−1.5
AVRH+0.5
LSB
0.6
⎯
⎯
µs
⎯
⎯
µs
1.1
⎯
µs
Resolution
Total error*
1
Full transition voltage*
1
Minimum comparison time*2
Minimum sampling time*2
Conversion time
0.3*3
0.9*
3
Remarks
AVCC = 3.3 V,
AVRH = 3.3 V
Not including sampling
time
Power supply current
(analog + digital)
⎯
7.2
⎯
mA
At operating A/D 2 unit
⎯
⎯
5
µA
At power down operation*4
Reference power supply
current
(between AVRH and AVRL)
⎯
940
⎯
µA
At operating A/D 2 unit
AVRH = 3.0 V,
AVRL = 0.0 V
⎯
⎯
10
µA
At power down operation*4
Analog input capacitance
⎯
⎯
20
pF
Interchannel disparity
⎯
⎯
4
LSB
*1 : Measured in the CPU sleep state.
*2 : Depends on the clock cycle supplied to the peripheral resource.
*3 : No external load
*4 : Current when the A/D converter is not operating and the CPU is in stop mode
65
MB91345 Series
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. If
the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input circuit model
R
Analog input pin
Comparator
C
During sampling : ON
R
C
1.5 kΩ (Max) 20.0 pF (Max)
MB91F345B/F346B
Note : The values are reference values.
• The relationship between the external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
100
20
90
18
External impedance (kΩ)
External impedance (kΩ)
[External impedance = 0 kΩ to 100 kΩ]
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
Minimum sampling time (µs)
66
35
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
Minimum sampling time (µs)
8
MB91345 Series
• A/D Converter Block Electrical Characteristics
• Resolution
Analog variations recognized by an A/D converter.
• Linearity error
Deviation of actual conversion characteristics from an ideal line, which is across zero-transition point
(“00 0000 0000” ←→ “00 0000 0001”) and full-scale transition point (“11 1111 1110” ←→ “11 1111 1111”).
• Differential linearity error
Deviation from ideal value of input voltage, which is required for changing output code by 1 LSB.
• Total error
Difference between actual value and ideal value. The error includes zero-transition error, full-scale transition
error, and linearity error.
Total error
3FFH
Actual
characteristic
3FEH
1.5 LSB'
{1 LSB' (N − 1) + 0.5 LSB'}
Digital output
3FDH
004H
VNT
003H
(Actual measured
value)
002H
Actual
characteristic
001H
Ideal
characteristics
0.5 LSB'
AVSS
Analog input
AVRH
AVRH − AVSS
[V]
1024
VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
Total error of digital output N =
1 LSB'
1 LSB' (ideal value) =
VNT : Transition voltage for digital output to change from (N + 1) H to NH.
VOT' (ideal value) = AVSS + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
(Continued)
67
MB91345 Series
(Continued)
Linearity error
Differential linearity error
3FFH
{1 LSB' (N − 1) + VOT}
3FDH
N + 1H
VFST
(Actual
measured
value)
004H
VNT
(Actual
measured
value)
003H
Digital output
3FEH
Digital output
Actual conversion characteristic
Actual conversion
characteristic
NH
Ideal characteristics
VFST
(Actual
measured
value)
N − 1H
Actual conversion
characteristic
Ideal characteristics
002H
001H
N − 2H
VOT (Actual measured value)
AVSS
Analog input
VNT
(Actual measured
value)
AVRH
AVSS
Actual conversion
characteristic
Analog input
VNT − {1 LSB' × (N − 1) + VOT}
[LSB]
1 LSB'
V (N+1) T − VNT
Differential linearity error of digital output N =
−1[LSB]
1 LSB'
VFST − VOT
1 LSB =
[V]
1022
Linearity error of digital output N =
VOT : Transition voltage for digital output to change from (000) H to (001) H.
VFST : Transition voltage for digital output to change from (3FE) H to (3FF) H.
• About errors
• As |AVRH − AVSS| becomes smaller, values of relative errors grow larger.
68
AVRH
MB91345 Series
6. Flash Memory Write/Erase Characteristics
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Conditions
Value
Min
Typ
Max
Unit
Remarks
Sector erase time
⎯
⎯
1
15
s
Excludes 00H programming
prior erasure
Byte write time
⎯
⎯
6
100
µs
Not including system-level
overhead time
Chip write time
⎯
⎯
3.4
56
s
Not including system-level
overhead time
Erase/write cycle
⎯
10000
⎯
⎯
cycle
Average
Ta = + 55 °C
10
⎯
⎯
year *
Flash memory data
retain period
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 55 °C) .
69
MB91345 Series
■ ORDERING INFORMATION
Part number
MB91F345BPFT-GE1
MB91F346BPFT-GE1
70
Package
100-pin plastic TQFP
(FPT-100P-M18)
MB91345 Series
■ PACKAGE DIMENSIONS
100-pin plastic TQFP
(FPT-100P-M18)
100-pin plastic TQFP
(FPT-100P-M18)
Lead pitch
0.40 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.40g
Code(Reference)
P-TFQFP100-12 × 12-0.40
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
75
0.145±0.055
(.006±.002)
51
76
50
0.08(.003)
Details of "A" part
1.10±0.10
(.043±.004)
INDEX
0˚~8˚
26
100
0.10±0.05
(.004±.002)
(Stand off)
"A"
0.25(.010)
LEAD No.
1
0.40(.016)
C
0.60±0.15
(.024±.006)
25
0.18±0.05
(.007±.002)
0.07(.002)
M
2003 FUJITSU LIMITED F100029S-c-3-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
71
MB91345 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
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operation of the device with respect to use based on such
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Please note that Fujitsu will not be liable against you and/or any
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F0703