AvnetCore: Datasheet Version 1.0, July 2006 UTOPIA Level 2 Link Intended Use: — ATM Cell Processors — ATM Switch Fabrics Features: — Function compatible with ATM Forum af-phy-0017.000 & wr_data wr_enb wr_clk a_full increment af-phy-0039.000 TX FIFO rd_data rd_enb decrement empty flag TX Master egr_data egr_addr egr_soc egr_enb_n egr_clav egr_prty egr_clk tex t FIFO RX — Up to 31 PHYs supported — 8/16 bit interfaces supported — 52/54 byte cells supported — Simple system side FIFO interface ing_perr rd_data rd_enb rd_clk flag decrement — Asynchronous/synchronous FIFO using RAM — Simple system side FIFO interface wr_data wr_enb soc increment a_full RX Master ing_data ing_addr ing_soc ing_enb_n ing_clav ing_prty ing_clk Targeted Devices: — Axcelerator Family Core Deliverables: — Netlist Version > Netlist compatible with the Actel Designer place and route tool > Compiled RTL simulation model, compliant with the Actel Libero® environment — RTL Version > VHDL Source Code — All Block Diagram > User Guide > Test Bench UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 2 defines the interface between the ATM or LINK layer and a Physical Layer (PHY) device. The UTOPIA level 2 standard defines a full duplex interface with a Master/Slave format. The Slave or LINK layer device responds to the requests from the PHY or Master device. The Master performs PHY arbitration and initiates data transfers to and from the Slave. The ATM forum has defined the UTOPIA Level 2 as either 8 or 16 bits in width, at up to 50MHz, supporting an OC12 channel at 622Mbps. Synthesis and Simulation Support: — Synthesis: Synplicity — Simulation: ModelSim — Other tools supported upon request Verification: — Test Bench — Test Vectors Functional Description This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface. Please consult the appropriate standards document for all external signaling. TX MASTER The TX master is responsible for polling the phys and internal queues in order to send cells to the slave device. Width Direction EGR_CLK Signal 1 Input Description EGR_DATA 8/16 Output Utopia Data Bus. 8 or 16 bits selectable EGR_ADDR 5 Output Utopia Address Bus used for polling EGR_SOC 1 Output Utopia Start of Cell signal used to flag the first byte/word in the cell EGR_ENB_N 1 Output Utopia Enable signal used for selection EGR_CLAV 1 Input EGR_PRTY 1 Output RD_DATA N*8/16 Input RD_ENB N Output Internal FIFO Read Enable Signal DECREMENT N Output Internal signal used to decrement cell available counter EMPTY N Input Internal FIFO Empty flag FLAG N Input Internal signal used to indicate that there is a cell waiting to be sent for this queue 25/50 MHz Utopia Clock for all registers in this block Utopia Cell Available signal used to indicate that the phy has room for a cell Utopia Parity used for odd parity on EGR_DATA Internal FIFO Bus Table 1: TX Master Signal List TX FIFO The TX FIFO contains the RAM FIFO and the packet counter block. The packet counter is responsible for generating the cell available flags for the rest of the design. Every time a cell is written into the FIFO increment gets set and the cell count goes up, and when a cell is read decrement is set and the cell count goes down. The cell available “flag” is set when there is at least one cell in the FIFO that needs to be read. The FIFO operates in synchronous and asynchronous systems and can hold 9 cells. There is one FIFO per PHY polled. Signal Width Direction Description WR_CLK 1 Input System Clock for all registers in this block WR_DATA N*8/16 Input Write data bus for FIFO WR_ENB N Input Write enable signal for FIFO INCREMENT N Input Increment signal for packet counter block A_FULL N Output RD_CLK 1 Input Almost full for FIFO indicates that the FIFO does not have enough room for an additional cell. Read clock for the FIFO = EGR_CLK for all read registers in this block RD_DATA N*8/16 Output RD_ENB N Input Read enable signal for the FIFO DECREMENT N Input Decrement signal for packet counter block EMPTY N Output Read data bus for the FIFO Indicates when FIFO is empty Table 2: TX FIFO Signal List RX MASTER The RX master is responsible for polling the PHYs and internal queues in order to send cells to the slave device. Width Direction ING_CLK Signal 1 Input 25/50 MHz Utopia Clock for all registers in this block Description ING_DATA 8/16 Input Utopia Data Bus. 8 or 16 bits selectable ING_ADDR 5 Output ING_SOC 1 Input ING_ENB_N 1 Output ING_CLAV 1 Input Utopia Cell Available signal used to indicate that the phy has a cell is ready for transmission ING_PRTY 1 Input Utopia Parity used for odd parity on EGR_DATA ING_PERR N Output Internal signal used to indicate that a parity error was detected on ING_DATA WR_DATA N*8/16 Output Internal FIFO Bus WR_ENB N Output Internal FIFO Write Enable Signal INCREMENT N Output A_FULL N Input Utopia Address Bus used for polling Utopia Start of Cell signal used to flag the first byte/word in the cell Utopia Enable signal used for selection Internal signal used to increment cell available counter Internal FIFO almost full flag indicates that the FIFO cannot accept another cell Table 3: RX Master Signal List RX FIFO The RX FIFO contains the RAM FIFO and the packet counter block. The packet counter is responsible for generating the cell available flags for the rest of the design. Every time a cell is written into the FIFO increment gets set and the cell count goes up, and when a cell is read decrement is set and the cell count goes down. The cell available “flag” is set when there is at least one cell in the FIFO that needs to be read. The FIFO operates in synchronous and asynchronous systems and can hold 9 cells. There is one FIFO per PHY polled. If there is a SOC-SOC error the FIFO will discard all previous data and use the current data as the first byte in the new cell. Width Direction WR_CLK Signal 1 Input Write Clock for the FIFO = ING_CLK for all write registers in this block Description WR_DATA N*8/16 Input Write data bus for FIFO WR_ENB N Input Write enable signal for FIFO INCREMENT N Input Increment signal for packet counter block A_FULL N Output RD_CLK 1 Input RD_DATA N*8/16 Output RD_ENB N Input Read enable signal for the FIFO DECREMENT N Input Decrement signal for packet counter block EMPTY N Output Almost full for FIFO indicates that the FIFO does not have enough room for an additional cell. System Clock for all read registers in this block Read data bus for the FIFO Indicates when FIFO is Empty Table 4: RX FIFO Signal List DATA FORMATTING The data will be written into the FIFO in 8/16 bit increments. If the 16-bit Utopia interface is selected then the MSB will be in bits (15:8) and the LSB will be in (7:0). MSB (15:8) LSB (7:0) Figure 1: Data Formatting egr_data egr_addr egr_soc egr_enb_n egr_clav egr_prty egr_clk wr_data wr_enb wr_clk a_full increment TX FIFO TX Master ing_perr ing_data ing_addr ing_soc ing_enb_n ing_clav ing_prty ing_clk rd_data rd_enb rd_clk flag decrement RX FIFO MDS8076 RX Master Figure 1: Logic Symbol Device Requirements MC-ACT-UL2LINK (UTOPIA Level 2 LINK Interface) Device Speed Ingress / Egress C cells R cells Tiles RAM's A3P250 88 / 88 MHz - - 1833 (30%) 4 APA075 77 / 62 MHz - - 2163 (70%) 8 AX125 108 / 98 MHz 812 (60%) 640 (95%) - 4 Table 1: Device Utilization and Performance* *Note: These numbers obtained with 1 channel and 16-bit data size. Verification and Compliance The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error signals. This core has also been used successfully in customer designs. Signal Descriptions The following signal descriptions define the IO signals. Signal Width Direction Description WR_DATA N*8/16 Input Write data bus for FIFO WR_ENB N Input Write enable signal for FIFO WR_CLK 1 Input System Clock for all registers in this block A_FULL N Output INCREMENT N Input ING_PERR N Output Internal signal used to indicate that a parity error was detected on ING_DATA RD_DATA N*8/16 Output Read data bus for the FIFO RD_ENB N Input Read enable signal for the FIFO System Clock for all read registers in this block Almost full for FIFO indicates that the FIFO does not have enough room for an additional cell Increment signal for packet counter block RD_CLK 1 Input FLAG N Output DECREMENT N Input EGR_DATA 8/16 Output Utopia Data Bus, 8 or 16 bits selectable EGR_ADDR 5 Output Utopia Address Bus used for polling EGR_SOC 1 Output Utopia Start of Cell signal used to flag the first byte/word in the cell EGR_ENB_N 1 Output EGR_CLAV 1 Input EGR_PRTY 1 Output Signal used to indicate that there is a cell waiting to be sent for this queue Decrement signal for packet counter block Utopia Enable signal used for selection Utopia Cell Available signal used to indicate that the PHY has room for a cell Utopia Parity used for odd parity on EGR_DATA EGR_CLK 1 Input 25/50 MHz Utopia Clock for all registers in this block ING_DATA 8/16 Input Utopia Data Bus, 8 or 16 bits selectable ING_ADDR 5 Output ING_SOC 1 Input ING_ENB_N 1 Output ING_CLAV 1 Input Utopia Cell Available signal used to indicate that the PHY has a cell is ready for transmission ING_PRTY 1 Input Utopia Parity used for odd parity on EGR_DATA ING_CLK 1 Input 25/50 MHz Utopia Clock for all registers in this block Utopia Address Bus used for polling Utopia Start of Cell signal used to flag the first byte/word in the cell Utopia Enable signal used for selection Table 2: Core I/O Signals Timing Since the ATM Forum specification fully defines the line side of the UTOPIA Level 2 interface, timing for that is not replicated here. Instead, only user (FIFO) interface timing information is presented here. The figure below shows the functional timing for FIFO reads and writes. RD_CLK RD_CLK RD_ADDR RD_ADDR A0 A0 A1 A1 ... ... A52 A52 A53 A53 D0 D0 D1 D1 ... ... A52 D52 A0 A0 A1 A1 ... ... A52 A52 A53 A53 D0 D0 D1 D1 ... ... A52 D52 A53 D53 RD_ENB RD_ENB RD_DATA RD_DATA DECREMENT DECREMENT WR_CLK WR_CLK WR_ADDR WR_ADDR WR_ENB WR_ENB WR_DATA WR_DATA INCREMENT INCREMENT Figure 3: FIFO Timing A53 D53 Recommended Design Experience For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero v2.2 Integrated Design Environment (IDE) and preferably with Synplify and ModelSim. Ordering Information The CORE is provided under license from Avnet Memec for use in Actel programmable logic devices. Please contact Avnet Memec for pricing and more information. Information furnished by Avnet Memec is believed to be accurate and reliable. Avnet Memec reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Avnet Memec does not make any commitment to update this information. Avnet Memec assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Avnet Memec will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Avnet Memec does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Avnet Memec. AvnetCore products are not intended for use in life support appliances, devices, or systems. Use of a AvnetCore product in such application without the written consent of the appropriate Avnet Design officer is prohibited. All trademarks, registered trademarks, or service marks are property of their respective owners. Contact Information: North America 10805 Rancho Bernardo Road Suite 100 San Diego, California 92127 United States of America TEL: +1 858 385 7500 FAX: +1 858 385 7770 Europe, Middle East & Africa Mattenstrasse 6a CH-2555 Brügg BE Switzerland TEL: +41 0 32 374 32 00 FAX: +41 0 32 374 32 01 Ordering Information: Part Number MC-ACT-UL2LINK-NET MC-ACT-UL2LINK-VHDL Hardware Actel UL2LINK Netlist Actel UL2LINK VHDL Resale Contact for pricing Contact for pricing www.em.avnet.com/actel Copyright © 2006 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners. AEM-MC-ACT-UL2LINK-DS v.1.0-July 2006