FREESCALE MC68HC705P9VDW

Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC68HC705P9
Technical Data
M68HC05
Microcontrollers
MC68HC705P9/D
Rev. 4.0, 4/2002
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
MC68HC705P9
Freescale Semiconductor, Inc...
Technical Data
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
MC68HC908GT16 • MC68HC908GT8
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Technical Data
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© Motorola, Inc.,1996, 2002
Advance Information
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Revision History
Revision History
Date
Revision
Level
April, 2002
4.0
Page
Number(s)
Description
Throughout
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Reformatted to meet current publication standards
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MC68HC908GT16 • MC68HC908GT8
Technical Data
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Technical Data — MC68HC705P9
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21
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Section 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 25
Section 3. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Section 4. Central Processor Unit (CPU) . . . . . . . . . . . . 43
Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 65
Section 6. Low Power Modes. . . . . . . . . . . . . . . . . . . . . . 75
Section 7. Parallel Input/Output (I/O) Ports . . . . . . . . . . 81
Section 8. Computer Operating Properly
Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . . 95
Section 9. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 10. Serial Input/Output Port (SIOP) . . . . . . . . . 117
Section 11. Analog-to-Digital Converter (ADC) . . . . . . 129
Section 12. Electrical Specifications. . . . . . . . . . . . . . . 137
Section 13. Mechanical Specifications . . . . . . . . . . . . . 149
Section 14. Ordering Information . . . . . . . . . . . . . . . . . 151
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
MC68HC705P9 — Rev. 4.0
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Technical Data
List of Sections
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List of Sections
Technical Data
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MC68HC705P9 — Rev. 4.0
List of Sections
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MOTOROLA
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Technical Data — MC68HC705P9
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Section 2. Pin Descriptions
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.1
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.2.1
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.2.2
Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . 28
2.3.2.3
External Clock Connections. . . . . . . . . . . . . . . . . . . . . . . 28
2.3.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.6
PB7/SCK–PB5/SDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.7
PC7/VRH–PC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.8
PD7/TCAP and PD5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.9
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MC68HC705P9 — Rev. 4.0
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Table of Contents
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Table of Contents
Section 3. Memory
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .33
3.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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3.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.6.1
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . 37
3.6.1.1
EPROM Programming Register . . . . . . . . . . . . . . . . . . . .38
3.6.1.2
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.6.2
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.7
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Section 4. Central Processor Unit (CPU)
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.6.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Technical Data
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4.7.1.4
4.7.1.5
4.7.1.6
4.7.1.7
4.7.1.8
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.7.2.4
4.7.2.5
4.7.3
4.8
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . 53
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . 54
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .55
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . 56
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 5. Resets and Interrupts
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.2.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.3
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3
Low-Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.4.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.4.2
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.3.1
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.3.2
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .71
5.4.3.3
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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Section 6. Low Power Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Section 7. Parallel Input/Output (I/O) Ports
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.3.1
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . 83
7.3.2
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .83
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.4.1
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . 85
7.4.2
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .86
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.1
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . 88
7.5.2
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . .89
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.6.1
Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . 91
7.6.2
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . .92
Section 8. Computer Operating Properly
Watchdog (COP)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.1
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.2
COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .97
Technical Data
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8.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.6
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.7.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
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Section 9. Timer
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.4.1
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.1.1
PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.1.2
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
9.5
Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.7
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.7.1
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.7.2
Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.7.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.7.4
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.7.5
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.7.6
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . 115
9.8
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.8.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.8.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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Section 10. Serial Input/Output Port (SIOP)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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10.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.4.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.4.1.1
PB7/SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.4.1.2
PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.4.1.3
PB6/SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.4.2 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.5
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.7.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.8.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
10.8.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Section 11. Analog-to-Digital Converter (ADC)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.4.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.4.1.1
PC7/VRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.4.1.2
PC6/AN0–PC3/AN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
11.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.6
Timing and Electrical Characteristics . . . . . . . . . . . . . . . . . . . 133
Technical Data
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Table of Contents
11.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11.7.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 134
11.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.8.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
11.8.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Freescale Semiconductor, Inc...
Section 12. Electrical Specifications
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.3
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 139
12.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.5
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.6
5.0-Volt DC Electrical Characteristics
12.7
3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 142
12.8
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.9
Typical Supply Current vs. Internal Clock Frequency. . . . . . . 144
. . . . . . . . . . . . . . . . . 141
12.10 Maximum Supply Current vs. Internal Clock Frequency. . . . .145
12.11 5.0-Volt Control Timing
12.12 3.3 V Control Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Section 13. Mechanical Specifications
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.3
28-Pin PDIP — Case #710 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.4
28-Pin Cerdip — Case #733. . . . . . . . . . . . . . . . . . . . . . . . . . 150
13.5
28-Pin SOIC — Case #751F . . . . . . . . . . . . . . . . . . . . . . . . . 150
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Table of Contents
Section 14. Ordering Information
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Index
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Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Technical Data
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List of Figures
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Figure
Title
1-1
MC68HC705P9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .23
2-1
2-2
2-3
2-4
2-5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bypassing Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . 28
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3-1
3-2
3-3
3-4
3-5
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . . 38
Bootloader Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4-1
4-2
4-3
4-4
4-5
4-6
CPU Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .48
5-1
5-2
5-3
5-4
5-5
5-6
5-7
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
External Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Figure
Title
6-1
6-2
6-3
6-4
Stop Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
STOP Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
WAIT Instruction Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
STOP/WAIT Clock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
Parallel I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . 82
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . 83
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . 85
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . 86
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port C Data Register (PORTC). . . . . . . . . . . . . . . . . . . . . . . . . 88
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . 89
Port C I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Port D Data Register (PORTD). . . . . . . . . . . . . . . . . . . . . . . . . 91
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . . 92
Port D I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8-1
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Timer I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 102
Input Capture Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Input Capture Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 105
Timer Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Input Capture Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Output Compare Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Timer Overflow Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . 109
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . 110
Timer Registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . .112
Timer Register Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Alternate Timer Registers (ATRH and ATRL). . . . . . . . . . . . . 113
Alternate Timer Register Reads . . . . . . . . . . . . . . . . . . . . . . .113
Technical Data
16
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Figure
Title
Page
9-16
9-17
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . . 114
Output Compare Registers (OCRH and OCRL) . . . . . . . . . . . 115
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SIOP I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 119
SIOP Data/Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Master/Slave SIOP Shift Register Operation . . . . . . . . . . . . . 123
SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . 125
SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . 126
SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
11-2 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11-3 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . .134
11-4 ADC Data Register (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12-1
12-2
12-3
12-4
12-5
Typical High-Side Driver Characteristics . . . . . . . . . . . . . . . . 143
Typical Low-Side Driver Characteristics . . . . . . . . . . . . . . . . . 143
Typical Supply Current vsInternal Clock Frequency. . . . . . . . 144
Maximum Supply Current vsInternal Clock Frequency. . . . . . 145
Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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List of Figures
Technical Data
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List of Tables
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Table
Title
1-1
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3-1
Bootloader Function Selection . . . . . . . . . . . . . . . . . . . . . . . . . 40
4-1
4-2
4-3
4-4
4-5
4-6
4-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . .54
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 55
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5-1
5-2
5-3
5-4
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
External Interrupt Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . 70
External Interrupt Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . 70
Reset/Interrupt Vector Addresses. . . . . . . . . . . . . . . . . . . . . . . 73
7-1
7-2
7-3
7-4
Port A Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Port B Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port C Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port D Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9-1
9-2
9-3
Timer Characteristics (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . 105
Timer Characteristics (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . 105
Timer Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10-1
10-2
SIOP Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . 124
SIOP Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . 124
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List of Tables
Table
Title
Page
ADC Characteristics (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . .133
ADC Input Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . 135
14-1
Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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11-1
11-2
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Section 1. General Description
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1.1 Contents
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Features
Features of the MC68HC705P9 include:
•
Four peripheral modules
– 16-bit input capture/output compare timer
– Synchronous serial I/O port (SIOP)
– 4-channel, 8-bit analog-to-digital converter (ADC)
– Computer operating properly (COP) watchdog
•
20 bidirectional input/output (I/O) port pins and one input-only port
pin
•
On-chip oscillator with connections for:
– Crystal
– Ceramic resonator
– External clock
•
2104 bytes of EPROM/OTPROM
– 48 bytes of page zero EPROM/OTPROM
– Eight locations for user vectors
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General Description
•
128 bytes of user RAM
•
Bootloader ROM
•
Memory-mapped I/O registers
•
Fully static operation with no minimum clock speed
•
Power-saving stop, wait, and data-retention modes
•
Available packages:
Freescale Semiconductor, Inc...
– 28-pin plastic dual in-line package (PDIP)
– 28-pin small outline integrated circuit (SOIC)
– 28-pin ceramic dual in-line package (CERDIP)
1.3 Programmable Options
The options in Table 1-1 are programmable in the mask option register.
Table 1-1. Programmable Options
Feature
Option
COP watchdog
Enabled
or
Disabled
External interrupt pin triggering
Negative-edge triggering only
or
Negative-edge and low-level triggering
SIOP data format
MSB first
or
LSB first
Technical Data
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General Description
Structure
1.4 Structure
PA7
RESET
ACCUMULATOR
M68HC05
MCU
SDI
SDO
INDEX REGISTER
RESET
VRH
STACK POINTER
0 0 0 0 0 0 0 0 1 1
AN0
PROGRAM COUNTER
0 0 0
AN1
AN2
CONDITION CODE REGISTER
1 1 1 H I N C Z
AN3
PORT A
PA5
DIVIDE
BY 2
INTERNAL CLOCK
COP
WATCHDOG
VDD
PB7/SCK
PB6/SDI
PB5/SDO
PC7/VRH
PC6/AN0
PC5/AN1
PC4/AN2
PC3/AN3
PC2
PC1
PORT D
INTERNAL
OSCILLATOR
PA2
PC0
TO ADC
AND
SIOP
DATA DIRECTION
REGISTER D
OSC2
PA3
PA0
CPU CLOCK
OSC1
PA4
PA1
PORT B
SIOP
SCK
IRQ/VPP
PA6
PORT C
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
ADC
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RAM — 128 BYTES
DATA DIRECTION REGISTER C
BOOTLOADER ROM — 240 BYTES
DATA DIRECTION
REGISTER B
DATA DIRECTION REGISTER A
EPROM/OTPROM — 2104 BYTES
PD5
PD7/TCAP
TCAP
POWER
VSS
DIVIDE
BY 4
CAPTURE/COMPARE
TIMER
TCMP
Figure 1-1. MC68HC705P9 Block Diagram
MC68HC705P9 — Rev. 4.0
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General Description
Technical Data
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General Description
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Technical Data — MC68HC705P9
Section 2. Pin Descriptions
2.1 Contents
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2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.1
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.2.1
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.2.2
Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . 28
2.3.2.3
External Clock Connections. . . . . . . . . . . . . . . . . . . . . . . 28
2.3.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.6
PB7/SCK–PB5/SDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.7
PC7/VRH–PC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.8
PD7/TCAP and PD5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.9
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Pin Descriptions
RESET
1
28
VDD
IRQ/V PP
2
27
OSC1
PA7
3
26
OSC2
PA6
4
25
PD7/TCAP
PA5
5
24
TCMP
PA4
6
23
PD5
PA3
7
22
PC0
PA2
8
21
PC1
PA1
9
20
PC2
PA0
10
19
PC3/AN3
PB5/SDO
11
18
PC4/AN2
PB6/SDI
12
17
PC5/AN1
PB7/SCK
13
16
PC6/AN0
VSS
14
15
PC7/VRH
Figure 2-1. Pin Assignments
2.3 Pin Functions
2.3.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single 5-V power supply.
Technical Data
26
VSS
Very fast signal transitions occur
MCU
on the MCU pins, placing high
C1
short-duration current demands
0.1 µF
on the power supply. To prevent
noise problems, take special
C2
+
care to provide good power
supply bypassing at the MCU as
VDD
Figure 2-2 shows. Place the
Figure 2-2. Bypassing
bypass capacitors as close as
Recommendation
possible to the MCU. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
VDD
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2.2 Pin Assignments
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Pin Descriptions
Pin Functions
2.3.2 OSC1 and OSC2
•
Crystal
•
Ceramic resonator
•
External clock signal
The frequency of the on-chip oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
2.3.2.1 Crystal Connections
NOTE:
MCU
XTAL
27 pF
27 pF
Figure 2-3. Crystal Connections
Use an AT-cut crystal. Do not use a strip or tuning fork crystal. The MCU
may overdrive or have the incorrect characteristic impedance for a strip
or tuning fork crystal.
MC68HC705P9 — Rev. 4.0
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10 MΩ
OSC2
The circuit in Figure 2-3 shows a
typical crystal oscillator circuit
for an AT-cut, parallel resonant
crystal. Follow the crystal
supplier’s recommendations, as
the crystal parameters
determine the external
component values required to
provide reliable startup and
maximum stability. The load
capacitance values used in the
oscillator circuit design should
include all stray layout
capacitances. To minimize
output distortion, mount the
crystal and capacitors as close
as possible to the pins.
OSC1
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The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
The oscillator can be driven by any of the following:
Technical Data
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Pin Descriptions
NOTE:
CERAMIC
RESONATOR
OSC2
MCU
OSC1
To reduce cost, use a ceramic
resonator in place of the crystal.
Figure 2-4 shows a ceramic
resonator circuit. For the values
of any external components,
follow the recommendations of
the resonator manufacturer. The
load capacitance values used in
the oscillator circuit design
should include all stray layout
capacitances. To minimize
output distortion, mount the
resonator and capacitors as
close as possible to the pins.
Figure 2-4. Ceramic Resonator
Connections
Because the frequency stability of ceramic resonators is not as high as
that of crystal oscillators, using a ceramic resonator may degrade the
performance of the ADC.
2.3.2.3 External Clock Connections
An external clock from another
CMOS-compatible device can
drive the OSC1 input, with the
OSC2 pin unconnected, as
Figure 2-5 shows.
OSC2
MCU
OSC1
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2.3.2.2 Ceramic Resonator Connections
UNCONNECTED
EXTERNAL
CMOS CLOCK
2.3.3 RESET
A logic zero on the RESET pin
forces the MCU to a known
startup state. The RESET pin
input circuit contains an internal
Schmitt trigger to improve noise
immunity.
Figure 2-5. External Clock
Connections
Technical Data
28
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Pin Descriptions
Pin Functions
2.3.4 IRQ/VPP
The IRQ/VPP pin has the following functions:
•
Applying asynchronous external interrupt signals
•
Applying VPP, the EPROM/OTPROM programming voltage
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2.3.5 PA7–PA0
PA7–PA0 are general-purpose bidirectional I/O port pins. Use data
direction register A to configure port A pins as inputs or outputs.
2.3.6 PB7/SCK–PB5/SDO
Port B is a 3-pin bidirectional I/O port that shares its pins with the SIOP.
Use data direction register B to configure port B pins as inputs or
outputs.
2.3.7 PC7/VRH–PC0
Port C is an 8-pin bidirectional I/O port that shares five of its pins with the
ADC. Use data direction register C to configure port C pins as inputs or
outputs.
2.3.8 PD7/TCAP and PD5
Port D is a 2-pin I/O port that shares one of its pins with the
capture/compare timer. Use data direction register D to configure port D
pins as inputs or outputs.
2.3.9 TCMP
The TCMP pin is the output compare pin for the capture/compare timer.
MC68HC705P9 — Rev. 4.0
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Pin Descriptions
Technical Data
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MC68HC705P9 — Rev. 4.0
Pin Descriptions
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Technical Data — MC68HC705P9
Section 3. Memory
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3.1 Contents
3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .33
3.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.6.1
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . 37
3.6.1.1
EPROM Programming Register . . . . . . . . . . . . . . . . . . . .38
3.6.1.2
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.6.2
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.7
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 Features
Features include:
•
2104 bytes of EPROM/OTPROM
– 48 bytes of page zero EPROM/OTPROM
– Eight locations for user vectors
•
128 bytes of user RAM
•
Bootloader ROM
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3.3 Memory Map
$0000
↓
$001F
I/O REGISTERS (32 BYTES)
$0020
↓
$004F
PAGE ZERO USER EPROM (48 BYTES)
$0050
↓
$007F
UNIMPLEMENTED (48 BYTES)
PORT A DATA REGISTER (PORTA)
PORT B DATA REGISTER (PORTB)
PORT C DATA REGISTER (PORTC)
PORT D DATA REGISTER (PORTD)
DATA DIRECTION REGISTER A (DDRA)
DATA DIRECTION REGISTER B (DDRB)
DATA DIRECTION REGISTER C (DDRC)
DATA DIRECTION REGISTER D (DDRD)
TIMER CONTROL REGISTER (TCR)
TIMER STATUS REGISTER (TSR)
INPUT CAPTURE REGISTER HIGH (ICRH)
INPUT CAPTURE REGISTER LOW (ICRL)
OUTPUT COMPARE REGISTER HIGH (OCRH)
OUTPUT COMPARE REGISTER LOW (OCRL)
TIMER REGISTER HIGH (TRH)
TIMER REGISTER LOW (TRL)
ALTERNATE TIMER REGISTER HIGH (ATRH)
ALTERNATE TIMER REGISTER LOW (ATRL)
EPROM PROGRAMMING REGISTER (EPROG)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
ADC DATA REGISTER (ADDR)
$001D
ADC STATUS/CONTROL REGISTER (ADSCR)
$001E
RESERVED
$001F
TIMER INTERRUPT VECTOR HIGH
$1FF8
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UNIMPLEMENTED
$0080
↓
$00FF
RAM (128 BYTES)
$0100
↓
$08FF
USER EPROM (2048 BYTES)
$0900
MASK OPTION REGISTER
$0901
↓
$1EFF
UNIMPLEMENTED (5631 BYTES)
$1F00
↓
$1FEF
BOOTLOADER ROM (240 BYTES)
$1FF0
COP CONTROL REGISTER
$1FF1
↓
$1FF7
RESERVED
$1FF8
↓
$1FFF
USER VECTOR EPROM (8 BYTES)
SIOP CONTROL REGISTER (SCR)
SIOP STATUS REGISTER (SSR)
SIOP DATA REGISTER (SDR)
UNIMPLEMENTED
TIMER INTERRUPT VECTOR LOW
$1FF9
EXTERNAL INTERRUPT VECTOR HIGH
$1FFA
EXTERNAL INTERRUPT VECTOR LOW
$1FFB
SOFTWARE INTERRUPT VECTOR HIGH
$1FFC
SOFTWARE INTERRUPT VECTOR LOW
$1FFD
RESET VECTOR HIGH
$1FFE
RESET VECTOR LOW
$1FFF
Figure 3-1. Memory Map
Technical Data
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Input/Output Register Summary
3.4 Input/Output Register Summary
Addr.
$0000
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$0001
$0002
$0003
$0004
$0005
$0006
$0007
Name
Read:
Port A Data Register
(PORTA) Write:
See page 83.
Reset:
Read:
Port B Data Register
(PORTB) Write:
See page 85.
Reset:
Read:
Port C Data Register
(PORTC) Write:
See page 89.
Reset:
Read:
Port D Data Register
(PORTD) Write:
See page 92.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
PC2
PC1
PC0
0
0
0
Unaffected by reset
0
PB7
0
PB5
Unaffected by reset
PC7
PC6
PC5
PC4
PC3
Unaffected by reset
0
PD7
1
0
PD5
Unaffected by reset
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 83.
Reset:
0
Read:
Data Direction Register B
DDRB7
(DDRB) Write:
See page 86.
Reset:
0
Read:
Data Direction Register C
DDRC7
(DDRC) Write:
See page 89.
Reset:
0
Read:
Data Direction Register D
(DDRD) Write:
See page 92.
Reset:
PB6
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
0
0
0
0
DDRB6
DDRB5
0
0
0
0
0
0
0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRD5
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 3-2. I/O Register Summary (Sheet 1 of 4)
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Addr.
Name
$0008
Unimplemented
$0009
Unimplemented
Read:
SIOP Control Register
(SCR) Write:
See page 125.
Reset:
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$000A
Read:
SIOP Status Register
(SSR) Write:
See page 126.
Reset:
$000B
Read:
SIOP Data Register
(SDR) Write:
See page 127.
Reset:
$000C
$000D
Bit 7
6
5
4
3
2
1
Bit 0
0
SPE
0
MSTR
0
0
0
0
0
0
0
0
0
0
0
0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Unaffected by reset
Unimplemented
↓
$0011
Unimplemented
Read:
Timer Control Register
(TCR) Write:
See page 109.
Reset:
$0012
Read:
Timer Status Register
(TSR) Write:
See page 110.
Reset:
$0013
$0014
Read:
Input Capture Register High
(ICRH) Write:
See page 114.
Reset:
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Unaffected by reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 3-2. I/O Register Summary (Sheet 2 of 4)
Technical Data
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Input/Output Register Summary
Addr.
Name
Read:
Input Capture Register Low
(ICRL) Write:
See page 114.
Reset:
$0015
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$0016
$0017
Read:
Output Compare Register High
(OCRH) Write:
See page 115.
Reset:
Read:
Output Compare Register Low
(OCRL) Write:
See page 115.
Reset:
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
1
Bit 0
Unaffected by reset
Bit 15
Bit 7
13
12
11
6
5
4
3
Unaffected by reset
Read:
Timer Register Low
(TRL) Write:
See page 112.
Reset:
Bit 7
Read:
Alternate Timer Register High
(ATRH) Write:
See page 113.
Reset:
Bit 15
Read:
Alternate Timer Register Low
(ATRL) Write:
See page 113.
Reset:
Bit 7
Read:
EPROM Programming Register
(EPROG) Write:
See page 38.
Reset:
0
$001B
14
Unaffected by reset
Bit 15
$0019
$001C
6
Read:
Timer Register High
(TRH) Write:
See page 112.
Reset:
$0018
$001A
Bit 7
14
13
12
11
Reset initializes TRH to $FF
6
5
4
3
Reset initializes TRL to $FC
14
13
12
11
Reset initializes ATRH to $FF
6
5
4
3
2
Reset initializes ATRL to $FC
0
0
0
0
0
LATCH
R
R
R
R
R
EPGM
R
Unaffected by reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 3-2. I/O Register Summary (Sheet 3 of 4)
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Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADC Data Register
(ADDR) Write:
See page 136.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADC Status/Control Register
(ADSCR) Write:
See page 134.
Reset:
CCF
CH2
CH1
CH0
$001D
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$001E
0
0
ADRC
ADON
0
0
0
0
0
0
0
0
Reserved Read:
R
R
R
R
R
R
R
R
Read:
Mask Option Register
(MOR) Write:
See page 42.
Reset:
0
0
0
0
0
SIOP
IRQ
COPE
$001F
$0900
Unaffected by reset
Read:
COP Register
(COPR) Write:
See page 97.
Reset:
$1FF0
Unaffected by reset
R
R
R
R
0
R
R
R
COPC
Unaffected by reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 3-2. I/O Register Summary (Sheet 4 of 4)
3.5 RAM
The 128 addresses from $0080–$00FF are RAM locations. The CPU
uses the top 64 RAM addresses, $00C0–$00FF, as the stack. Before
processing an interrupt, the CPU uses five bytes of the stack to save the
contents of the CPU registers. During a subroutine call, the CPU uses
two bytes of the stack to store the return address. The stack pointer
decrements when the CPU stores a byte on the stack and increments
when the CPU retrieves a byte from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
Technical Data
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EPROM/OTPROM
3.6 EPROM/OTPROM
An MCU with a quartz window has 2104 bytes of erasable,
programmable ROM (EPROM). The quartz window allows EPROM
erasure with ultraviolet light.
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NOTE:
Keep the quartz window covered with an opaque material except when
programming the MCU. Ambient light may affect MCU operation.
In an MCU without the quartz window, the EPROM cannot be erased
and serves as 2104 bytes of one-time programmable ROM (OTPROM).
The following addresses are user EPROM/OTPROM locations:
•
$0020–$004F
•
$0100–$08FF
•
$1FF8–$1FFF (reserved for user-defined interrupt and reset
vectors)
The mask option register (MOR) is an EPROM/OTPROM location at
address $0900.
3.6.1 EPROM/OTPROM Programming
The two ways to program the EPROM/OTPROM are:
•
Manipulating the control bits in the EPROM programming register
to program the EPROM/OTPROM on a byte-by-byte basis
•
Activating the bootloader ROM to download the contents of an
external memory device to the on-chip EPROM/OTPROM
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3.6.1.1 EPROM Programming Register
The EPROM programming register contains the control bits for
programming the EPROM/OTPROM.
$001C
Bit 7
6
5
4
3
Read:
0
0
0
0
0
2
1
Bit 0
0
LATCH
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
EPGM
R
0
0
0
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R = Reserved
Figure 3-3. EPROM Programming Register (EPROG)
LATCH — EPROM Bus Latch
This read/write bit latches the address and data buses for
EPROM/OTPROM programming. Clearing the LATCH bit
automatically clears the EPGM bit. EPROM/OTPROM data cannot be
read while the LATCH bit is set. Resets clear the LATCH bit.
1 = Address and data buses configured for EPROM/OTPROM
programming
0 = Address and data buses configured for normal operation
EPGM bit— EPROM Programming
This read/write bit applies the voltage from the IRQ/VPP pin to the
EPROM/OTPROM. To write the EPGM bit, the LATCH bit must
already be set. Clearing the LATCH bit also clears the EPGM bit.
Resets clear the EPGM bit.
1 = EPROM/OTPROM programming power switched on
0 = EPROM/OTPROM programming power switched off
NOTE:
Writing logic ones to both the LATCH and EPGM bits with a single
instruction sets LATCH and clears EPGM. LATCH must be set first by a
separate instruction.
Bits 7–3 and Bit 1— Reserved
Bits 7–3 and bit 1 are factory test bits that always read as logic zeros.
Technical Data
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EPROM/OTPROM
Take the following steps to program a byte of EPROM/OTPROM:
1. Apply 16.5 V to the IRQ/VPP pin.
2. Set the LATCH bit.
3. Write to any EPROM/OTPROM address.
4. Set the EPGM bit for a time, tEPGM, to apply the programming
voltage.
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5. Clear the LATCH bit.
3.6.1.2 Bootloader ROM
The bootloader ROM, located at addresses $1F00–$1FEF, contains
routines for copying an external EPROM to the on-chip
EPROM/OTPROM.
The bootloader copies to the following EPROM/OTPROM addresses:
•
$0020–$004F
•
$0100–$0900
•
$1FF0–$1FFF
The addresses of the code in the external EPROM must match the
MC68HC705P9 addresses. The bootloader ignores all other addresses.
Figure 3-4 shows the circuit for downloading to the on-chip
EPROM/OTPROM from a 2764 EPROM. The bootloader circuit includes
an external 12-bit counter to address the external EPROM. Operation is
fastest when unused external EPROM addresses contain $00. The
bootloader function begins when a rising edge occurs on the RESETpin
while the VPP voltage is on the IRQ/VPP pin, and the PD7/TCAP pin is at
logic one.
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D0
A0
Q1
D1
A1
Q2
D2
A2
Q3
D3
A3
Q4
D4
A4
Q5
D5
A5
Q6
D6
A6
Q7
D7
A7
Q8
CE
A8
Q9
OE
A9
Q10
A10
Q11
A11
Q12
10 kΩ
1
S1
RESET
1 µF
PB5
PD7
11
25
MC14040B
2764
MC68HC705P9
10
VPP 2 IRQ/V
PA0
PP
2 MHz
27
9
OSC1
PA1
26
8
OSC2
PA2
7
PA3
6
PA4
10 MΩ
5
PA5
4
PA6
3
PA7
VDD
A12
VDD
RST
CLK
10 kΩ
17
PC5/AN1
VDD
PC1
PC2
16
PROGRAM
13
20
VDD
PC6/AN0
10 kΩ
PB7/SCK
330 Ω
PC4
VERIFY
12
21
PB6/SDI
PC3
10 kΩ
18
S2
19
S3
330 Ω
Figure 3-4. Bootloader Circuit
The logical states of the PC4/AN2 and PC3/AN3 pins select the
bootloader function, as Table 3-1 shows.
Table 3-1. Bootloader Function Selection
PC4/AN2
PC3/AN3
Function
1
1
Program and verify
1
0
Verify only
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Memory
EPROM/OTPROM
Complete the following steps to bootload the MCU:
1. Turn off all power to the circuit.
2. Install the EPROM containing the code to be downloaded.
3. Install the MCU.
4. Select the bootloader function:
a. Open switches S2 and S3 to select the program and verify
function.
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b. Open only switch S2 to select only the verify function.
5. Close switch S1.
6. Turn on the VDD power supply.
CAUTION:
Turn on the VDD power supply before turning on the VPP power supply.
7. Turn on the VPP power supply.
8. Open switch S1. The bootloader code begins to execute. If the
PROGRAM function is selected, the PROGRAM LED turns on
during programming. If the VERIFY function is selected, the
VERIFY LED turns on when verification is successful. The
PROGRAM and VERIFY functions take about 10 seconds.
9. Close switch S1.
10. Turn off the VPP power supply.
CAUTION:
Turn off the VPP power supply before turning off the VDD power supply.
11. Turn off the VDD power supply.
3.6.2 EPROM Erasing
The erased state of an EPROM bit is zero. Erase the EPROM by
exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537
angstroms. Position the ultraviolet light source one inch from the
EPROM. Do not use a shortwave filter.
Cerdip packages have a transparent window for erasing the EPROM
with ultraviolet light. In the windowless PDIP and SOIC packages, the
2104 EPROM bytes function as one-time programmable ROM
(OTPROM).
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3.7 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that is
programmable only with the bootloader function. The MOR controls:
•
LSB first or MSB first SIOP data transfer
•
Edge-triggered or edge- and level-triggered external interrupt pin
•
Enabled or disabled COP watchdog
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To program the MOR, use the 5-step procedure given in 3.6.1.1 EPROM
Programming Register. Write to address $0900 in step 3.
$0900
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
SIOP
IRQ
COPE
0
0
0
Write:
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
= Unimplemented
Figure 3-5. Mask Option Register (MOR)
SIOP — Serial I/O Port
The SIOP bit controls the shift direction into and out of the SIOP shift
register.
1 = SIOP data transferred LSB first (bit 0 first)
0 = SIOP data transferred MSB first (bit 7 first)
IRQ — Interrupt Request
The IRQ bit makes the external interrupt function of the IRQ/VPP pin
level-triggered as well as edge-triggered.
1 = IRQ/VPP pin negative-edge triggered and low-level triggered
0 = IRQ/VPP pin negative-edge triggered only
COPE — COP Enable
COPE enables the COP watchdog. In applications that have wait
cycles longer than the COP watchdog timeout period, the COP
watchdog can be disabled by not programming the COPE bit to logic
one.
1 = COP watchdog enabled
0 = COP watchdog disabled
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Section 4. Central Processor Unit (CPU)
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4.1 Contents
4.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.6.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7.1.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.7.1.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.7.1.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.7.1.7
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.7.1.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.7.2
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.7.2.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . 53
4.7.2.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . 54
4.7.2.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .55
4.7.2.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . 56
4.7.2.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.7.3
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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4.2 Features
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Features include:
•
2.1-MHz bus frequency
•
8-bit accumulator
•
8-bit index register
•
13-bit program counter
•
6-bit stack pointer
•
Condition code register with five status flags
•
62 instructions
•
Eight addressing modes
•
Power-saving stop, wait, and data-retention modes
4.3 Introduction
The central processor unit (CPU) consists of a CPU control unit, an
arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit
fetches and decodes instructions. The ALU executes the instructions.
The CPU registers contain data, addresses, and status bits that reflect
the results of CPU operations.
4.4 CPU Control Unit
The CPU control unit fetches and decodes instructions during program
operation. The control unit selects the memory locations to read and
write and coordinates the timing of all CPU operations.
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Central Processor Unit (CPU)
Arithmetic/Logic Unit
ARITHMETIC/LOGIC UNIT
CPU CONTROL UNIT
7
6
5
4
3
2
1
0
ACCUMULATOR (A)
7
6
5
4
3
2
1
0
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INDEX REGISTER (X)
15 14 13 12 11 10
9
8
7
6
0
0
0
0
1
1
15 14 13 12 11 10
9
8
7
6
0
0
0
0
0
0
5
4
3
2
1
0
STACK POINTER (SP)
5
4
3
2
1
0
0
PROGRAM COUNTER (PC)
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 4-1. CPU Programming Model
4.5 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and
manipulation operations decoded from the instruction set by the CPU
control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register
(CCR).
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4.6 CPU Registers
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The M68HC05 CPU contains five registers that control and monitor MCU
operation:
•
Accumulator
•
Index register
•
Stack pointer
•
Program counter
•
Condition code register
CPU registers are not memory mapped.
4.6.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic and logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 4-2. Accumulator (A)
4.6.2 Index Register
The index register can be used for data storage or as a counter. In the
indexed addressing modes, the CPU uses the byte in the index register
to determine the effective address of the operand.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 4-3. Index Register (X)
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Central Processor Unit (CPU)
CPU Registers
4.6.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
stack location to be used. During a reset or after the reset stack pointer
instruction (RSP), the stack pointer is preset to $00FF. The address in
the stack pointer decrements after a byte is stacked and increments
before a byte is unstacked.
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Read:
Bit
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
5
4
3
2
1
Bit
0
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 4-4. Stack Pointer (SP)
The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
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4.6.4 Program Counter
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The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The three most significant bits
of the program counter are ignored internally and appear as 000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit
15
14
13
0
0
0
12
11
10
9
8
7
6
5
4
3
2
Bit
0
1
Read:
Write:
Reset:
Loaded with vector from $1FFE and $1FFF
Figure 4-5. Program Counter (PC)
4.6.5 Condition Code Register
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
Read:
Bit 7
6
5
1
1
1
Write:
Reset:
1
1
1
= Unimplemented
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
U = Unaffected
Figure 4-6. Condition Code Register (CCR)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The halfcarry flag is required for binary-coded decimal (BCD) arithmetic
operations.
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Central Processor Unit (CPU)
Instruction Set
I — Interrupt Mask
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Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic zero, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is set, the interrupt request is latched. Normally, the CPU processes
the latched interrupt as soon as the interrupt mask is cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
4.7 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
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4.7.1 Addressing Modes
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The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
4.7.1.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
4.7.1.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
4.7.1.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
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Central Processor Unit (CPU)
Instruction Set
4.7.1.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
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When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
4.7.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
4.7.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
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4.7.1.7 Indexed, 16-Bit Offset
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Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
4.7.1.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
4.7.2 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
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Central Processor Unit (CPU)
Instruction Set
4.7.2.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 4-1. Register/Memory Instructions
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Instruction
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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4.7.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 4-2. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR (1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET
use only direct addressing.
2. TST is an exception to the read-modify-write sequence because
it does not write a replacement value.
Technical Data
54
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Central Processor Unit (CPU)
Instruction Set
4.7.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
Freescale Semiconductor, Inc...
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
Table 4-3. Jump and Branch Instructions
Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Continued on next page
MC68HC705P9 — Rev. 4.0
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Central Processor Unit (CPU)
Table 4-3. Jump and Branch Instructions (Continued)
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
4.7.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 4-4. Bit Manipulation Instructions
Instruction
Bit Clear
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Bit Set
Technical Data
56
Mnemonic
BSET
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Central Processor Unit (CPU)
Instruction Set
4.7.2.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 4-5. Control Instructions
Freescale Semiconductor, Inc...
Instruction
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
MC68HC705P9 — Rev. 4.0
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Mnemonic
Technical Data
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Central Processor Unit (CPU)
4.7.3 Instruction Set Summary
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Description
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
C
Branch if Carry Bit Clear
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
C
—
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
Mn ← 0
BCS rel
Branch if Carry Bit Set (Same as BLO)
BEQ rel
BHCC rel
BHCS rel
Branch if Half-Carry Bit Set
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
BIH rel
Branch if IRQ Pin High
— —
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
— —
REL
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
b0
PC ← (PC) + 2 + rel ? C = 0
Clear Bit n
—
b0
b7
BCLR n opr
—
— —
0
b7
BCC rel
A ← (A) + (M)
Add without Carry
Arithmetic Shift Right
A ← (A) + (M) + (C)
Add with Carry
— — — — —
DIR
DIR
DIR
DIR
— — — — —
DIR
DIR
DIR
DIR
(b0)
(b1)
(b2)
(b3)
(b4)
(b5)
(b6)
(b7)
ff
ff
Cycles
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
H I N Z C
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
5
3
3
6
5
5
3
3
6
5
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
Technical Data
58
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 4-6. Instruction Set Summary (Sheet 1 of 6)
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Instruction Set
H I N Z C
Operand
Cycles
Freescale Semiconductor, Inc...
BIL rel
Operation
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 2 of 6)
— — — — —
REL
2E
rr
3
—
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
Description
PC ← (PC) + 2 + rel ? IRQ = 0
Branch if IRQ Pin Low
Effect on
CCR
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
REL
23
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
Mn ← 1
— —
— — — —
— — — — —
REL
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
(b0)
(b1)
(b2)
(b3)
(b4)
(b5)
(b6)
(b7)
REL
20
rr
3
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
21
rr
3
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
(b0)
(b1)
(b2)
(b3)
(b4)
(b5)
(b6)
(b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR
DIR
DIR
DIR
— — — — —
DIR
DIR
DIR
DIR
(b0)
(b1)
(b2)
(b3)
(b4)
(b5)
(b6)
(b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
rr
6
— — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
MC68HC705P9 — Rev. 4.0
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Central Processor Unit (CPU)
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP
JMP
JMP
JMP
JMP
opr
opr
opr,X
opr,X
,X
3F
4F
5F
6F
7F
dd
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
—
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
—
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
Technical Data
60
DIR
INH
INH
IX1
IX
Effect on
CCR
— — 0 1 —
— —
— —
— —
— —
— —
— —
—
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
Freescale Semiconductor, Inc...
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 3 of 6)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC705P9 — Rev. 4.0
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Central Processor Unit (CPU)
Instruction Set
LDA
LDA
LDA
LDA
LDA
LDA
#opr
opr
opr
opr,X
opr,X
,X
LDX
LDX
LDX
LDX
LDX
LDX
#opr
opr
opr
opr,X
opr,X
,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
A ← (M)
Load Accumulator with Memory Byte
—
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
—
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
DIR
INH
INH
IX1
IX
Logical Shift Left (Same as ASL)
Unsigned Multiply
— —
C
0
b7
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
INH
42
Negate Byte (Two’s Complement)
NOP
No Operation
C
— — 0
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— —
b0
0
b7
— — — — —
— —
X ← (M)
Load Index Register with Memory Byte
MUL
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— —
— — — — —
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
— —
C
— —
b7
b0
MC68HC705P9 — Rev. 4.0
MOTOROLA
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
ff
ff
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
—
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
39
49
59
69
79
dd
DIR
INH
INH
IX1
IX
Cycles
Description
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
EXT
IX2
IX1
IX
Effect on
CCR
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Address
Mode
Source
Form
Operand
Table 4-6. Instruction Set Summary (Sheet 4 of 6)
ff
2
3
4
5
4
3
5
3
3
6
5
Technical Data
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Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
36
46
56
66
76
dd
— — — — —
INH
9C
2
INH
80
9
— — — — —
INH
81
6
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
H I N Z C
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
C
b7
Subtract Memory Byte and Carry Bit from
Accumulator
— —
b0
A ← (A) – (M) – (C)
— —
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX
STX
STX
STX
STX
opr
opr
opr,X
opr,X
,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SWI
Store Index Register In Memory
Subtract Memory Byte from Accumulator
Software Interrupt
M ← (A)
B7
C7
D7
E7
F7
— 0 — — —
INH
8E
— —
5
3
3
6
5
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
—
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
M ← (X)
A ← (A) – (M)
Technical Data
62
—
DIR
EXT
IX2
IX1
IX
ff
Cycles
Description
Rotate Byte Right through Carry Bit
#opr
opr
opr
opr,X
opr,X
,X
DIR
INH
INH
IX1
IX
Effect on
CCR
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
SBC
SBC
SBC
SBC
SBC
SBC
Operand
Operation
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 5 of 6)
— —
— —
4
5
6
5
4
10
MC68HC705P9 — Rev. 4.0
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Central Processor Unit (CPU)
Opcode Map
Freescale Semiconductor, Inc...
TAX
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
WAIT
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
X ← (A)
(M) – $00
INH
97
— —
A ← (X)
—
— — — — —
Stop CPU Clock and Enable Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
— — — — —
—
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
—
— — —
Cycles
Description
Transfer Accumulator to Index Register
H I N Z C
Effect on
CCR
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 6 of 6)
2
dd
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
INH
9F
2
INH
8F
2
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
4.8 Opcode Map
See Table 4-7.
MC68HC705P9 — Rev. 4.0
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Technical Data
Central Processor Unit (CPU)
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
5
BSET0
DIR
5
BCLR0
2
DIR
5
BSET1
2
DIR
5
BCLR1
2
DIR
5
BSET2
2
DIR
5
BCLR2
2
DIR
5
BSET3
2
DIR
5
BCLR3
2
DIR
5
BSET4
2
DIR
5
BCLR4
2
DIR
5
BSET5
2
DIR
5
BCLR5
2
DIR
5
BSET6
2
DIR
5
BCLR6
2
DIR
5
BSET7
2
DIR
5
BCLR7
2
DIR
5
BRSET0
3
DIR
5
BRCLR0
3
DIR
5
BRSET1
3
DIR
5
BRCLR1
3
DIR
5
BRSET2
3
DIR
5
BRCLR2
3
DIR
5
BRSET3
3
DIR
5
BRCLR3
3
DIR
5
BRSET4
3
DIR
5
BRCLR4
3
DIR
5
BRSET5
3
DIR
5
BRCLR5
3
DIR
5
BRSET6
3
DIR
5
BRCLR6
3
DIR
5
BRSET7
3
DIR
5
BRCLR7
3
DIR
2
1
DIR
0
DIR
Bit Manipulation
3
DIR
6
7
IX
8
6
3
ROR
RORX
IX1
1
INH 2
6
3
ASR
ASRX
IX1
1
INH 2
6
3
ASLX/LSLX ASL/LSL
IX1
1
INH 2
6
3
ROL
ROLX
IX1
1
INH 2
6
3
DEC
DECX
IX1
1
INH 2
ASR
IX
5
5
IX
5
ASL/LSL
1
IX
5
ROL
1
IX
5
DEC
1
IX
1
1
ROR
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH
2
SEC
INH
2
CLI
INH
2
SEI
INH
2
RSP
INH
2
NOP
INH
LSB of Opcode in Hexadecimal
2
STOP
1
INH
2
2
5
6
3
3
TXA
WAIT
CLR
CLR
CLRX
CLRA
INH
INH 1
IX 1
IX1 1
INH 2
1
INH 1
5
6
3
3
INC
INC
INCX
INCA
IX
IX1 1
INH 2
INH 1
4
5
3
3
TST
TST
TSTX
TSTA
IX
IX1 1
INH 2
1
INH 1
1
3
RORA
1
INH
3
ASRA
1
INH
3
ASLA/LSLA
1
INH
3
ROLA
1
INH
3
DECA
1
INH
9
INH
Control
INH
9
RTI
INH
6
RTS
1
INH
5
6
3
3
NEG
NEG
NEGX
NEGA
IX 1
IX1 1
INH 2
INH 1
5
IX1
11
MUL
1
INH
10
5
6
3
3
SWI
COM
COM
COMX
COMA
INH
IX 1
IX1 1
INH 2
1
INH 1
5
6
3
3
LSR
LSR
LSRX
LSRA
IX
IX1 1
INH 2
1
INH 1
1
4
INH
Read-Modify-Write
INH
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
5
3
NEG
BRA
DIR
REL 2
3
BRN
2
REL
3
BHI
2
REL
5
3
COM
BLS
DIR
2
REL 2
5
3
LSR
BCC
DIR
2
REL 2
3
BCS/BLO
2
REL
5
3
ROR
BNE
DIR
2
REL 2
5
3
ASR
BEQ
DIR
2
REL 2
5
3
ASL/LSL
BHCC
DIR
2
REL 2
5
3
ROL
BHCS
DIR
2
REL 2
5
3
DEC
BPL
DIR
2
REL 2
3
BMI
2
REL
5
3
INC
BMC
DIR
2
REL 2
4
3
TST
BMS
DIR
2
REL 2
3
BIL
2
REL
5
3
CLR
BIH
DIR
2
REL 2
2
2
REL
Branch
Table 4-7. Opcode Map
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
MSB
0
LSB
0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
SUB
IX2
5
CMP
IX2
5
SBC
IX2
5
CPX
IX2
5
AND
IX2
5
BIT
IX2
5
LDA
IX2
6
STA
IX2
5
EOR
IX2
5
ADC
IX2
5
ORA
IX2
5
ADD
IX2
4
JMP
IX2
7
JSR
IX2
5
LDX
IX2
6
STX
IX2
D
IX2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT
4
AND
EXT
4
BIT
EXT
4
LDA
EXT
5
STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
6
JSR
EXT
4
LDX
EXT
5
STX
EXT
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
2
REL 2
2
LDX
2
IMM 2
2
2
EOR
IMM 2
2
ADC
2
IMM 2
2
ORA
2
IMM 2
2
ADD
2
IMM 2
2
2
2
2
2
2
2
2
A
IMM
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
MC68HC705P9 — Rev. 4.0
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Freescale Semiconductor, Inc.
Technical Data — MC68HC705P9
Section 5. Resets and Interrupts
5.1 Contents
Freescale Semiconductor, Inc...
5.2
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.2.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.3
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3
Low-Voltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.4.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.4.2
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.3.1
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.3.2
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .71
5.4.3.3
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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Resets and Interrupts
5.2 Resets
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A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. The following sources can
generate resets:
•
Power-on reset (POR) circuit
•
RESET pin
•
COP watchdog
VDD
POWER-ON RESET
COP WATCHDOG
(PROGRAMMABLE OPTION)
RESET
S
D
INTERNAL CLOCK
Q
RST
TO CPU AND
SUBSYSTEMS
CK
RESET
LATCH
Figure 5-1. Reset Sources
5.2.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset.
NOTE:
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at logic
zero at the end of 4064 tCYC, the MCU remains in the reset condition until
the signal on the RESET pin goes to logic one.
Technical Data
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Resets and Interrupts
Resets
VDD
(NOTE 1)
4064 tCYC
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFE
Freescale Semiconductor, Inc...
INTERNAL
DATA BUS
1FFE
1FFF
NEW
PCH
NEW
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 5-2. Power-On Reset Timing
5.2.2 External Reset
A logic zero applied to the RESET pin for one and one-half tCYC
generates an external reset. A Schmitt trigger senses the logic level at
the RESET pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
NEW
PCH
INTERNAL
DATA BUS
1FFF
NEW PC
NEW
PCL
NEW PC
DUMMY
OP
CODE
tRL
RESET
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 5-3. External Reset Timing
Table 5-1. External Reset Timing
Characteristic
RESET Pulse Width
Symbol
Min
Max
Unit
tRL
1.5
—
tCYC
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Resets and Interrupts
5.2.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic zero to bit 0 (COPC) of
the COP register at location $1FF0.
Freescale Semiconductor, Inc...
5.3 Low-Voltage Protection
A drop in power supply voltage below the minimum operating VDD
voltage is called a brownout condition. A brownout while the MCU is in a
non-reset state can corrupt MCU operation and necessitate a power-on
reset to resume operation.
The best protection against brownout is an undervoltage sensing circuit
that pulls the RESET pin low when it detects a low-power supply voltage.
The undervoltage sensing circuit may be made of discrete components
or an integrated circuit can be used.
For information about brownout and the COP watchdog, see Section 8.
Computer Operating Properly Watchdog (COP).
5.4 Interrupts
The following sources can generate interrupts:
•
SWI instruction
•
IRQ/VPP pin
•
Capture/compare timer
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a userdefined interrupt vector address.
Technical Data
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Resets and Interrupts
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Resets and Interrupts
Interrupts
5.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
5.4.2 External Interrupt
Freescale Semiconductor, Inc...
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/VPP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request. Figure 5-4 shows the IRQ/VPP pin interrupt logic.
LEVEL-SENSITIVE TRIGGER
(MOR OPTION)
(FROM CCR)
VDD
I
D
IRQ/VPP
Q
EXTERNAL
INTERRUPT
REQUEST
CK
CLR
RESET
VECTOR FETCH
Figure 5-4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ/VPP pin is a programmable
option. The IRQ/VPP pin can be negative-edge triggered or negativeedge- and low-level triggered. The level-sensitive triggering option
allows multiple external interrupt sources to be wire-ORed to the
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Resets and Interrupts
IRQ/VPP pin. An external interrupt request, shown in Figure 5-5, is
latched as long as any source is holding the IRQ/VPP pin low.
tILIL
tILIH
IRQ/VPP PIN
tILIH
IRQ1
.
.
.
Freescale Semiconductor, Inc...
IRQn
IRQ (INTERNAL)
Figure 5-5. External Interrupt Timing
Table 5-2. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(2)
—
tCYC
1. V DD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The minimum tILIL should not be less than the number of interrupt service routine cycles plus
19 tCYC.
Table 5-3. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(2)
—
tCYC
1. V DD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The minimum tILIL should not be less than the number of interrupt service routine cycles plus
19 tCYC.
Technical Data
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Resets and Interrupts
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Resets and Interrupts
Interrupts
5.4.3 Timer Interrupts
The capture/compare timer can generate the following interrupts:
•
Input capture interrupt
•
Output compare interrupt
•
Timer overflow interrupt
Freescale Semiconductor, Inc...
Setting the I bit in the condition code register disables timer interrupts.
5.4.3.1 Input Capture Interrupt
An input capture interrupt request occurs if the input capture flag, ICF,
becomes set while the input capture interrupt enable bit, ICIE, is also set.
ICF is in the timer status register, and ICIE is in the timer control register.
5.4.3.2 Output Compare Interrupt
An output compare interrupt request occurs if the output compare flag,
OCF, becomes set while the output compare interrupt enable bit, OCIE,
is also set. OCF is in the timer status register, and OCIE is in the timer
control register.
5.4.3.3 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF is in the timer status register, and TOIE is in the timer control
register.
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5.4.4 Interrupt Processing
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The CPU takes the following actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in
Figure 5-6
•
Sets the I bit in the condition code register to prevent further
interrupts
•
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $1FFC and $1FFD (software interrupt vector)
– $1FFA and $1FFB (external interrupt vector)
– $1FF8 and $1FF9 (timer interrupt vector)
The return from interrupt (RTI) instruction causes the CPU to recover the
CPU registers from the stack as shown in Figure 5-6.
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
UNSTACKING
ORDER
•
•
•
•
•
•
5
1
CONDITION CODE REGISTER
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 5-6. Interrupt Stacking Order
Technical Data
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Resets and Interrupts
Interrupts
Table 5-4. Reset/Interrupt Vector Addresses
Function
Source
Reset
Power-On
RESET Pin
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
None
None
None
None
1
1
1
$1FFE–$1FFF
Freescale Semiconductor, Inc...
COP Watchdog(1)
Software
Interrupt
(SWI)
User Code
None
None
External
Interrupt
IRQ/VPP Pin
None
I Bit
2
$1FFA–$1FFB
Timer
Interrupts
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
I Bit
3
$1FF8–$1FF9
Same Priority as
$1FFC–$1FFD
Instruction
1. The COP watchdog is programmable in the mask option register.
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Resets and Interrupts
FROM RESET
YES
I BIT SET?
NO
Freescale Semiconductor, Inc...
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
NO
TIMER
INTERRUPT?
YES
STACK PC, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
NO
YES
UNSTACK CCR, A, X, PC.
EXECUTE INSTRUCTION.
Figure 5-7. Interrupt Flowchart
Technical Data
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Technical Data — MC68HC705P9
Section 6. Low Power Modes
Freescale Semiconductor, Inc...
6.1 Contents
6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2 Stop Mode
The STOP instruction puts the MCU in its lowest power-consumption
mode and has the following effects on the MCU:
•
Stops the internal oscillator, the CPU clock, and the internal clock,
turning off the capture/compare timer, the COP watchdog, the
SIOP, and the ADC
•
Clears the I bit in the condition code register, enabling external
interrupts
•
Clears the ICIE, OCIE, and TOIE bits in the timer control register,
disabling further timer interrupts
The STOP instruction does not affect any other registers or any I/O lines.
The following events bring the MCU out of stop mode:
•
An external interrupt signal on the IRQ/VPP pin — A high-to-low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $1FFA and $1FFB. The timer resumes
counting from the last value before the STOP instruction.
•
External reset — A logic zero on the RESET pin resets the MCU
and loads the program counter with the contents of locations
$1FFE and $1FFF. The timer begins counting from $FFFC.
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When the MCU exits stop mode, processing resumes after a
stabilization delay of 4064 oscillator cycles.
An active edge on the PD7/TCAP pin during stop mode sets the ICF flag
when an external interrupt brings the MCU out of stop mode. An external
interrupt also latches the value in the timer registers into the input
capture registers.
Freescale Semiconductor, Inc...
If a reset brings the MCU out of stop mode, then an active edge on the
PD7/TCAP pin during stop mode has no effect on the ICF flag or the
input capture registers.
See Figure 6-1 for stop recovery timing information.
OSC
(NOTE 1)
tRL
RESET
IRQ/VPP
(NOTE 2)
tILIH
4064 tCYC
IRQ/VPP
(NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
(NOTE 4)
1FFE
1FFE
1FFE
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
Figure 6-1. Stop Recovery Timing
Technical Data
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Stop Mode
Figure 6-2 shows the sequence of events caused by the STOP
instruction.
STOP
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CLEAR I BIT IN CCR
CLEAR TIMER INTERRUPT FLAGS AND TIMER INTERRUPT ENABLE BITS
CLEAR TIMER PRESCALER
TURN OFF OSCILLATOR
NO
RESET?
YES
NO
EXTERNAL
INTERRUPT?
YES
TURN ON OSCILLATOR
DELAY 4064 CYCLES
TO STABILIZE
(1) LOAD PC WITH RESET VECTOR
OR
(2) SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-2. STOP Instruction Flowchart
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6.3 Wait Mode
The WAIT instruction puts the MCU in an intermediate powerconsumption mode and has the following effects on the MCU:
•
Clears the I bit in the condition code register, enabling interrupts
•
Stops the CPU clock, but allows the internal clock to drive the
capture/compare timer, the COP watchdog, and the ADC
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The WAIT instruction does not affect any other registers or any I/O lines.
The following conditions restart the CPU clock and bring the MCU out of
wait mode:
•
External interrupt — A high-to-low transition on the IRQ/VPP pin
loads the program counter with the contents of locations $1FFA
and $1FFB.
•
Timer interrupt — Input capture, output compare, and timer
overflow interrupt requests load the program counter with the
contents of locations $1FF8 and $1FF9.
•
COP watchdog reset — A timeout of the COP watchdog resets the
MCU and loads the program counter with the contents of locations
$1FFE and $1FFF. Software can enable timer interrupts so that
the MCU can periodically exit wait mode to reset the COP
watchdog.
•
External reset — A logic zero on the RESET pin resets the MCU
and loads the program counter with the contents of locations
$1FFE and $1FFF.
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Wait Mode
Figure 6-3 shows the sequence of events caused by the WAIT
instruction.
WAIT
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CLEAR I BIT IN CCR
STOP CPU CLOCK
NO
RESET?
YES
EXTERNAL
INTERRUPT?
NO
YES
TIMER
INTERRUPT?
NO
YES
OTHER ON-CHIP
INTERRUPT
SOURCES?
NO
RESTART CPU CLOCK
(1) FETCH RESET VECTOR
OR
(2) SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. VECTOR TO INTERRUPT SERVICE ROUTINE
Figure 6-3. WAIT Instruction Flowchart
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Figure 6-4 shows the effect of the STOP and WAIT instructions on the
CPU clock and the timer clock.
WAIT
STOP
OSC1
OSC2
INTERNAL
OSCILLATOR
÷2
INTERNAL CLOCK
÷2
CPU CLOCK
TIMER CLOCK
ADC CLOCK
Freescale Semiconductor, Inc...
Figure 6-4. STOP/WAIT Clock Logic
6.4 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU
register contents at VDD voltages as low as 2.0 Vdc. The data-retention
feature allows the MCU to remain in a low-power consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic zero.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic one.
Technical Data
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Technical Data — MC68HC705P9
Section 7. Parallel Input/Output (I/O) Ports
7.1 Contents
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7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.3.1
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . 83
7.3.2
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .83
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.4.1
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . 85
7.4.2
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .86
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.1
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . 88
7.5.2
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . .89
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.6.1
Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . 91
7.6.2
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . .92
7.2 Introduction
Twenty bidirectional pins and one input-only pin form four parallel
input/output (I/O) ports. All the bidirectional port pins are programmable
as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
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Parallel Input/Output (I/O) Ports
Addr.
$0000
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$0001
$0002
$0003
$0004
$0005
$0006
$0007
Name:
R/W
Read:
Port A Data Register
(PORTA) Write:
See page 83.
Reset:
Read:
Port B Data Register
(PORTB) Write:
See page 85.
Reset:
Read:
Port C Data Register
(PORTC) Write:
See page 88.
Reset:
Read:
Port D Data Register
(PORTD) Write:
See page 91.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
PC2
PC1
PC0
0
0
0
Unaffected by reset
0
PB7
PB6
Unaffected by reset
PC7
PC6
PC5
PC4
PC3
Unaffected by reset
0
PD7
1
0
PD5
Unaffected by reset
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 83.
Reset:
0
Read:
Data Direction Register B
DDRB7
(DDRB) Write:
See page 86.
Reset:
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
0
0
0
0
DDRB6
DDRB5
0
0
0
0
0
0
0
Read:
Data Direction Register C
DDRC7 DDRC6 DDRC5 DDRC4
(DDRC) Write:
See page 89.
Reset:
0
0
0
0
Read:
Data Direction Register D
(DDRD) Write:
See page 92.
Reset:
0
PB5
0
0
DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRD5
0
0
0
= Unimplemented
Figure 7-1. Parallel I/O Port Register Summary
Technical Data
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Parallel Input/Output (I/O) Ports
Port A
7.3 Port A
Port A is an 8-bit general-purpose I/O port.
7.3.1 Port A Data Register (PORTA)
The port A data register contains a latch for each of the eight port A pins.
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$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-2. Port A Data Register (PORTA)
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
7.3.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output.
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all eight port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
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NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 7-4 shows the I/O logic of port A.
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INTERNAL DATA BUS
READ DATA DIRECTION REGISTER A ($0004)
WRITE DATA DIRECTION REGISTER A ($0004)
RESET
WRITE PORT A DATA REGISTER ($0000)
DDRAx
PAx
PAx
READ PORT A DATA REGISTER ($0000)
Figure 7-4. Port A I/O Circuit
Writing a logic one to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic zero disables the output buffer.
When bit DDRAx is a logic one, reading address $0000 reads the PAx
data latch. When bit DDRAx is a logic zero, reading address $0000
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-1 summarizes the
operation of the port A pins.
Table 7-1. Port A Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
Technical Data
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Parallel Input/Output (I/O) Ports
Port B
7.4 Port B
Port B is a 3-bit I/O port that shares its pins with the serial I/O port
(SIOP).
NOTE:
Do not use port B for general-purpose I/O while the SIOP is enabled.
7.4.1 Port B Data Register (PORTB)
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The port B data register contains a latch for each of the three port B pins.
$0001
Bit 7
6
5
PB7
PB6
PB5
Read:
4
3
2
1
Bit 0
0
0
0
0
0
Write:
Reset:
Alternate
Function:
Unaffected by reset
SCK
SDI
SDO
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB[7:5] — Port B Data Bits
These read/write bits are software programmable bits. Data direction
of each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
NOTE:
Writing to data direction register B does not affect the data direction of
port B pins that are being used by the SIOP. However, data direction
register B always determines whether reading port B returns the states
of the latches or the states of the pins.
SCK — Serial Clock
When the SIOP is enabled, SCK is the SIOP clock output (in master
mode) or the SIOP clock input (in slave mode).
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SDI — Serial Data Input
When the SIOP is enabled, SDI is the SIOP data input.
SDO — Serial Data Output
When the SIOP is enabled, SDO is the SIOP data output.
7.4.2 Data Direction Register B (DDRB)
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Data direction register B determines whether each port B pin is an input
or an output.
NOTE:
Enabling and then disabling the SIOP configures data direction register
B for SIOP operation and can also change the port B data register. After
disabling the SIOP, initialize data direction register B and the port B data
register as your application requires.
$0005
Bit 7
6
5
DDRB7
DDRB6
DDRB5
0
0
0
Read:
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
DDRB[7:5] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:5], configuring all three port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-7 shows the I/O logic of port B.
Technical Data
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Port C
READ DATA DIRECTION REGISTER B ($0005)
INTERNAL DATA BUS
WRITE DATA DIRECTION REGISTER B ($0005)
RESET
WRITE PORT B DATA REGISTER ($0001)
DDRBx
PBx
PBx
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READ PORT B DATA REGISTER ($0001)
Figure 7-7. Port B I/O Logic
Writing a logic one to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic zero disables the output buffer.
When bit DDRBx is a logic one, reading address $0001 reads the PBx
data latch. When bit DDRBx is a logic zero, reading address $0001
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-2 summarizes the
operation of the port B pins.
Table 7-2. Port B Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
7.5 Port C
Port C is an 8-bit I/O port that shares five of its pins with the A/D
converter (ADC). The five shared pins are available for general-purpose
I/O functions when the ADC is disabled.
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7.5.1 Port C Data Register (PORTC)
The port C data register contains a latch for each of the eight port C pins.
$0002
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Read:
Write:
Reset:
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Alternate
Function:
Unaffected by reset
VRH
AN0
AN1
AN2
AN3
Figure 7-8. Port C Data Register (PORTC)
PC[7:0] — Port C Data Bits
These read/write bits are software programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
VRH — Voltage Reference High Bit
When the ADC is turned on, the PC7/VRH pin is the positive ADC
reference voltage.
AN[3:0] — Analog Input Bits
When the ADC is turned on, the AN0–AN3 pins are softwareselectable analog inputs. Unused analog inputs can be used as digital
inputs, but pins PC3/AN3, PC4/AN2, PC5/AN1, and PC6/AN0 cannot
be used as digital outputs while the ADC is on. Only pins PC0, PC1,
and PC2 can be used as digital outputs when the ADC is on.
The port C data register reads normally while the ADC is on, except
that the bit corresponding to the currently selected ADC input pin
reads as logic zero.
Writing to bits PC7–PC3 while the ADC is on can produce
unpredictable ADC results.
Technical Data
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Port C
7.5.2 Data Direction Register C (DDRC)
Data direction register C determines whether each port C pin is an input
or an output.
$0006
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 7-9. Data Direction Register C (DDRC)
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Writing to bits DDRC7–DDRC3 while the ADC is on can produce
unpredictable ADC results.
Figure 7-10 shows the I/O logic of port C.
READ DATA DIRECTION REGISTER C ($0006)
INTERNAL DATA BUS
WRITE DATA DIRECTION REGISTER C ($0006)
RESET
WRITE PORT C DATA REGISTER ($0002)
DDRCx
PCx
PCx
READ PORT C DATA REGISTER ($0002)
Figure 7-10. Port C I/O Logic
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Writing a logic one to a DDRC bit enables the output buffer for the
corresponding port C pin; a logic zero disables the output buffer.
When bit DDRCx is a logic one, reading address $0002 reads the PCx
data latch. When bit DDRCx is a logic zero, reading address $0002
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-3 summarizes the
operation of the port C pins.
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Table 7-3. Port C Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
7.6 Port D
Port D is a 2-bit port with one I/O pin and one input-only pin. Port D
shares the input-only pin, PD7/TCAP, with the capture/compare timer.
PD7/TCAP is the timer input capture pin. The PD7/TCAP pin can always
be a general-purpose input, even if input capture interrupts are enabled.
Technical Data
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Port D
7.6.1 Port D Data Register (PORTD)
The port D data register contains a latch for each of the two port D pins.
$0003
Bit 7
Read:
6
5
0
PD7
4
3
2
1
Bit 0
1
0
0
0
0
PD5
Write:
Reset:
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Alternate
Function:
Unaffected by reset
TCAP
= Unimplemented
Figure 7-11. Port D Data Register (PORTD)
PD7 and PD5 — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
TCAP — Timer Capture
TCAP is the input capture pin for the timer.
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7.6.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output.
$0007
Bit 7
6
Read:
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
DDRD5
Write:
Reset:
0
0
0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 7-12. Data Direction Register D (DDRD)
DDRD5 — Data Direction Register D Bit
This read/write bit controls the data direction of pin PD5. Reset clears
DDRD5, configuring PD5 as an input.
1 = PD5 configured as output
0 = PD5 configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 7-13 shows the I/O logic of port D.
READ DATA DIRECTION REGISTER D ($0007)
INTERNAL DATA BUS
WRITE DATA DIRECTION REGISTER D ($0007)
RESET
WRITE PORT D DATA REGISTER ($0003)
DDRDx
PDx
PDx
READ PORT D DATA REGISTER ($0003)
Figure 7-13. Port D I/O Logic
Technical Data
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Parallel Input/Output (I/O) Ports
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Parallel Input/Output (I/O) Ports
Port D
Writing a logic one to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic zero disables the output buffer.
When bit DDRDx is a logic one, reading address $0003 reads the PDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 7-4 summarizes the
operation of the port D pins.
Freescale Semiconductor, Inc...
Table 7-4. Port D Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Parallel Input/Output (I/O) Ports
Technical Data
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Technical Data — MC68HC705P9
Section 8. Computer Operating Properly Watchdog (COP)
Freescale Semiconductor, Inc...
8.1 Contents
8.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.1
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.4.2
COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . 96
8.4.3
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .97
8.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.6
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.7.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.2 Features
Features include:
•
Protection from runaway software
•
65.5-ms timeout period (with 2-MHz bus frequency)
•
Wait mode operation
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Computer Operating Properly Watchdog (COP)
8.3 Introduction
The purpose of the computer operating properly (COP) watchdog is to
reset the MCU in case of software failure. Software that is operating
properly periodically services the COP watchdog and prevents the reset
from occurring. The COP watchdog function is programmable in the
mask option register.
Freescale Semiconductor, Inc...
8.4 Operation
8.4.1 COP Watchdog Timeout
The COP watchdog is a 16-bit counter that generates a reset if allowed
to time out. Periodically clearing the counter starts a new timeout period
and prevents the COP from resetting the MCU. A COP watchdog
timeout indicates that the software is not executing instructions in the
correct sequence.
NOTE:
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog also depends on a power supply voltage at or above
a minimum specification and is not guaranteed to protect against
brownout. For information about brownout protection, see Section 5.
Resets and Interrupts.
8.4.2 COP Watchdog Timeout Period
Use the following formula to calculate the COP timeout period:
131 ,072 cycles
COP timeout period = --------------------------------------f BUS
where
crystal frequency
f BUS = --------------------------------------------2
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Computer Operating Properly Watchdog (COP)
Interrupts
8.4.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic zero
to bit 0 (COPC) of the COP register at location $1FF0.
Freescale Semiconductor, Inc...
If the main program executes within the COP timeout period, the clearing
routine needs to be executed only once. If the main program takes
longer than the COP timeout period, the clearing routine must be
executed more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
8.5 Interrupts
The COP watchdog does not generate interrupts.
8.6 COP Register
The COP register is a write-only register that returns the contents of
EPROM location $1FF0 when read.
$1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
COPC
Write:
Reset:
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 8-1. COP Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
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Computer Operating Properly Watchdog (COP)
8.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
8.7.1 Stop Mode
Freescale Semiconductor, Inc...
The STOP instruction clears the COP watchdog counter. Upon exit from
stop mode by external reset:
•
The counter begins counting from $0000.
•
The counter is cleared again after the 4064-cycle oscillator
stabilization delay.
Upon exit from stop mode by external interrupt:
•
The counter begins counting from $0000.
•
The counter is not cleared again after the oscillator stabilization
delay and has a count of 4064 when the program resumes.
8.7.2 Wait Mode
The COP watchdog continues to operate normally after a WAIT
instruction. Software should periodically take the MCU out of wait mode
and write to the COPC bit to prevent a COP watchdog timeout.
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Technical Data — MC68HC705P9
Section 9. Timer
Freescale Semiconductor, Inc...
9.1 Contents
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.4.1
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.1.1
PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.1.2
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
9.5
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.7
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.7.1
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.7.2
Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.7.3
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.7.4
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.7.5
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.7.6
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . 115
9.8
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.8.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
9.8.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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Timer
9.2 Features
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Features include:
•
Programmable polarity of input capture edge
•
Programmable polarity of output compare signal
•
Alternate counter registers
•
16-bit counter
•
Interrupt-driven operation with three maskable interrupt flags:
– Input capture
– Output compare
– Timer overflow
9.3 Introduction
The timer provides a timing reference for MCU operations. The input
capture and output compare functions provide a means to latch the
times at which external events occur, to measure input waveforms, and
to generate output waveforms and timing delays. Figure 9-1 shows the
structure of the timer module.
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Timer
Operation
EDGE
SELECT/
DETECT
LOGIC
TCAP
IEDG
ICRH
ICRL
TRH
TRL
ATRH
ATRL
Freescale Semiconductor, Inc...
INTERNAL
CLOCK
(XTAL ÷ 2)
÷4
16-BIT COUNTER
16-BIT COMPARATOR
OCRH
PIN
CONTROL
LOGIC
TCMP
OCRL
OLVL
INTERNAL
DATA BUS
TIMER OVERFLOW
OCIE
OCF
TOIE
TOF
TIMER
INTERRUPT
REQUEST
ICIE
ICF
Figure 9-1. Timer Block Diagram
9.4 Operation
The timing reference for the input capture and output compare functions
is a 16-bit free-running counter. The counter is preceded by a divide-byfour prescaler and rolls over every 218 cycles. Timer resolution with a 4MHz crystal is 2 µs. Software can read the value in the counter at any
time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
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Timer
Addr.
$0012
$0013
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$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
Name
R/W
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Read: Bit 15
Input Capture Register High
(ICRH) Write:
See page 114.
Reset:
14
13
12
11
10
9
Bit 8
Read:
Input Capture Register Low
(ICRL) Write:
See page 114.
Reset:
6
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
1
Bit 0
Read:
Timer Control Register
(TCR) Write:
See page 109.
Reset:
Read:
Timer Status Register
(TSR) Write:
See page 110.
Reset:
Bit 7
5
4
3
Unaffected by reset
Read:
Output Compare Register High
Bit 15
(OCRH) Write:
See page 115.
Reset:
Read:
Output Compare Register Low
(OCRL) Write:
See page 115.
Reset:
Unaffected by reset
Bit 7
14
13
12
11
Unaffected by reset
6
5
4
3
Unaffected by reset
Read: Bit 15
Timer Register High
(TRH) Write:
See page 112.
Reset:
14
Read:
Timer Register Low
(TRL) Write:
See page 112.
Reset:
6
Bit 7
13
12
11
Reset initializes TRH to $FF
5
4
3
Reset initializes TRL to $FC
Read: Bit 15
Alternate Timer Register High
(ATRH) Write:
See page 113.
14
Read:
Alternate Timer Register Low
(ATRL) Write:
See page 113.
6
Bit 7
13
12
11
Reset initializes ATRH to $FF
5
4
3
2
Reset initializes ATRL to $FC
= Unimplemented
U = Unaffected
Figure 9-2. Timer I/O Register Summary
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Timer
Operation
9.4.1 Pin Functions
The timer uses two pins.
9.4.1.1 PD7/TCAP
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PD7/TCAP is the input capture pin. When an active edge occurs on
PD7/TCAP, the timer transfers the current counter value to the input
capture registers. PD7/TCAP is also an I/O port pin.
9.4.1.2 TCMP
TCMP is the output-only output compare pin. When the counter value
matches the value written in the output compare registers, the timer
transfers the output level bit, OLVL, to the TCMP pin.
9.4.2 Input Capture
The input capture function is a means to record the time at which an
external event occurs. When the input capture circuitry detects an active
edge on the PD7/TCAP pin, it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the
PD7/TCAP pin. Latching the counter values at successive edges of
opposite polarity measures the pulse width of the signal. Figure 9-3
shows the logic of the input capture function.
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Timer
EDGE
SELECT/
DETECT
LOGIC
TCAP
IEDG
ICRH
ICRL
TRH
TRL
ICF
TIMER
INTERRUPT
REQUEST
Freescale Semiconductor, Inc...
ICIE
Figure 9-3. Input Capture Operation
9.4.3 Output Compare
The output compare function is a means of generating an output signal
when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and duty cycle on the TCMP pin.
Figure 9-4 shows the logic of the output compare function.
16-BIT COUNTER
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
OCRH ($0016)
TCMP
OCRL ($0017)
OLVL
OCF
OCIE
TIMER
INTERRUPT
REQUEST
Figure 9-4. Output Compare Operation
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Timer
Timing
9.5 Timing
Table 9-1. Timer Characteristics (VDD = 5.0 Vdc)(1)
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Characteristic
Symbol
Min
Max
Unit
Timer Resolution(2)
tRESL
4.0
—
tCYC
Input Capture Pulse Width
tH, tL
125
—
ns
Input Capture Pulse Period
tTLTL
—
tCYC
Note
(3)
1. V DD = 5.0 Vdc ± 10%, TA = TL to TH unless otherwise noted.
2. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC.
3. The minimum tTLTL should not be less than the number of interrupt service routine cycles plus
19 tCYC.
Table 9-2. Timer Characteristics (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Timer Resolution(2)
tRESL
4.0
—
tCYC
Input Capture Pulse Width
tH, tL
250
—
ns
Input Capture Pulse Period
tTLTL
—
tCYC
Note
(3)
1. V DD = 3.3 Vdc ± 10%, TA = TL to TH unless otherwise noted.
2. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC.
3. The minimum tTLTL should not be less than the number of interrupt service routine cycles plus
19 tCYC.
tTLTL
tTH
tTL
Figure 9-5. Input Capture Characteristics
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Timer
INTERNAL
BUS CLOCK
INTERNAL
RESET
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
 T00


 T01

TIMER 
CLOCKS 
 T10



 T11
16-BIT
COUNTER
$FFFC
$FFFE
$FFFD
$FFFF
RESET (EXTERNAL
OR END OF POR)
Figure 9-6. Timer Reset Timing
INTERNAL
BUS CLOCK

 T00


 T01

TIMER 
CLOCKS 
 T10


 T11

16-BIT
COUNTER $FFEB
$FFEC
$FFED
$FFEE
$FFEF
INPUT CAPTURE
EDGE
INPUT CAPTURE
LATCH
INPUT CAPTURE
REGISTER
PREVIOUSLY CAPTURED VALUE
$FFED
INPUT CAPTURE
FLAG
Note:
If the input capture edge occurs in the shaded area between T10 states, then the input capture
flag becomes set during the next T11 state.
Figure 9-7. Input Capture Timing
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Timer
Timing
INTERNAL
BUS CLOCK

 T00


 T01

TIMER 
CLOCKS 
 T10


 T11

Freescale Semiconductor, Inc...
16-BIT
COUNTER
OUTPUT COMPARE
REGISTERS
$FFEB
$FFEC
$FFED
$FFEF
$FFEE
$FFED
CPU WRITES $FFED
COMPARE
REGISTER LATCH
OUTPUT COMPARE
FLAG AND TCMP
NOTES:
1. A write to the output compare registers may occur at any time, but a compare only occurs at
timer state T01. Therefore, the compare may follow the write by up to four cycles.
2. The output compare flag is set at the timer state T11 that follows the comparison latch.
Figure 9-8. Output Compare Timing
INTERNAL
BUS CLOCK

 T00


 T01

TIMER 
CLOCKS 
 T10


 T11

16-BIT
COUNTER
$FFFF
$0000
$0001
$0002
OVERFLOW
FLAG (TOF)
Figure 9-9. Timer Overflow Timing
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9.6 Interrupts
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The following timer sources can generate interrupts:
•
Input capture flag (ICF) — The ICF bit is set when an edge of the
selected polarity occurs on the input capture pin. The input
capture interrupt enable bit, ICIE, enables ICF interrupt requests.
•
Output compare flag (OCF) — The OCF bit is set when the
counter value matches the value written in the output compare
registers. The output compare interrupt enable bit, OCIE, enables
OCF interrupt requests.
•
Timer overflow flag (TOF) — The TOF bit is set when the counter
value rolls over from $FFFF to $0000. The timer overflow enable
bit (TOIE) enables timer overflow interrupt requests.
Table 9-3 summarizes the timer interrupt sources.
Table 9-3. Timer Interrupt Sources
Source
Local Mask
Global
Mask
Priority
(1 = Highest)
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
I Bit
3
9.7 I/O Registers
The following registers control and monitor the operation of the timer:
•
Timer control register (TCR)
•
Timer status register (TSR)
•
Timer registers (TRH and TRL)
•
Alternate timer registers (ATRH and ATRL)
•
Input capture registers (ICRH and ICRL)
•
Output compare registers (OCRH and OCRL)
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Timer
I/O Registers
9.7.1 Timer Control Register
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The timer control register (TCR) performs the following functions:
•
Enables input capture interrupts
•
Enables output compare interrupts
•
Enables timer overflow interrupts
•
Controls the active edge polarity of the TCAP signal
•
Controls the active level of the TCMP output
$0012
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
Read:
Write:
Reset:
U = Unaffected
Figure 9-10. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the PD7/TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
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Bits 4–2 — Unused
These are read/write bits that always read as logic zeros.
Freescale Semiconductor, Inc...
IEDG — Input Edge
The state of this read/write bit determines whether a positive or
negative transition on the PD7/TCAP pin triggers a transfer of the
contents of the timer registers to the input capture registers. Reset
has no effect on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic one or a
logic zero appears on the TCMP pin when a successful output
compare occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
9.7.2 Timer Status Register
The timer status register (TSR) contains flags for the following events:
•
An active signal on the PD7/TCAP pin, transferring the contents of
the timer registers to the input capture registers
•
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
•
A timer rollover from $FFFF to $0000
$0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 9-11. Timer Status Register (TSR)
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I/O Registers
ICF — Input Capture Flag
The ICF bit is automatically set when an edge of the selected polarity
occurs on the PD7/TCAP pin. Clear the ICF bit by reading the timer
status register with ICF set, and then reading the low byte of the input
capture registers. Reset has no effect on ICF.
1 = Input capture
0 = No input capture
OCF — Output Compare Flag
Freescale Semiconductor, Inc...
The OCF bit is automatically set when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set, and then reading
the low byte of the output compare registers. Reset has no effect on
OCF.
1 = Output compare
0 = No output compare
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte of the timer
registers. Reset has no effect on TOF.
1 = Timer overflow
0 = No timer overflow
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9.7.3 Timer Registers
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The read-only timer registers (TRH and TRL) contain the current high
and low bytes of the 16-bit counter. Reading TRH before reading TRL
causes TRL to be latched until TRL is read. Reading TRL after reading
the timer status register clears the timer overflow flag (TOF). Writing to
the timer registers has no effect.
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Reset initializes TRH to $FF
$0019
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Reset initializes TRL to $FC
= Unimplemented
Figure 9-12. Timer Registers (TRH and TRL)
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer. The buffer value
remains fixed even if the high byte is read more than once. Reading TRL
reads the transparent low byte buffer and completes the read sequence
of the timer registers.
INTERNAL
DATA BUS
LATCH
READ TRH
BUFFER
TRH ($0018)
TRL ($0019)
Figure 9-13. Timer Register Reads
NOTE:
To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
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Timer
I/O Registers
9.7.4 Alternate Timer Registers
Freescale Semiconductor, Inc...
The read-only alternate timer registers (ATRH and ATRL) contain the
current high and low bytes of the 16-bit counter. Reading ATRH before
reading ATRL causes ATRL to be latched until ATRL is read. Reading
does not affect the timer overflow flag (TOF). Writing to the alternate
timer registers has no effect.
$001A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Reset initializes ATRH to $FF
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Reset initializes ATRL to $FC
= Unimplemented
Figure 9-14. Alternate Timer Registers (ATRH and ATRL)
Reading ATRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer.
INTERNAL
DATA BUS
LATCH
READ ATRH
ATRH ($001A)
BUFFER
ATRL ($001B)
Figure 9-15. Alternate Timer Register Reads
NOTE:
To prevent interrupts between readings of ATRH and ATRL, set the
interrupt mask (I bit) in the condition code register before reading ATRH,
and clear the mask after reading ATRL.
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9.7.5 Input Capture Registers
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When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits
further captures until ICRL is read. Reading ICRL after reading the timer
status register clears the input capture flag (ICF). Writing to the input
capture registers has no effect.
$0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Unaffected by reset
$0015
7
6
5
4
3
2
1
0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 9-16. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts between readings of ICRH and ICRL, set the
interrupt mask (I bit) in the condition code register before reading ICRH,
and clear the mask after reading ICRL.
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Timer
I/O Registers
9.7.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL), the planned TCMP pin
action takes place. Writing to OCRH before writing to OCRL inhibits
timer compares until OCRL is written. Reading or writing to OCRL after
reading the timer status register clears the output compare flag (OCF).
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Freescale Semiconductor, Inc...
Read:
Write:
Reset:
$0017
Unaffected by reset
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 9-17. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
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9.8 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
9.8.1 Stop Mode
Freescale Semiconductor, Inc...
The STOP instruction suspends the timer counter. Upon exit from stop
mode by external reset:
•
The timer counter resumes counting from $FFFC.
•
An input capture edge during stop mode does not affect the ICF
bit or the input capture registers.
Upon exit from stop mode by external interrupt:
•
The counter resumes counting from the suspended value.
•
An input capture edge during stop mode sets the ICF bit and
transfers the suspended timer counter value to the input capture
registers.
9.8.2 Wait Mode
The timer remains active after a WAIT instruction. Any enabled timer
interrupt request can bring the MCU out of wait mode.
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Technical Data — MC68HC705P9
Section 10. Serial Input/Output Port (SIOP)
Freescale Semiconductor, Inc...
10.1 Contents
10.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.4.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.4.1.1
PB7/SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.4.1.2
PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.4.1.3
PB6/SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.4.2 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.5
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10.7.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.7.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.8.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
10.8.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
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Serial Input/Output Port (SIOP)
10.2 Features
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Features include:
•
Master or slave operation
•
Programmable MSB-first or LSB-first operation
•
Interrupt-driven operation with transfer complete flag
•
Data collision flag
•
Master mode frequency = bus frequency ÷ 4
•
Maximum slave mode frequency = bus frequency ÷ 4
•
No minimum slave mode frequency
10.3 Introduction
The serial input/output port (SIOP) is a 3-wire master/slave
communication port with serial clock, data input, and data output
connections. The SIOP enables high-speed synchronous serial data
transfer between the MCU and peripheral devices. Shift registers used
with the SIOP can increase the number of parallel I/O pins controlled by
the MCU. More powerful peripherals such as analog-to-digital
converters and real-time clocks are also compatible with the SIOP.
Figure 10-1 shows the structure of the SIOP module.
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Serial Input/Output Port (SIOP)
Introduction
INTERNAL BUS
SIOP DATA REGISTER
7
6
5
4
3
2
1
PB5/SDO
0
SIOP
Freescale Semiconductor, Inc...
SIOP
CONTROL
PB6/SDI
SHIFT CLOCK
FROM MOR
SPIF/DCOL
PB7/SCK
PIN
CONTROL
LOGIC
AND
DDR
SPE
MSTR
M
S
SPIF
DCOL
INTERNAL
CLOCK
(fOSC ÷ 2)
DIVIDE
BY 4
CLOCK
LOGIC
Figure 10-1. SIOP Block Diagram
Addr.
$000A
$000B
$000C
Name
Read:
SIOP Control Register
(SCR) Write:
See page 125.
Reset:
Read:
SIOP Status Register
(SSR) Write:
See page 126.
Reset:
Read:
SIOP Data Register
(SDR) Write:
See page 127.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
SPE
0
MSTR
0
0
0
0
0
0
0
0
0
0
0
0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Unaffected by reset
= Unimplemented
Figure 10-2. SIOP I/O Register Summary
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Serial Input/Output Port (SIOP)
10.4 Operation
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The master MCU initiates and controls the transfer of data to and from
one or more slave peripheral devices. In master mode, a transmission is
initiated by writing to the SIOP data register (SDR). Data written to the
SDR is parallel-loaded and shifted out serially to the slave device(s).
Many simple slave devices are designed to only receive data from a
master or to only supply data to a master. For example, when a serialto-parallel shift register is used as an 8-bit port, the master MCU initiates
transfers of 8-bit data values to the shift register. Since the serial-toparallel shift register does not send any data to the master, the MCU
ignores whatever it receives as a result of the transmission.
The SIOP is simpler than the serial peripheral interface (SPI) on some
other Motorola MCUs in that:
•
The polarity of the serial clock is fixed.
•
There is no slave select pin.
•
The direction of serial data does not automatically switch as on the
SPI because the SIOP is not intended for use in multimaster
systems. Most applications use one MCU as the master to initiate
and control data transfer between one or more slave peripheral
devices.
A programmable option allows the SIOP to transfer data MSB first or
LSB first.
10.4.1 Pin Functions
The SIOP uses three pins and shares them with port B:
NOTE:
•
PB7/SCK
•
PB6/SDI
•
PB5/SDO
Do not use the PB7/SCK, PB6/SDI, or PB5/SDO pins for generalpurpose I/O while the SIOP is enabled.
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Serial Input/Output Port (SIOP)
Operation
When bit 6 (SPE) of the SIOP control register (SCR) is set, the SIOP is
enabled and the PB7/SCK, PB5/SDO, and PB6/SDI pins are dedicated
to SIOP functions. Clearing SPE disables the SIOP and the SIOP pins
become standard I/O port pins.
Freescale Semiconductor, Inc...
NOTE:
Enabling and then disabling the SIOP configures the data direction
register bits associated with the SIOP pins for SIOP operation and can
also change the associated port data register. After disabling the SIOP,
initialize the data direction register and the port data register as the
application requires.
10.4.1.1 PB7/SCK
The PB7/SCK pin synchronizes the movement of data into and out of the
MCU through the PB6/SDI and PB5/SDO pins. In master mode, the
PB7/SCK pin is an output. The serial clock frequency in master mode is
one-fourth the internal clock frequency.
In slave mode, the PB7/SCK pin is an input. The maximum serial clock
frequency in slave mode is one-fourth the internal clock rate. Slave
mode has no minimum serial clock frequency.
Figure 10-3 shows the timing relationships among the serial clock, data
input, and data output. The state of the serial clock between
transmissions is a logic one. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
SERIAL CLOCK
SAMPLE INPUT
DATA OUTPUT
(MSB-FIRST OPTION)
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
DATA OUTPUT
(LSB-FIRST OPTION)
LSB
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
MSB
Figure 10-3. SIOP Data/Clock Timing
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Serial Input/Output Port (SIOP)
The first falling edge on PB7/SCK begins a transmission. At this time the
first bit of received data is accepted at the PB6/SDI pin and the first bit
of transmitted data is presented at the PB5/SDO pin.
Freescale Semiconductor, Inc...
10.4.1.2 PB5/SDO
The PB5/SDO pin is the SIOP data output. Between transfers, the state
of the PB5/SDO pin reflects the value of the last bit shifted out on the
previous transmission, if there was one. To preset the beginning state,
write to the corresponding port data bit before enabling the SIOP. On the
first falling edge on the PB7/SCK pin, the first data bit to be shifted out
appears at the PB5/SDO pin.
After SPE is set, the PB5/SDO output driver can be disabled by writing
a zero to the corresponding data direction register bit of the port, thereby
configuring PB5/SDO as a high-impedance input.
10.4.1.3 PB6/SDI
The PB6/SDI pin is the SIOP data input. Valid SDI data must be present
for an SDI setup time, tS, before the rising edge of the serial clock and
must remain valid for an SDI hold time, tH, after the rising edge of the
serial clock. (See Table 10-1 and Table 10-2.)
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Serial Input/Output Port (SIOP)
Timing
10.4.2 Data Movement
Freescale Semiconductor, Inc...
Connecting the SIOP data register of a master MCU with the SIOP of a
slave MCU forms a 16-bit circular shift register. During an SIOP transfer,
the master shifts out the contents of its SIOP data register on its
PB5/SDO pin. At the same time, the slave MCU shifts out the contents
of its SIOP data register on its PB5/SDO pin. Figure 10-4 shows how the
master and slave exchange the contents of their data registers.
SIOP SHIFT REGISTER
SDO
SDO
SDI
SDI
SIOP SHIFT REGISTER
SIOP IN
SLAVE MODE
SIOP IN
MASTER MODE
SCK
SCK
Figure 10-4. Master/Slave SIOP Shift Register Operation
10.5 Timing
tSCK
tSCKL
SCK
tV
SDO
tHO
MSB
BIT 1
LSB
tH
tS
SDI
VALID
DATA
MSB
LSB
Figure 10-5. SIOP Timing
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Table 10-1. SIOP Timing (VDD = 5.0 Vdc)(1)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Master
Slave
fSIOP(M)
fSIOP(S)
fOSC/64
dc
fOSC/8
525
MHz
kHz
Cycle Time
Master
Slave
tSCK(M)
tSCK(S)
4.0
—
4.0
1920
tCYC(2)
ns
Clock (SCK) Low Time (fOP = 2.1 MHz) (3)(4)
tSCKL
932
—
ns
SDO Data Valid Time
tV
—
200
ns
SDO Hold Time
tHO
0
—
ns
SDI Setup Time
tS
100
—
ns
SDI Hold Time
tH
100
—
ns
1. V DD = 5.0 Vdc ±10%, V SS = 0 Vdc, TA = TL to TH unless otherwise noted.
2. tCYC = 1 ÷ fOP
3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 2.1 MHz maximum
4. In master mode, the frequency of SCK is fOP ÷ 4.
Table 10-2. SIOP Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Master
Slave
fSIOP (M)
fSIOP(S)
fOSC/64
dc
fOSC/8
250
MHz
kHz
Cycle Time
Master
Slave
tSCK(M)
tSCK(S)
4.0
—
4.0
4000
tCYC(2)
Clock (SCK) Low Time (fOP = 1.0 MHz) (3) (4)
tSCKL
1980
—
ns
SDO Data Valid Time
tV
—
400
ns
SDO Hold Time
tHO
0
—
ns
SDI Setup Time
tS
200
—
ns
SDI Hold Time
tH
200
—
ns
1. V DD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted
2. tCYC = 1 ÷ fOP
3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 1.0 MHz maximum
4. In master mode, the frequency of SCK is fOP ÷ 4.
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Serial Input/Output Port (SIOP)
Interrupts
10.6 Interrupts
The SIOP does not generate interrupt requests.
10.7 I/O Registers
Freescale Semiconductor, Inc...
The following registers control and monitor SIOP operation:
•
SIOP control register (SCR)
•
SIOP status register (SSR)
•
SIOP data register (SDR)
10.7.1 SIOP Control Register
The read/write SIOP control register (SCR) contains two bits. One bit
enables the SIOP, and the other configures the SIOP for master mode
or for slave mode.
$000A
Bit 7
6
5
4
3
2
1
Bit 0
0
SPE
0
MSTR
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 10-6. SIOP Control Register (SCR)
SPE — SIOP Enable
This read/write bit enables the SIOP. Setting SPE initializes the data
direction register as follows:
•
The PB6/SDI pin is an input.
•
The PB5/SDO pin is an output.
•
The PB7/SCK pin is an input in slave mode and an output in
master mode.
Clearing SPE disables the SIOP and returns the port to its normal I/O
functions. The data direction register and the port data register remain
in their SIOP-initialized state.
NOTE:
After clearing SPE, be sure to initialize the port for its intended I/O use.
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Serial Input/Output Port (SIOP)
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
1 = SIOP enabled
0 = SIOP disabled
Freescale Semiconductor, Inc...
MSTR — Master Mode Select
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
1 = Master mode selected
0 = Slave mode selected
10.7.2 SIOP Status Register
The read-only SIOP status register (SSR) contains two bits. One bit
indicates that a SIOP transfer is complete, and the other indicates that
an invalid access of the SIOP data register occurred while a transfer was
in progress.
$000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 10-7. SIOP Status Register (SSR)
SPIF — Serial Peripheral Interface Flag
This clearable, read-only bit is set automatically on the eighth rising
edge on the PB7/SCK pin and indicates that a data transmission took
place. SPIF does not inhibit further transmissions. Clear SPIF by
reading the SIOP status register while SPIF is set and then reading or
writing the SIOP data register. Reset clears SPIF.
1 = Transmission complete
0 = Transmission not complete
DCOL — Data Collision Flag
Technical Data
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Serial Input/Output Port (SIOP)
I/O Registers
Freescale Semiconductor, Inc...
This clearable, read-only bit is automatically set if the SIOP data
register is accessed while a data transfer is in progress. Reading or
writing the SIOP data register while a transmission is in progress
causes invalid data to be transmitted or read. Clear DCOL by reading
the SIOP status register with SPIF set and then accessing the SIOP
data register. Because the clearing sequence accesses the SIOP
data register, the sequence has to be completed before another
transmission starts or DCOL is set again.
To clear DCOL when SPIF is not set, turn off the SIOP by writing a
zero to SPE and then turn it back on by writing a one to SPE. Reset
clears DCOL.
1 = Invalid access of SDR
0 = Valid access of SDR
10.7.3 SIOP Data Register
The SIOP data register (SDR) is both the transmit data register and the
receive data register. To read or write the SIOP data register, the SPE
bit in the SIOP control register must be set.
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 10-8. SIOP Data Register (SDR)
With the SIOP configured for master mode, writing to the SIOP data
register initiates a serial transfer. This register is not buffered. Writing to
the SIOP data register overwrites the previous contents. Reading or
writing to the SIOP data register while a transmission is in progress can
cause invalid data to be transmitted or received.
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Serial Input/Output Port (SIOP)
10.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
Freescale Semiconductor, Inc...
10.8.1 Stop Mode
The STOP instruction suspends the clock to the SIOP. When the MCU
exits stop mode, processing resumes after the internal oscillator
stabilization delay of 4064 oscillator cycles.
A STOP instruction in a master SIOP does not suspend the clock to
slave SIOPs.
10.8.2 Wait Mode
The WAIT instruction suspends the clock to the SIOP. When the MCU
exits wait mode, processing resumes immediately.
A WAIT instruction in a master SIOP does not suspend the clock to slave
SIOPs.
Technical Data
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Section 11. Analog-to-Digital Converter (ADC)
Freescale Semiconductor, Inc...
11.1 Contents
11.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
11.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.4.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.4.1.1
PC7/VRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.4.1.2
PC6/AN0–PC3/AN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
11.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.6
Timing and Electrical Characteristics . . . . . . . . . . . . . . . . . . . 133
11.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
11.7.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . 134
11.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
11.8.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
11.8.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
11.2 Features
Features include:
•
8-bit conversions with ± 1.5-LSB precision
•
Four external and three internal analog input channels
•
Wait mode operation
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Analog-to-Digital Converter (ADC)
11.3 Introduction
The ADC consists of a single successive-approximation A/D converter,
an input multiplexer to select one of four external or two internal
channels, and control circuitry. Figure 11-1 shows the structure of the
ADC module.
AN3
COMPARATOR
AN2
INPUT
MULTIPLEXER
Freescale Semiconductor, Inc...
AN1
AN1
CH2
CH1
CH0
DIGITALTO-ANALOG
CONVERTER
VRH
VSS
ADON
INTERNAL DATA BUS
CCF
CONTROL
LOGIC
INTERNAL CLOCK
(XTAL ÷ 2)
ADRC
INTERNAL
RC
OSCILLATOR
Figure 11-1. ADC Block Diagram
Technical Data
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Analog-to-Digital Converter (ADC)
Operation
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADC Data Register
(ADDR) Write:
See page 136.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADC Status/Control Register
(ADSCR) Write:
See page 134.
Reset:
CCF
CH2
CH1
CH0
0
0
0
$001D
$001E
Unaffected by reset
0
ADRC
ADON
0
0
0
0
0
0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 11-2. ADC I/O Register Summary
11.4 Operation
The A/D conversion process is ratiometric, using two reference voltages,
VRH and VSS. Conversion accuracy is guaranteed only if VRH is equal to
VDD.
11.4.1 Pin Functions
The ADC uses five pins and shares them with port C:
•
PC7/VRH
•
PC6/AN0, PC5/AN1, PC4/AN2, and PC3/AN3
11.4.1.1 PC7/VRH
The voltage reference high pin (PC7/VRH) supplies the high reference
voltage for the ratiometric conversion process. For ratiometric
conversion, the supply voltage of the analog source should be the same
as VRH and be referenced to VSS.
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Analog-to-Digital Converter (ADC)
11.4.1.2 PC6/AN0–PC3/AN3
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The multiplexer can select one of four external analog input channels
(AN0, AN1, AN2, or AN3) for sampling. The conversion takes 32 cycles.
The first 12 cycles sample the voltage on the selected input pin by
charging an internal capacitor. In the last 20 cycles, a comparator
successively compares the output of an internal D/A converter to the
sampled analog input. Control logic changes the D/A converter input one
bit at a time, starting with the MSB, until the D/A converter output
matches the sampled analog input. The conversion is monotonic and
has no missing codes. At the end of the conversion, the conversion
complete flag (CCF) becomes set, and the CPU takes two cycles to
move the result to the ADC data register.
NOTE:
To prevent excess power dissipation, do not simultaneously use an I/O
port pin as a digital input and an analog input.
While the ADC is on, the selected analog input reads as logic zero. The
port C pins that are not selected read normally.
An analog input voltage equal to VRH converts to digital $FF; an input
voltage greater than VRH converts to $FF with no overflow. An analog
input voltage equal to VSS converts to digital $00. For ratiometric
conversion, the source of each analog input should use VRH as the
supply voltage and be referenced to VSS.
The clock frequency must be equal to or greater than 1 þMHz. If the
internal clock frequency is less than 1þMHz, the internal RC oscillator
(nominally 1.5 MHz) must be used for the ADC conversion clock. Make
this selection by setting the ADRC bit to logic one in the ADC status and
control register.
11.5 Interrupts
The ADC cannot generate interrupt requests.
Technical Data
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Analog-to-Digital Converter (ADC)
Timing and Electrical Characteristics
11.6 Timing and Electrical Characteristics
Table 11-1. ADC Characteristics (VDD = 5.0 Vdc)(1)
Freescale Semiconductor, Inc...
Characteristic
Min
Max
Unit
Resolution
8
8
Bit
Absolute Accuracy (4.0 > VRH > VDD)(2)
—
±1.5
LSB
Conversion Range (PC7/VRH)
VSS
VDD
V
Conversion Time (Includes Sampling Time)
External Clock
Internal RC Oscillator (ADRC = 1)
32
32
32
32
tAD(3)
µs
Monotonicity
Inherent (Within Total Error)
Zero Input Reading (VIN = 0 V)
00
01
Hex
Full-Scale Reading (VIN = VRH)
FF
FF
Hex
Sample Acquisition Time(4)
External Clock
Internal RC Oscillator (ADRC = 1)
12
—
12
12
tAD(5)
µs
—
12
pF
VSS
VRH
V
Input Leakage(6)
PC6/AN0, PC5/AN1, PC4/AN2, PC3/AN3
PC7/VRH
—
—
±1
±1
µA
ADC On Current Stabilization Time
—
100
µs
Input Capacitance
PC6/AN0, PC5/AN1, PC4/AN2, PC3/AN3
Analog Input Voltage
1. V DD = 5.0 Vdc ±10%, VSS = 0 Vdc
2. ADC accuracy may decrease proportionately as VRH is reduced below 4.0 V.
3. tAD = cycle time of the A/D converter
4. Source impedances more than 10 kΩ adversely affect internal RC charging time during input sampling.
5. tAD = tCYC (1 ÷ fOP) if MCU clock is clock source
6. External system error caused by input leakage approximately equals R source times input current.
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Analog-to-Digital Converter (ADC)
11.7 I/O Registers
The following registers control and monitor operation of the ADC:
•
ADC status and control register (ADSCR)
•
ADC data register (ADDR)
11.7.1 ADC Status and Control Register
Freescale Semiconductor, Inc...
The ADC status and control register (ADSCR) contains a conversion
complete flag and four writable control bits. Writing to ADSCR clears the
conversion complete flag and starts a new conversion sequence.
$001E
Bit 7
Read:
CCF
6
5
ADRC
ADON
0
0
4
3
0
0
2
1
Bit 0
CH2
CH1
CH0
0
0
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 11-3. ADC Status and Control Register (ADSCR)
CCF — Conversion Complete Flag
This read-only bit is automatically set when an analog-to-digital
conversion is complete, and a new result can be read from the ADC
data register. Clear the CCF bit by writing to the ADC status and
control register or by reading the ADC data register. Resets clear the
CCF bit.
1 = Conversion complete
0 = Conversion not complete
ADRC — ADC RC (Oscillator)
This read/write bit turns on the internal RC oscillator to drive the ADC.
If the internal clock frequency (fOP) is less than 1 MHz, ADRC must be
set. When the RC oscillator is turned on, it requires a time, tADRC, to
stabilize, and results can be inaccurate during this time. Resets clear
the ADRC bit.
1 = Internal RC oscillator drives ADC
0 = Internal clock drives ADC
Technical Data
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Analog-to-Digital Converter (ADC)
I/O Registers
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When the internal RC oscillator is being used as the ADC clock, two
limitations apply:
•
Because of the frequency tolerance of the RC oscillator and its
asynchronism with the internal clock, the conversion complete flag
must be used to determine when a conversion sequence is
complete.
•
The conversion process runs at the nominal 1.5-MHz rate, but the
conversion results must be transferred to the ADC data register
synchronously with the internal clock; therefore, the conversion
process is limited to a maximum of one channel every internal
clock cycle.
ADON — ADC On
This read/write bit turns on the ADC. When the ADC is on, it requires
a time, tADON, for the current sources to stabilize. During this time,
results can be inaccurate. Resets clear the ADON bit.
1 = ADC turned on
0 = ADC turned off
Bits 4–2 — Not used
Bits 4–2 always read as logic zeros.
CH[2:0] — Channel Select Bits
These read/write bits select one of eight ADC input channels as
shown in Table 11-2. Channels 0–3 are the input pins, PC3/AN3,
PC4/AN2, PC5/AN1, and PC6/AN0. Channels 4–6 can be used for
reference measurements. Channel 7 is reserved for factory testing.
Table 11-2. ADC Input Channel Selection
CH[2:1:0]
Channel
Signal
000
0
AN0
001
1
AN1
010
2
AN2
011
3
AN3
100
4
VRH
101
5
(VRH + VSS) / 2
110
6
VSS
111
7
Reserved
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Analog-to-Digital Converter (ADC)
To prevent excess power dissipation, do not use an ADC pin as an
analog input and a digital input at the same time.
Using one of the port pins as the ADC input does not affect the ability to
use the remaining port pins as digital inputs.
Freescale Semiconductor, Inc...
Reading a port pin that is selected as an analog input returns a logic
zero.
11.7.2 ADC Data Register
The ADC data register (ADDR) is a read-only register that contains the
result of the most recent analog-to-digital conversion.
$001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 11-4. ADC Data Register (ADDR)
11.8 Low-Power Modes
11.8.1 Stop Mode
The STOP instruction turns off the ADC and aborts any current and
pending conversions.
11.8.2 Wait Mode
The ADC continues to operate normally after the WAIT instruction. To
reduce power consumption in wait mode:
•
If the ADC is not being used, clear both the ADON and ADRC bits
before entering wait mode.
•
If the ADC is being used and the internal clock rate is above
1 MHz, clear the ADRC bit before entering wait mode.
Technical Data
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Section 12. Electrical Specifications
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12.1 Contents
12.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.3
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 139
12.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.5
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.6
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .141
12.7
3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142
12.8
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.9
Typical Supply Current vs. Internal Clock Frequency. . . . . . . 144
12.10 Maximum Supply Current vs. Internal Clock Frequency. . . . .145
12.11 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.12 3.3 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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Electrical Specifications
12.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
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The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
I
25
mA
Input Voltage
VIn
VSS – 0.3 to VDD + 0.3
V
EPROM Programming Voltage
VPP
16.75
V
Storage Temperature Range
TSTG
–65 to +150
°C
Supply Voltage
Current Drain per Pin
(Excluding VDD and VSS)
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 12.6 5.0-Volt DC Electrical Characteristics and
12.7 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
Technical Data
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Electrical Specifications
Operating Temperature Range
12.3 Operating Temperature Range
Package Type
Symbol
Value
Unit
TL to TH
MC68HC705P9P(1),
DW (2),
S(3)
(Standard)
Freescale Semiconductor, Inc...
MC68HC705P9C (4)P, CDW, CS (Extended)
MC68HC705P9V(5)P, VDW, VS (Automotive)
MC68HC705P9M(6)P, MDW, MS (Automotive)
TA
0 to 70
–40 to +85
–40 to +105
–40 to +125
°C
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. S = Ceramic dual in-line package (Cerdip)
4. C = Extended temperature range (–40 to +85°C)
5. V = Automotive temperature range (–40 to +105°C)
6. M = Automotive temperature range (–40 to +125°C)
12.4 Thermal Characteristics
Characteristic
Thermal Resistance
Plastic Dual In-Line Package (PDIP)
Small Outline Integrated Circuit (SOIC)
Ceramic Dual In-Line Package (Cerdip)
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Symbol
Value
Unit
θJA
60
60
60
°C/W
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Electrical Specifications
12.5 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)
(1)
Freescale Semiconductor, Inc...
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
TJ + 273°C
Solving equations (1) and (2) for K gives:
K = PD x (TA + 273°C) + θJA x (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Technical Data
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Electrical Specifications
5.0-Volt DC Electrical Characteristics
12.6 5.0-Volt DC Electrical Characteristics
Symbol
Min
Typ(1)
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output High Voltage (ILOAD = –0.8 mA)
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
TCMP
VOH
VDD – 0.8
—
—
V
Output Low Voltage (ILOAD = 1.6 mA)
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
TCMP
VOL
—
—
0.4
V
Input High Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ/VPP, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input Low Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
—
4.7
2.1
1.3
6.5
2.9
1.9
mA
mA
mA
—
—
—
2
—
—
30
50
100
µA
µA
µA
Characteristic
Freescale Semiconductor, Inc...
Output Voltage
ILOAD = 10.0 µA
ILOAD = –10.0 µA
Supply Current(2) (3) (4) (5)
Run Mode
Wait Mode (ADC On)
Wait Mode (ADC Off)
Stop Mode
25°C
0 to 70°C (Standard)
–40 to 125°C
IDD
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5
IIL
—
—
±10
µA
ADC Ports Hi-Z Leakage Current
IOZ
—
—
±1
µA
Input Current
RESET, IRQ/VPP, OSC1, PD7/TCAP
IIn
—
—
±1
µA
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ/VPP
COut
CIn
—
—
—
—
12
8
pF
Programming Voltage
VPP
16.25
16.5
16.75
V
Programming Current
IPP
—
5
10
mA
tEPGM
4
—
—
ms
Programming Time per Byte
1. Typical values at midpoint of voltage range, 25°C only
2. Run mode and wait mode IDD measured using external square wave clock source (fOSC = 4.2 MHz); all inputs 0.2 V from rail;
no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
3. Wait mode and stop mode IDD measured with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V
4. Stop mode IDD measured with OSC1 = VSS
5. Wait mode IDD affected linearly by OSC2 capacitance
MC68HC705P9 — Rev. 4.0
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Electrical Specifications
12.7 3.3-Volt DC Electrical Characteristics
Symbol
Min
Typ(1)
Max
Unit
Output Voltage (ILOAD ≤ 10.0 µA)
VOL
VOH
—
VDD –
0.1
—
—
0.1
—
V
Output High Voltage (ILOAD = –0.2 mA)
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
TCMP
VOH
VDD –
0.3
—
—
V
Output Low Voltage (ILOAD = 0.4 mA)
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
TCMP
VOL
—
—
0.3
V
Input High Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ/VPP, RESET, OSC1
VIH
0.7 ×
VDD
—
VDD
V
Input Low Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 ×
VDD
V
Data-Retention Mode Supply Voltage
VRM
2.0
—
—
V
—
—
—
1.6
0.9
0.4
2.3
1.3
0.6
mA
mA
mA
—
—
—
1.0
—
—
20
40
50
µA
µA
µA
Freescale Semiconductor, Inc...
Characteristic
Supply Current(2) (3) (4) (5)
Run Mode
Wait Mode (ADC On)
Wait Mode (ADC Off)
Stop Mode
25°C
0 to 70°C (Standard)
–40 to 125°C
IDD
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5
IIL
—
—
±10
µA
Input Current
RESET, IRQ/VPP, OSC1, PD7/TCAP
IIn
—
—
±1
µA
COut
CIn
—
—
—
—
12
8
pF
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ/VPP
1. Typical values at midpoint of voltage range, 25°C only
2. Run mode and wait mode IDD measured using external square wave clock source (fOSC = 2.1 MHz); all inputs 0.2 V from rail;
no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
3. Wait mode and stop mode IDD measured with all ports configured as inputs; VIL = 0.2 V; VIH = V DD – 0.2 V
4. Stop mode IDD measured with OSC1 = VSS
5. Wait mode IDD affected linearly by OSC2 capacitance
Technical Data
142
MC68HC705P9 — Rev. 4.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
Driver Characteristics
12.8 Driver Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.8
0.8
0.6
0.6
V DD – VOH (V)
0.7
0.5
0.4
0.3
0.5
0.4
(NOTE 3)
0.3
0.2
0.2
0.1
0.1
0
0
0
–1.0
–2.0
–3.0
–4.0
–5.0
0
–1.0
–2.0
IOH (mA)
–3.0
–4.0
–5.0
IOH (mA)
NOTES:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V vs. I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 800 mV @ IOL = –0.8 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = –0.2 mA.
Figure 12-1. Typical High-Side Driver Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.40
0.40
(NOTE 2)
0.35
0.35
0.30
0.30
0.25
0.25
VOL (V)
VOL (V)
Freescale Semiconductor, Inc...
V DD – VOH (V)
(NOTE 2)
0.7
0.20
0.15
0.20
0.15
0.10
0.10
0.05
0.05
0
(NOTE 3)
0
0
2.0
4.0
6.0
8.0
10.0
0
2.0
4.0
6.0
8.0
10.0
IOL (mA)
IOL (mA)
NOTES:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V vs. I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
Figure 12-2. Typical Low-Side Driver Characteristics
MC68HC705P9 — Rev. 4.0
MOTOROLA
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Electrical Specifications
12.9 Typical Supply Current vs. Internal Clock Frequency
5.0
RUN MODE
25 °C
5.5 V
4.0
Freescale Semiconductor, Inc...
SUPPLY CURRENT (mA)
4.5 V
3.6 V
3.0
3.0 V
2.0
1.0
0
0.5
0
1.0
2.0
1.5
INTERNAL CLOCK FREQUENCY (MHz)
2.0
1.2
1.0
WAIT MODE
25 °C
ADC OFF
5.5 V
0.8
4.5 V
1.0
RUN MODE
25 °C
ADC ON
5.5 V
0.5
4.5 V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.5
3.6 V
3.6 V
3.0 V
0.6
0.4
0.2
3.0 V
0
0
0
0.5
1.0
1.5
INTERNAL CLOCK FREQUENCY (MHz)
2.0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 12-3. Typical Supply Current vs. Internal Clock Frequency
Technical Data
144
MC68HC705P9 — Rev. 4.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
Maximum Supply Current vs. Internal Clock Frequency
12.10 Maximum Supply Current vs. Internal Clock Frequency
7.0
2.5
VDD = 5 V ±10%
–40 to +125 °C
6.0
Run Mode
Run Mode
2.0
Wait Mode (ADC On)
Wait Mode (ADC Off)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
Wait Mode (ADC On)
Wait Mode (ADC Off)
5.0
Freescale Semiconductor, Inc...
VDD = 3.3 V ±10%
–40 to +125 °C
4.0
3.0
2.0
1.5
1.0
0.5
1.0
0
0
0
0.5
1.0
1.5
INTERNAL CLOCK FREQUENCY (MHz)
2.0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 12-4. Maximum Supply Current vs. Internal Clock Frequency
MC68HC705P9 — Rev. 4.0
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Electrical Specifications
12.11 5.0-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fOSC
—
dc
4.2
4.2
MHz
Internal Operating Frequency (fOSC ÷ 2)
Crystal
External Clock
fOP
—
dc
2.1
2.1
MHz
Cycle Time (1 ÷ fOP)
tCYC
480
—
ns
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tILCH
—
100
ms
tRL
1.5
—
tCYC
tRESL
t H, t L
tTLTL
4.0
125
Note(2)
—
—
—
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(3)
—
tCYC
tOH, tOL
90
—
ns
RC Oscillator Stabilization Time
tRCON
—
5
µs
ADC On Current Stabilization Time
tADON
—
100
µs
RESET Pulse Width
Timer
Resolution (1)
Input Capture Pulse Width
Input Capture Pulse Period
OSC1 Pulse Width
ns
tCYC
1. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC
2. The minimum tTLTL should not be less than the number of interrupt service routine cycles plus
19 tCYC
3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus
19 tCYC
Technical Data
146
MC68HC705P9 — Rev. 4.0
Electrical Specifications
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Electrical Specifications
3.3 V Control Timing
12.12 3.3 V Control Timing
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fOSC
—
dc
2.0
2.0
MHz
Internal Operating Frequency (fOSC ÷ 2)
Crystal
External Clock
fOP
—
dc
1.0
1.0
MHz
Cycle Time (1 ÷ fOP)
tCYC
1
—
ms
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tILCH
—
100
ms
tRL
1.5
—
tCYC
tRESL
t H, t L
tTLTL
4.0
250
Note(2)
—
—
—
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(3)
—
tCYC
tOH, tOL
200
—
ns
RESET Pulse Width
Timer
Resolution (1)
Input Capture Pulse Width
Input Capture Pulse Period
OSC1 Pulse Width
ns
tCYC
1. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC
2. The minimum tTLTL should not be less than the number of interrupt service routine cycles plus
19 tCYC
3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus
19 tCYC
VDD
PINS
R2
R1
R2
C
3.26 kΩ
2.38 kΩ¾
50 pF
PA7–PA0
TEST POINT
PB7/SCK–PB5/SDO
C
R1
PC7/VRH–PC0
Figure 12-5. Test Load
MC68HC705P9 — Rev. 4.0
MOTOROLA
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Electrical Specifications
Technical Data
148
MC68HC705P9 — Rev. 4.0
Electrical Specifications
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Advance Information — MC68HC705P9
Section 13. Mechanical Specifications
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.3
28-Pin PDIP — Case #710 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.4
28-Pin Cerdip — Case #733. . . . . . . . . . . . . . . . . . . . . . . . . . 150
13.5
28-Pin SOIC — Case #751F . . . . . . . . . . . . . . . . . . . . . . . . . 150
13.2 Introduction
The MC68HC705P9 is available in the following packages:
•
Case 710 — Plastic dual in-line package (PDIP)
•
Case 733 — Ceramic dual in-line package (Cerdip)
•
Case 751F — Small outline integrated circuit (SOIC)
13.3 28-Pin PDIP — Case #710
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
15
B
1
14
A
L
C
N
H
G
F
D
K
SEATING
PLANE
M
J
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MC68HC705P9 — Rev. 4.0
MOTOROLA
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
5.08
3.94
0.56
0.36
1.52
1.02
2.54 BSC
2.16
1.65
0.38
0.20
3.43
2.92
15.24 BSC
15°
0°
1.02
0.51
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
15°
0°
0.020 0.040
Technical Data
Mechanical Specifications
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Mechanical Specifications
13.4 28-Pin Cerdip — Case #733
28
NOTES:
1. DIMENSIONS A AND B INCLUDES MENISCUS.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4. CONTROLLING DIMENSION: INCH.
15
B
1
14
-A-
DIM
A
B
C
D
F
G
J
K
L
M
N
L
C
Freescale Semiconductor, Inc...
N
-TSEATING
PLANE
K
G
H
J
M
F
D
28 PL
M T
0.25 (0.010)
INCHES
MIN
MAX
1.435
1.490
0.500
0.605
0.160
0.230
0.015
0.022
0.050
0.065
0.100 BSC
0.008
0.012
0.125
0.160
0.600 BSC
0°
15°
0.020
0.050
MILLIMETERS
MIN
MAX
36.45
37.84
12.70
15.36
4.06
5.84
0.38
0.55
1.27
1.65
2.54 BSC
0.20
0.30
3.18
4.06
15.24 BSC
0°
15°
0.51
1.27
A M
13.5 28-Pin SOIC — Case #751F
-A28
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
14X
-B1
P
0.010 (0.25)
M
B
M
14
28X D
0.010 (0.25)
M
T
A
S
B
M
S
R X 45°
C
-T26X
-T-
G
K
SEATING
PLANE
F
J
Technical Data
150
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
17.80 18.05
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8°
0°
10.05 10.55
0.75
0.25
INCHES
MIN
MAX
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
8°
0°
0.395 0.415
0.010 0.029
MC68HC705P9 — Rev. 4.0
Mechanical Specifications
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Technical Data — MC68HC705P9
Section 14. Ordering Information
Freescale Semiconductor, Inc...
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
14.2 Introduction
This section contains ordering numbers for the MC68HC705P9.
14.3 MC Order Numbers
Table 14-1. Order Numbers
Package
Type
Plastic DIP(1)
SOIC
(2)
CERDIP(3)
Case
Outline
710
733
751F
Pin
Count
Operating
Temperature
28
0 to +70°C
–40 to +85°C
–40 to +105°C
–40 to +125°C
MC68HC705P9P
MC68HC705P9CP
MC68HC705P9VP
MC68HC705P9MP
28
0 to +70°C
–40 to +85°C
–40 to +105°C
–40 to +125°C
MC68HC705P9DW
MC68HC705P9CDW
MC68HC705P9VDW
MC68HC705P9MDW
28
0 to +70°C
–40 to +85°C
–40 to +105°C
–40 to +125°C
MC68HC705P9S
MC68HC705P9CS
MC68HC705P9VS
MC68HC705P9MS
Order Number
1. DIP = dual in-line package
2. SOIC = small outline integrated circuit
3. CERDIP = ceramic DIP
MC68HC705P9 — Rev. 4.0
MOTOROLA
Technical Data
Ordering Information
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Ordering Information
Technical Data
152
MC68HC705P9 — Rev. 4.0
Ordering Information
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Technical Data — MC68HC705P9
Freescale Semiconductor, Inc...
Index
A
accumulator (A) . . . . . . . . . . . . . . .49–50, 53
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
ADC (analog-to-digital converter)
block diagram . . . . . . . . . . . . . . . . . . .130
features . . . . . . . . . . . . . . . . . . . . . . . .129
I/O register summary . . . . . . . . . . . . .131
I/O registers . . . . . . . . . . . . . . . . . . . .134
low-power modes . . . . . . . . . . . . . . . .136
ADC data register (ADDR) . . . .132, 134–136
ADC status and control
register (ADSCR) . . . . . . . . . .132, 134
addressing modes . . . . . . . . . . . . . . . . . . .50
ADON bit . . . . . . . . . . . . . . . . . . . . .135–136
ADRC bit . . . . . . . . . . . . . . . . .132, 134, 136
alternate timer registers (ATRH/L) . . . . . .113
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
AN[3:0] bits . . . . . . . . . . . . . . . . . . . . . . . . .88
arithmetic/logic unit (ALU) . . . . . . . . . . . . .45
B
bootloader ROM . . . . . . . . . . . . . . . . . . . . .37
bootload procedure . . . . . . . . . . . . . . . .41
bootloader circuit . . . . . . . . . . . . . . . . . .40
location . . . . . . . . . . . . . . . . . . . . . . . . .39
brownout . . . . . . . . . . . . . . . . . . . . . . . .68, 96
bypass capacitors . . . . . . . . . . . . . . . . . . . .26
MOTOROLA
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
case outlines . . . . . . . . . . . . . . . . . . 149–151
CCF bit . . . . . . . . . . . . . . . . . . . . . . . 132, 134
ceramic resonator circuit . . . . . . . . . . . . . . 28
CH[2:0] bits . . . . . . . . . . . . . . . . . . . . . . .135
condition code register
(CCR) . . .45, 55, 69, 71–72, 112–115
COP register (COPR) . . . . . . . . . . . . . 68, 97
COP watchdog
COP in stop mode . . . . . . . . . . . . . . . . 98
COP in wait mode . . . . . . . . . . . . . . . . .98
COP register (COPR) . . . . . . . . . . . . . . 97
enabling and disabling . . . . . . . . . . . . . 42
features . . . . . . . . . . . . . . . . . . . . . . . . . 95
operation . . . . . . . . . . . . . . . . . . . . . . . .96
timeout period . . . . . . . . . . . . . . . . . . . .96
COP watchdog reset . . . . . . . . . . . 68, 96–97
COPC bit . . . . . . . . . . . . . . . . . . . . 68, 97–98
COPE bit . . . . . . . . . . . . . . . . . . . . . . . . . .42
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
block diagram . . . . . . . . . . . . . . . . . . . .45
control unit . . . . . . . . . . . . . . . . . . . . . . 44
features . . . . . . . . . . . . . . . . . . . . . . . . . 44
instruction set summary . . . . . . . . . . . .58
instruction types . . . . . . . . . . . . . . . . . .52
instructions set . . . . . . . . . . . . . . . . . . .49
opcode map . . . . . . . . . . . . . . . . . . . . . 64
registers . . . . . . . . . . . . . . . . . . . . . . . .45
Index
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Index
CPU registers . . . . . . . . . . .36, 50, 53, 57, 72
accumulator (A) . . . . . . . . . . . . .49–50, 53
condition code register
(CCR) .45, 55, 69, 71–72, 112–115
index register (X) . . . . . . . . . . . . . . .49–53
program counter (PC) . . . . .52, 55, 66, 72
stack pointer (SP) . . . . . . . . . . . . . . . . .36
crystal
AT-cut . . . . . . . . . . . . . . . . . . . . . . . . . .27
strip . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
tuning fork . . . . . . . . . . . . . . . . . . . . . . .27
crystal oscillator circuit . . . . . . . . . . . . . . . .27
D
data direction registers . . . . . . .121–122, 125
data direction register A (DDRA) . .29, 83
data direction register B (DDRB) . .29, 86
data direction register C (DDRC) . .29, 89
data direction register D (DDRD) . .29, 92
data-retention mode . . . . . . . . . . . . . . . . . .80
DCOL bit . . . . . . . . . . . . . . . . . . . . . . . . . .126
DDRA[7:0] bits . . . . . . . . . . . . . . . . . . . . . .83
DDRB[7:5] bits . . . . . . . . . . . . . . . . . . . . . .86
DDRC[7:0] bits . . . . . . . . . . . . . . . . . . . . . .89
DDRD5 bit . . . . . . . . . . . . . . . . . . . . . . . . .92
E
electrical specifications
control timing . . . . . . . . . . . . . . . .146–147
current versus internal clock
frequency . . . . . . . . . . . . .144–145
DC electrical characteristics . . . .141–142
driver characteristics . . . . . . . . . . . . . .143
maximum ratings . . . . . . . . . . . . . . . . .138
power considerations . . . . . . . . . . . . .140
electrostatic damage . . . . . . . . . . . . . . . . .81
EPGM bit . . . . . . . . . . . . . . . . . . . . . . . . . .38
EPROM erasure . . . . . . . . . . . . . . . . . .37, 41
EPROM programming register (EPROG) . .38
154
EPROM/OTPROM
bootloader circuit . . . . . . . . . . . . . . . . . 40
EPROM erasing . . . . . . . . . . . . . . . . . . 41
locations . . . . . . . . . . . . . . . . . . . . . . . .37
programming . . . . . . . . . . . . . . . . . . . . 37
external interrupt . . . . . . . 29, 69–70, 98, 116
external interrupt vector . . . . . . . . . . . . . . .72
external reset . . . . . . . . . . . . . . . . 67, 98, 116
F
features . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I
I bit . . . . . . . . . . . . . . . . . 69, 71–72, 112–115
I/O bits
ADON bit . . . . . . . . . . . . . . . . . . 135–136
ADRC bit . . . . . . . . . . . . . . .132, 134, 136
AN[3:0] bits . . . . . . . . . . . . . . . . . . . . . .88
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CCF bit . . . . . . . . . . . . . . . . . . . . 132, 134
CH[2:0] bits . . . . . . . . . . . . . . . . . . . . .135
COPC bit . . . . . . . . . . . . . . . . .68, 97–98
COPE bit . . . . . . . . . . . . . . . . . . . . . . . .42
DCOL bit . . . . . . . . . . . . . . . . . . . . . . .126
DDRA[7:0] bits . . . . . . . . . . . . . . . . . . .83
DDRB[7:5] bits . . . . . . . . . . . . . . . . . . .86
DDRC[7:0] bits . . . . . . . . . . . . . . . . . . .89
DDRD5 bit . . . . . . . . . . . . . . . . . . . . . .92
EPGM bit . . . . . . . . . . . . . . . . . . . . . . .38
I bit . . . . . . . . . . . . . . 69, 71–72, 112–115
ICF bit . . . . . . . . . .71, 108, 111, 114, 116
ICIE bit . . . . . . . . . . . . . . . . .71, 108–109
IEDG bit . . . . . . . . . . . . . . . . . . . . . . .110
IRQ bit . . . . . . . . . . . . . . . . . . . . . . . . .42
LATCH bit . . . . . . . . . . . . . . . . . . . . . . .38
MSTR bit . . . . . . . . . . . . . . . . . . . . . . .126
OCF bit . . . . . . . . . . . . . 71, 108, 111, 115
OCIE bit . . . . . . . . . . . . . . . .71, 108–109
OLVL bit . . . . . . . . . . . . . . . . . . . 104, 110
PA[7:0] bits . . . . . . . . . . . . . . . . . . . . . .83
PB[7:5] bits . . . . . . . . . . . . . . . . . . . . . .85
Index
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Index
PC[7:0] bits . . . . . . . . . . . . . . . . . . . . . .88
PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . .91
PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . .91
SIOP bit . . . . . . . . . . . . . . . . . . . . . . . . .42
SPE bit . . . . . . . . . . . .121–122, 125, 127
SPIF bit . . . . . . . . . . . . . . . . . . . . . . . .126
TOF bit . . . . . . . . . . . . .71, 108, 111–113
TOIE bit . . . . . . . . . . . . . . . . .71, 108–109
I/O pins
IRQ/VPP pin . . . . . .22, 29, 38–39, 42, 69
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . .27
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . .27
PB5/SDO pin . . . . . . . . .86, 120–122, 125
PB6/SDI pin . . . . . . . . .86, 120–122, 125
PB7/SCK pin . . . . . . . . .85, 120–122, 125
PC3/AN0 pin . . . . . . . . . . . . . . . . . . . .135
PC3/AN3 pin . . . . . . . . . . . . . . . . .88, 131
PC4/AN2 pin . . . . . . . . . . . . .88, 131, 135
PC5/AN1 pin . . . . . . . . . . . . .88, 131, 135
PC6/AN0 pin . . . . . . . . . . . . .88, 131, 135
PC7/VRH pin . . . . . . . . . . . . . . . . .88, 131
PD7/TCAP pin . . . . .39, 90, 103, 110–111
RESET pin . . . . . . . . . . . . .28, 39, 66–68
TCMP pin . . . . . . .29, 103–104, 110, 115
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . .26
I/O port pin termination . . . . . . . . . . . . . . . .81
I/O registers
ADC data register (ADDR) .132, 134–136
ADC status and control
register (ADSCR) . . . . . . .132, 134
alternate timer registers (ATRH/L) . . .113
COP register (COPR) . . . . . . . . . . .68, 97
data direction register A (DDRA) . . . . .83
data direction register B (DDRB) . . . . .86
data direction register C (DDRC) . . . . .89
data direction register D (DDRD) . . . . .92
EPROM programming
register (EPROG) . . . . . . . . . . . .38
input capture registers (ICRH/ICRL) . .103
input capture registers
(ICRH/L) . . . . . .110–111, 114, 116
mask option register
(MOR) . . . . . . . . . . .22, 37, 42, 96
MOTOROLA
output compare registers
(OCRH/L) . . . . . . . . .110–111, 115
output compare registers
(OCRH/OCRL) . . . . . . . . . . . . .104
port A data register (PORTA) . . . . . . . .83
port B data register (PORTB) . . . . . . . .85
port C data register (PORTC) . . . . . . . . 88
port D data register (PORTD) . . . . . . . . 91
SIOP control register
(SCR) . . . . . . . . . . . . . . . . . 121, 125, 127
SIOP data register (SDR) . . . . . . 126–127
SIOP status register (SSR) . . . . . . . . .126
timer control register (TCR) . . . . . 71, 109
timer registers (TRH/L) . . . . . . . . 110–112
timer status register
(TSR) . . . . . . . . . 71, 110, 114–115
ICF bit . . . . . . . . . . . . 71, 108, 111, 114, 116
ICIE bit . . . . . . . . . . . . . . . . . . . .71, 108–109
IEDG bit . . . . . . . . . . . . . . . . . . . . . . . . . . 110
index register (X) . . . . . . . . . . . . . . . . . 49–53
input capture interrupt . . . . . . . . . . . . . . . 100
input capture registers
(ICRH/L) . . . .103, 110–111, 114, 116
instruction set . . . . . . . . . . . . . . . . . . . . . . .49
addressing modes . . . . . . . . . . . . . . . . 50
instruction set summary . . . . . . . . . . . .58
instruction types . . . . . . . . . . . . . . . . . .52
opcode map . . . . . . . . . . . . . . . . . . . . . 64
internal clock . . . . . . . . . . . . . . . . . . . . . . .96
frequency . . . . . . . . . . . . . . . . . . . . . . . 27
internal RC oscillator . . . . . . . .132, 134–135
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 108
interrupts
external interrupt . . . . . . . . . . . . . . . . . . 69
external interrupt logic . . . . . . . . . . . . .69
external interrupt timing . . . . . . . . . . . .70
interrupt flowchart . . . . . . . . . . . . . . . . . 74
interrupt processing . . . . . . . . . . . . . . . 72
interrupt sources . . . . . . . . . . . . . . . . . . 68
interrupt stacking order . . . . . . . . . . . . .72
reset/interrupt vector addresses . . . . . .73
Index
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155
Freescale Semiconductor, Inc.
Index
software interrupt . . . . . . . . . . . . . . . . .69
timer interrupts . . . . . . . . . . . . . . . . . . .71
IRQ bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . .69
IRQ/VPP pin . . . . . . . . .22, 29, 38–39, 42, 69
Freescale Semiconductor, Inc...
J
junction temperature . . . . . . . . . . . . . . . . .140
L
LATCH bit . . . . . . . . . . . . . . . . . . . . . . . . . .38
low voltage protection . . . . . . . . . . . . . . . . .68
low-power modes
ADC in stop and wait modes . . . . . . . .136
COP in stop and wait modes . . . . . . . .98
data-retention mode . . . . . . . . . . . . . . .80
SIOP in stop and wait modes . . . . . . .128
STOP instruction flowchart . . . . . . . . . .77
stop mode . . . . . . . . . . . . . . . . . . . . . . .75
stop recovery timing . . . . . . . . . . . . . . .76
STOP/WAIT clock logic . . . . . . . . . . . . .80
timer in stop and wait modes . . . . . . .116
WAIT instruction flowchart . . . . . . . . . .79
wait mode . . . . . . . . . . . . . . . . . . . . . . .78
M
mask option register (MOR) . . .22, 37, 42, 96
mechanical specifications
packages . . . . . . . . . . . . . . . . . . . . . . .148
memory
EPROM/OTPROM . . . . . . . . . . . . . . . .37
features . . . . . . . . . . . . . . . . . . . . . . . . .31
parallel I/O register summary . . . . . . . .33
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .36
MSTR bit . . . . . . . . . . . . . . . . . . . . . . . . .126
N
noise . . . . . . . . . . . . . . . . . . . . . . . . . . .26, 28
156
O
OCF bit . . . . . . . . . . . . . . . .71, 108, 111, 115
OCIE bit . . . . . . . . . . . . . . . . . . .71, 108–109
OLVL bit . . . . . . . . . . . . . . . . . . . . . . 104, 110
on-chip oscillator . . . . . . . . . . . . . . . . . . . .27
frequency . . . . . . . . . . . . . . . . . . . . . . . 27
stabilization delay . . . . . . . . . .66, 98, 128
opcode map . . . . . . . . . . . . . . . . . . . . . . . .64
operating temperature . . . . . . . . . . . . . . . 151
options
programmable . . . . . . . . . . . . . . . . . . .22
order numbers . . . . . . . . . . . . . . . . . . . . . 151
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . .27
output compare interrupt . . . . . . . . . 100, 104
output compare registers
(OCRH/L) . . . . . . .104, 110–111, 115
P
PA[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . .83
package dimensions
Cerdip . . . . . . . . . . . . . . . . . . . . . . . . . 150
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . 150
package types . . . . . . . . . . . . . . . . . . . . . 151
PB[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . .85
PB5/SDO pin . . . . . . . . . . . 86, 120–122, 125
PB6/SDI pin . . . . . . . . . . . .86, 120–122, 125
PB7/SCK pin . . . . . . . . . . . 85, 121–122, 125
PB7SCK pin . . . . . . . . . . . . . . . . . . . . . . .120
PC[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . .88
PC3/AN3 pin . . . . . . . . . . . . . . . 88, 131, 135
PC4/AN2 pin . . . . . . . . . . . . . . . 88, 131, 135
PC5/AN1 pin . . . . . . . . . . . . . . . 88, 131, 135
PC6/AN0 pin . . . . . . . . . . . . . . . 88, 131, 135
Index
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Index
PC7/VRH pin . . . . . . . . . . . . . . . . . . . .88, 131
PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
PD7/TCAP pin . . . . . . .39, 90, 103, 110–111
pin assignments . . . . . . . . . . . . . . . . . . . . .26
pin functions . . . . . . . . . . . . . . . . . . . . . . . .26
port A . . . . . . . . . . . . . . . . . . . . . . . . . .29, 83
data direction register A (DDRA) . . . . .83
port A data register (PORTA) . . . . . . . .83
port B . . . . . . . . . . . . . . . . . . . . . . . . . .29, 85
data direction register B (DDRB) . . . . .86
port B data register (PORTB) . . . . . . . .85
port C . . . . . . . . . . . . . . . . . . . . . . . . . .29, 87
data direction register C (DDRC) . . . . .89
port C data register (PORTC) . . . . . . . .88
port D . . . . . . . . . . . . . . . . . . . . . . . . . .29, 90
data direction register D (DDRD) . . . . .92
port D data register (PORTD) . . . . . . . .91
ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
parallel I/O port register summary . . . . .82
port A . . . . . . . . . . . . . . . . . . . . . . . . . .83
port B . . . . . . . . . . . . . . . . . . . . . . . . . .85
port C . . . . . . . . . . . . . . . . . . . . . . . . . .87
port D . . . . . . . . . . . . . . . . . . . . . . . . . .90
power dissipation . . . . . . . . . . . . . . .136, 140
power supply (VDD) . . . . . . . . . . . . . . .26, 41
power supply (VPP) . . . . . . . . . . . . . . . . . .41
power-on reset . . . . . . . . . . . . . . . . . . . . . .66
program counter (PC) . . . . . . . .52, 55, 66, 72
programmable options
COP watchdog enable/disable . . . .22, 96
external interrupt pin triggering . . . .22, 42
SIOP data format . . . . . . . . . . . . .22, 120
Q
quartz window . . . . . . . . . . . . . . . . . . . . . .37
MOTOROLA
R
RAM
locations . . . . . . . . . . . . . . . . . . . . . . . .36
stack . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reading . . . . . . . . . . . . . . . . . . . . . . . . . . 112
registers
ADC I/O register summary . . . . . . . . .131
CPU registers . . . . . . . . . . . . . . . . . . . .45
parallel I/O port register summary . . . . 82
parallel I/O register summary . . . . . . . . 33
SIOP I/O register summary . . . . . . . . 119
timer I/O register summary . . . . . . . . .102
RESET pin . . . . . . . . . . . . . . . . 28, 39, 66–68
reset sources
COP watchdog . . . . . . . . . . . . . . . . . . . 66
power-on . . . . . . . . . . . . . . . . . . . . . . . .66
RESET pin . . . . . . . . . . . . . . . . . . . . . . 66
reset vector . . . . . . . . . . . . . . . . . . . . . . . .66
resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
COP watchdog reset . . . . . . . . . . . 68, 96
COP watchdog reset operation . . . . . . 96
external reset . . . . . . . . . . . . . . . . . . . . 67
external reset timing . . . . . . . . . . . . . . .67
low-voltage protection reset . . . . . . . . . 68
power-on reset (POR) . . . . . . . . . . . . . 66
power-on reset (POR) timing . . . . . . . .67
reset sources . . . . . . . . . . . . . . . . . . . . 66
reset/interrupt vector addresses . . . . . .73
S
SIOP (serial input/output port)
block diagram . . . . . . . . . . . . . . . . . . .119
description . . . . . . . . . . . . . . . . . . . . . 118
features . . . . . . . . . . . . . . . . . . . . . . . . 118
I/O register summary . . . . . . . . . . . . . 119
I/O registers . . . . . . . . . . . . . . . . . . . . 125
low-power modes . . . . . . . . . . . . . . . . 128
operation . . . . . . . . . . . . . . . . . . . . . . .120
timing . . . . . . . . . . . . . . . . . . . . . 123–124
Index
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157
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Freescale Semiconductor, Inc...
Index
SIOP bit . . . . . . . . . . . . . . . . . . . . . . . . . . .42
SIOP control register (SCR) . . .121, 125, 127
SIOP data register (SDR) . . . . . . . . .126–127
SIOP status register (SSR) . . . . . . . . . . .126
software failure . . . . . . . . . . . . . . . . . . . . . .96
software interrupt vector . . . . . . . . . . . . . . .72
SPE bit . . . . . . . . . . . . . . .121–122, 125, 127
specifications
See "electrical specifications."
See "mechanical specifications." . . . .148
SPIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . .126
stack pointer (SP) . . . . . . . . . . . . . . . . . . . .36
stack RAM . . . . . . . . . . . . . . . . . . . . . .36, 72
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .75
effect on ADC . . . . . . . . . . . . . . . . . . .136
effect on capture/compare timer . . . . .116
effect on COP watchdog . . . . . . . . . . . .98
effect on SIOP . . . . . . . . . . . . . . . . . . .128
STOP instruction flowchart . . . . . . . . . .77
stop recovery timing . . . . . . . . . . . . . . .76
STOP/WAIT clock logic . . . . . . . . . . . . .80
supply voltage (VDD) . . . . . . . . . . . . .96, 138
T
TCMP pin . . . . . . . . . .29, 103–104, 110, 115
thermal resistance . . . . . . . . . . . . . .139–140
timer
block diagram . . . . . . . . . . . . . . . . . . .101
features . . . . . . . . . . . . . . . . . . . . . . . .100
158
I/O register summary . . . . . . . . . . . . . 102
I/O registers . . . . . . . . . . . . . . . . . . . . 108
interrupts . . . . . . . . . . . . . . . . . . . .71, 108
low-power modes . . . . . . . . . . . . . . . . 116
operation . . . . . . . . . . . . . . . . . . . . . . .101
reading . . . . . . . . . . . . . . . . . . . . 101, 113
timing . . . . . . . . . . . . . . . . . . . . . 105–107
timer control register (TCR) . . . . . . . . 71, 109
timer interrupt vector . . . . . . . . . . . . . . . . . 72
timer registers (TRH/L) . . . . . . . . . . 110–112
timer resolution . . . . . . . . . . . . . . . . . . . . 101
timer status register (TSR) .71, 110, 114–115
TOF bit . . . . . . . . . . . . . . . . 71, 108, 111–113
TOIE bit . . . . . . . . . . . . . . . . . . .71, 108–109
V
VDD power supply . . . . . . . . . . . . . . . .26, 41
VPP power supply . . . . . . . . . . . . . . . . . . . .41
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
W
wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .78
effect on ADC . . . . . . . . . . . . . . . . . . .136
effect on capture/compare timer . . . . .116
effect on COP watchdog . . . . . . . . . . . .98
effect on SIOP . . . . . . . . . . . . . . . . . .128
STOP/WAIT clock logic . . . . . . . . . . . .80
WAIT instruction flowchart . . . . . . . . . .79
Index
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MOTOROLA
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Home Page:
www.freescale.com
email:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
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