ONSEMI MC74ACT273DWR2

MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D–type
flip–flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip–flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW–to–HIGH clock transition, is transferred
to the corresponding flip–flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
•
•
•
•
•
•
•
•
•
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip–Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
′ACT273 Has TTL Compatible Inputs
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PDIP–20
N SUFFIX
CASE 738
20
1
SO–20
DW SUFFIX
CASE 751
20
1
20
1
TSSOP–20
DT SUFFIX
CASE 948E
EIAJ–20
M SUFFIX
CASE 967
20
1
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
ORDERING INFORMATION
Figure 1. Pinout: 20–Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
Device
Package
Shipping
MC74AC273N
PDIP–20
18 Units/Rail
MC74ACT273N
PDIP–20
18 Units/Rail
MC74AC273DW
SOIC–20
38 Units/Rail
MC74AC273DWR2
SOIC–20
1000 Tape & Reel
MC74ACT273DW
SOIC–20
38 Units/Rail
MC74ACT273DWR2
SOIC–20
1000 Tape & Reel
MC74AC273DT
TSSOP–20
75 Units/Rail
MC74AC273DTR2
TSSOP–20 2500 Tape & Reel
MC74ACT273DT
TSSOP–20
TSSOP–20 2500 Tape & Reel
75 Units/Rail
PIN
FUNCTION
D0–D7
Data Inputs
MC74ACT273DTR2
MR
Master Reset
MC74AC273M
EIAJ–20
40 Units/Rail
CP
Clock Pulse Input
MC74AC273MEL
EIAJ–20
2000 Tape & Reel
Q0–Q7
Data Outputs
MC74ACT273M
EIAJ–20
40 Units/Rail
MC74ACT273MEL
EIAJ–20
2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 5
1
Publication Order Number:
MC74AC273/D
MC74AC273, MC74ACT273
MODE SELECT-FUNCTION TABLE
D0 D1 D2 D3 D4 D5 D6 D7
CP
Inputs
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 2. Logic Symbol
D0
Outputs
Operating Mode
MR
CP
Dn
Qn
Reset (Clear)
L
X
X
L
Load ′1′
H
H
H
Load ′0′
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
D1
D2
D3
D4
D5
D6
D7
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
RD
RD
RD
RD
RD
RD
RD
RD
MR
O0
NOTE:
O1
O2
O3
O4
O5
O6
O7
That this diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
–65 to +150
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
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2
MC74AC273, MC74ACT273
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Min
Typ
Max
′AC
2.0
5.0
6.0
Unit
′ACT
4.5
5.0
5.5
0
–
VCC
VCC @ 3.0 V
–
150
–
VCC @ 4.5 V
–
40
–
VCC @ 5.5 V
–
25
–
VCC @ 4.5 V
–
10
–
VCC @ 5.5 V
–
8.0
–
–
–
140
°C
–40
25
85
°C
V
V
ns/V
tr, tf
In ut Rise and Fall Time (Note 2)
Input
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
Output Current – High
–
–
–24
mA
IOL
Output Current – Low
–
–
24
mA
ns/V
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
–40°C to
+85°C
Typ
VIH
VIL
VOH
VOL
Guaranteed Limits
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC – 0.1 V
Maximum
a
u Low
o Level
e e
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC – 0.1 V
Minimum
u High
g Level
e e
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
–
–
–
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
–
–
–
0.36
0.36
0.36
0.44
0.44
0.44
55
5.5
–
±0 1
±0.1
5.5
–
5.5
55
5.5
Maximum
a
u Low
o Level
e e
Output Voltage
Maximum
a
u Input
u
Leakage Current
IOLD
†Minimum Dynamic
O t t Current
Output
C
t
ICC
Conditions
Minimum
u High
g Level
e e
Input Voltage
IIN
IOHD
Unit
Maximum
a
u Quiescent
Qu esce
Supply Current
IOUT = –50 µA
V
IOUT = 50 µA
V
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
±1 0
±1.0
µA
VI = VCC, GND
–
75
mA
VOLD = 1.65 V Max
–
–
–75
mA
VOHD = 3.85 V Min
–
80
8.0
80
µA
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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3
*VIN = VIL or VIH
–12 mA
IOH
–24 mA
–24 mA
MC74AC273, MC74ACT273
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74AC
74AC
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
3.3
5.0
90
140
125
175
–
–
75
125
–
–
Mhz
3–3
tPLH
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.5
12.5
9.0
3.0
2.5
14.0
10.0
ns
3–6
tPHL
Propagation Delay
Clock to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
3.5
2.5
14.5
11.0
ns
3–6
tPHL
Propagation Delay
MR to Output
3.3
5.0
4.0
3.0
7.0
5.0
13.0
10.0
3.5
2.5
14.0
10.5
ns
3–6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
Typ
74AC
74AC
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Data to CP
3.3
5.0
3.5
2.5
5.5
4.0
6.0
4.5
ns
3–9
th
Hold Time, HIGH or LOW
Data to CP
3.3
5.0
–2.0
–1.0
0
1.0
0
1.0
ns
3–9
tw
Clock Pulse Width
HIGH or LOW
3.3
5.0
3.5
2.5
5.5
4.0
6.0
4.5
ns
3–6
tw
MR Pulse Width
HIGH or LOW
3.3
5.0
2.0
1.5
5.5
4.0
6.0
4.5
ns
3–6
trec
Recovery Time
MR to CP
3.3
5.0
1.5
1.0
3.5
2.0
4.5
3.0
ns
3–9
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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MC74AC273, MC74ACT273
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
–40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum
u High
g Level
e e
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC – 0.1 V
VIL
Maximum
a
u Low
o Level
e e
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC – 0.1 V
VOH
Minimum
u High
g Level
e e
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
–
–
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
–
–
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
VOL
Maximum
a
u Low
o Level
e e
Output Voltage
IOUT = –50 µA
*VIN = VIL or VIH
–24 mA
IOH
–24 mA
V
IOUT = 50 µA
V
IIN
Maximum
a
u Input
u
Leakage Current
55
5.5
–
±0 1
±0.1
±1 0
±1.0
µA
VI = VCC, GND
∆ICCT
Additional Max. ICC/Input
5.5
0.6
–
1.5
mA
VI = VCC – 2.1 V
IOLD
†Minimum Dynamic
O t t Current
Output
C
t
5.5
–
–
75
mA
VOLD = 1.65 V Max
5.5
–
–
–75
mA
VOHD = 3.85 V Min
55
5.5
–
80
8.0
80
µA
VIN = VCC or GND
IOHD
ICC
Maximum
a
u Quiescent
Qu esce
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
50
5.0
125
200
–
125
–
MHz
3–3
tPHL
Pro agation Delay
Propagation
Clock to Output
50
5.0
30
3.0
60
6.0
10
25
2.5
11 0
11.0
ns
3–6
tPLH
Pro agation Delay
Propagation
Clock to Output
50
5.0
30
3.0
65
6.5
11
25
2.5
12 0
12.0
ns
3–6
tPHL
Pro agation Delay
Propagation
MR to Output
50
5.0
30
3.0
70
7.0
11
25
2.5
11 5
11.5
ns
3–6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC273, MC74ACT273
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = –40°C
to +85°C
CL = 50 pF
Typ
Unit
Fig.
No.
Guaranteed Minimum
ts
Setu Time, HIGH or LOW
Setup
Data to CP
50
5.0
30
3.0
45
4.5
50
5.0
ns
3–9
th
Hold Time, HIGH or LOW
Data to CP
50
5.0
–2 5
–2.5
20
2.0
20
2.0
ns
3–9
tw
Clock Pulse Width
HIGH or LOW
50
5.0
25
2.5
40
4.0
45
4.5
ns
3–6
tw
MR Pulse Width
HIGH or LOW
50
5.0
25
2.5
40
4.0
45
4.5
ns
3–6
trec
Recovery Time
MR to CP
50
5.0
–1 0
–1.0
20
2.0
30
3.0
ns
3–6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
50
pF
VCC = 5.0 V
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6
MC74AC273, MC74ACT273
MARKING DIAGRAMS
PDIP–20
SO–20
MC74AC273N
AWLYYWW
AC273
AWLYYWW
MC74ACT273N
AWLYYWW
ACT273
AWLYYWW
A
WL, L
YY, Y
WW, W
TSSOP–20
EIAJ–20
AC
273
ALYW
74AC273
AWLYWW
ACT
273
ALYW
74ACT273
AWLYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
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7
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
20 PIN PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0
15
0.51
1.01
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
A
20
X 45 h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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8
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
MC74AC273, MC74ACT273
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
V
S
S
K
K1
11
J J1
B
L
–U–
PIN 1
IDENT
ÍÍÍ
ÍÍÍ
ÍÍÍ
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
N
F
DETAIL E
–W–
C
G
D
H
DETAIL E
0.100 (0.004)
–T– SEATING
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
PLANE
EIAJ–20
M SUFFIX
20 PIN PLASTIC EIAJ PACKAGE
CASE 967–01
ISSUE O
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M
L
10
DETAIL P
Z
D
VIEW P
e
A
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
http://onsemi.com
9
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
--0.032
MC74AC273, MC74ACT273
Notes
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10
MC74AC273, MC74ACT273
Notes
http://onsemi.com
11
MC74AC273, MC74ACT273
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC74AC273/D