MC74AC74, MC74ACT74 Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH http://onsemi.com PDIP−14 N SUFFIX CASE 646 14 1 SOIC−14 D SUFFIX CASE 751A 14 1 14 Features 1 • Outputs Source/Sink 24 mA • ′ACT74 Has TTL Compatible Inputs • Pb−Free Packages are Available 14 VCC CD2 D2 CP2 SD2 Q2 Q2 14 13 12 11 10 9 8 1 TSSOP−14 DT SUFFIX CASE 948G SOEIAJ−14 M SUFFIX CASE 965 ORDERING INFORMATION CD1 D1 Q1 CP1 SD1 Q1 See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. SD2 CP2 Q2 D2 CD2 Q2 1 2 3 4 5 6 7 CD1 D1 CP1 SD1 Q1 Q1 GND Figure 1. Pinout: 14−Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN FUNCTION D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 7 1 Publication Order Number: MC74AC74/D MC74AC74, MC74ACT74 TRUTH TABLE (Each Half) Inputs Outputs SD CD CP D Q Q L H L H H H H L L H H H X X X X X X H L X H L H H L Q0 L H H L H Q0 NOTE: L Q1 SD1 D1 CP1 Q2 SD2 D2 CP2 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial; = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock Q1 CD1 Q2 CD2 Figure 2. Logic Symbol SD D Q CP Q CD NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC74AC74, MC74ACT74 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note ) ′AC Devices except Schmitt Inputs Min Typ Max Unit ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 − VCC VCC @ 3.0 V − 150 − VCC @ 4.5 V − 40 − VCC @ 5.5 V − 25 − VCC @ 4.5 V − 10 − VCC @ 5.5 V − 8.0 − − − 140 °C −40 25 85 °C V V ns/V tr, tf Input Rise and Fall Time (Note ) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH Output Current − High − − −24 mA IOL Output Current − Low − − 24 mA ns/V 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ Unit Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 5.5 − ±0.1 5.5 − 5.5 5.5 VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current IOHD ICC Maximum Quiescent Supply Current V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 mA V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 mA VI = VCC, GND − 75 mA VOLD = 1.65 V Max − − −75 mA VOHD = 3.85 V Min − 4.0 40 mA VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. http://onsemi.com 3 V IOUT = −50 mA MC74AC74, MC74ACT74 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol VCC* (V) Parameter 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Clock Frequency 3.3 5.0 100 140 125 160 − − 95 125 − − MHz 3−3 tPLH Propagation Delay CDn or SDn to Qn or Qn 3.3 5.0 5.0 3.5 8.0 6.0 12.5 9.0 4.0 3.0 13.0 10.0 ns 3−6 tPHL Propagation Delay CDn or SDn to Qn or Qn 3.3 5.0 4.0 3.0 10.5 8.0 12.0 9.5 3.5 2.5 13.5 10.5 ns 3−6 tPLH Propagation Delay CPn to Qn or Qn 3.3 5.0 4.5 3.5 8.0 6.0 13.5 10.0 4.0 3.0 16.0 10.5 ns 3−6 tPHL Propagation Delay CPn to Qn or Qn 3.3 5.0 3.5 2.5 8.0 6.0 14.0 10.0 3.5 2.5 14.5 10.5 ns 3−6 Unit Fig. No. *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter Typ 74AC 74AC TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Guaranteed Minimum ts Set-up Time, HIGH or LOW Dn to CPn 3.3 5.0 1.5 1.0 4.0 3.0 4.5 3.0 ns 3−9 th Hold Time, HIGH or LOW Dn to CPn 3.3 5.0 −2.0 −1.5 0.5 0.5 0.5 0.5 ns 3−9 tw CPn or CDn or SDn Pulse Width 3.3 5.0 3.0 2.5 5.5 4.5 7.0 5.0 ns 3−6 trec Recovery TIme CDn or SDn to CP 3.3 5.0 −2.5 −2.0 0 0 0 0 ns 3−9 *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. http://onsemi.com 4 MC74AC74, MC74ACT74 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = −40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 4.5 5.5 − − 3.86 4.86 3.76 4.76 4.5 5.5 0.001 0.001 0.1 0.1 0.1 0.1 4.5 5.5 − − 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA VOL Maximum Low Level Output Voltage IOUT = −50 mA *VIN = VIL or VIH −24 mA IOH −24 mA V IOUT = 50 mA V IIN Maximum Input Leakage Current 5.5 − ±0.1 ±1.0 mA VI = VCC, GND DICCT Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V IOLD †Minimum Dynamic Output Current 5.5 − − 75 mA VOLD = 1.65 V Max 5.5 − − −75 mA VOHD = 3.85 V Min 5.5 − 4.0 40 mA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max Unit Fig. No. fmax Maximum Clock Frequency 5.0 145 210 − 125 − MHz 3−3 tPLH Propagation Delay CDn or SDn to Qn or Qn 5.0 3.0 5.5 9.5 2.5 10.5 ns 3−6 tPHL Propagation Delay CDn or SDn to Qn or Qn 5.0 3.0 6.0 10.0 3.0 11.5 ns 3−6 tPLH Propagation Delay CPn to Qn or Qn 5.0 4.0 7.5 11.0 4.0 13.0 ns 3−6 tPHL Propagation Delay CPn to Qn or Qn 5.0 3.5 6.0 10.0 3.0 11.5 ns 3−6 *Voltage Range 5.0 V is 5.0 V ±0.5 V. http://onsemi.com 5 MC74AC74, MC74ACT74 AC OPERATING REQUIREMENTS Symbol VCC* (V) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Set-up Time, HIGH or LOW Dn to CPn 5.0 1.0 3.0 3.5 ns 3−9 th Hold Time, HIGH or LOW Dn to CPn 5.0 −0.5 1.0 1.0 ns 3−9 tw CPn or CDn or SDn Pulse Width 5.0 3.0 5.0 6.0 ns 3−6 trec Recovery TIme CDn or SDn to CP 5.0 −2.5 0 0 ns 3−9 *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 35 pF VCC = 5.0 V http://onsemi.com 6 MC74AC74, MC74ACT74 ORDERING INFORMATION Device Package Shipping † MC74AC74N PDIP−14 MC74AC74NG PDIP−14 (Pb−Free) MC74ACT74N PDIP−14 MC74ACT74NG PDIP−14 (Pb−Free) MC74AC74D SOIC−14 MC74AC74DG SOIC−14 (Pb−Free) MC74AC74DR2 SOIC−14 MC74AC74DR2G SOIC−14 (Pb−Free) MC74ACT74D SOIC−14 MC74ACT74DG SOIC−14 (Pb−Free) MC74ACT74DR2 SOIC−14 MC74ACT74DR2G SOIC−14 (Pb−Free) 2500/Tape & Reel MC74AC74DT TSSOP−14* 96 Units/Rail MC74AC74DTR2 TSSOP−14* MC74AC74DTR2G TSSOP−14* MC74ACT74DT TSSOP−14* MC74ACT74DTR2 TSSOP−14* MC74ACT74DTR2G TSSOP−14* MC74AC74MEL SOEIAJ−14 MC74AC74MELG SOEIAJ−14 (Pb−Free) MC74ACT74MEL SOEIAJ−14 MC74ACT74MELG SOEIAJ−14 (Pb−Free) 25 Units/Rail 55 Units/Rail 2500/Tape & Reel 55 Units/Rail 2500/Tape & Reel 96 Units/Rail 2500/Tape & Reel 2000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 7 MC74AC74, MC74ACT74 MARKING DIAGRAMS PDIP−14 MC74AC74N AWLYYWWG SOIC−14 TSSOP−14 SOEIAJ−14 AC74G AWLYWW AC 74 ALYWG G 74AC74 ALYWG ACT74G AWLYWW ACT 74 ALYWG G 14 1 MC74ACT74N AWLYYWWG 14 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) http://onsemi.com 8 74ACT74 ALYWG MC74AC74, MC74ACT74 PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 9 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 MC74AC74, MC74ACT74 SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74AC74, MC74ACT74 PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S DETAIL E ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K A −V− K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74AC74, MC74ACT74 SOEIAJ−14 CASE 965−01 ISSUE A 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE M_ L 7 1 DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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