MC74LCX74 Low−Voltage CMOS Dual D−Type Flip−Flop With 5 V−Tolerant Inputs The MC74LCX74 is a high performance, dual D−type flip−flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows MC74LCX74 inputs to be safely driven from 5.0 V devices. The MC74LCX74 consists of 2 edge−triggered flip−flops with individual D−type inputs. The flip−flop will store the state of individual D inputs, that meet the setup and hold time requirements, on the LOW−to−HIGH Clock (CP) transition. http://onsemi.com MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 14 1 1 Features • • • • • • 14 Designed for 2.3 V to 3.6 V VCC Operation 5.0 V Tolerant Inputs − Interface Capability With 5.0 V TTL Logic 14 1 LVTTL Compatible TSSOP−14 DT SUFFIX CASE 948G 1 LCX 74 ALYW LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA • • ESD Performance: • LCX74G AWLYWW Human Body Model >2000 V Machine Model >200 V Pb−Free Packages are Available* 14 14 1 SOEIAJ−14 M SUFFIX CASE 965 74LCX74 ALYWG 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 May, 2005 − Rev. 5 1 Publication Order Number: MC74LCX74/D MC74LCX74 SD1 4 SD 2 D1 VCC CD2 14 13 D2 12 CP2 SD2 O2 11 10 CP1 O2 9 2 D1 3 CP1 4 5 SD1 O1 CP Q 6 7 O1 GND 1 10 12 D2 CP2 11 D Q CP Q CD CD2 13 Figure 2. Logic Diagram PIN NAMES Function CP1, CP2 Clock Pulse Inputs D1−D2 Data Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs On−On Outputs TRUTH TABLE Inputs Outputs SDn CDn CPn Dn On On Operating Mode L H X X H L Asynchronous Set H L X X L H Asynchronous Clear L L X X H H Undetermined H H ↑ h H L H H ↑ l L H H H ↑ X NC NC H h L l NC X ↑ ↑ O1 SD Figure 1. Pinout: 14−Lead (Top View) Pins 6 O1 CD SD2 1 Q 8 CD1 CD1 3 5 D L d and Load dR Read dR Register i t Hold = High Voltage Level = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition = Low Voltage Level = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition = No Change = High or Low Voltage Level and Transitions are Acceptable = Low−to−High Transition = Not a Low−to−High Transition For ICC reasons, DO NOT FLOAT Inputs http://onsemi.com 2 9 8 O2 O2 MC74LCX74 MAXIMUM RATINGS Symbol Parameter Value Condition Unit VCC DC Supply Voltage −0.5 to +7.0 V VI DC Input Voltage −0.5 ≤ VI ≤ +7.0 V VO DC Output Voltage IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA +50 VO > VCC mA −0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State (Note 1) V IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Operating Data Retention Only Min Type Max Unit 2.0 1.5 2.5, 3.3 2.5, 3.3 3.6 3.6 V 0 5.5 V 0 VCC V VCC Supply Voltage VI Input Voltage VO Output Voltage (HIGH or LOW State) (3−State) IOH HIGH Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V −24 −12 −8 mA IOL LOW Level Output Current VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V VCC = 2.3 V − 2.7 V +24 +12 +8 mA TA Operating Free−Air Temperature −40 +85 °C t/V Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V ORDERING INFORMATION Package Shipping† MC74LCX74D SOIC−14 55 Units / Rail MC74LCX74DG SOIC−14 (Pb−Free) 55 Units / Rail MC74LCX74DR2 SOIC−14 2500 Tape & Reel MC74LCX74DR2G SOIC−14 (Pb−Free) 2500 Tape & Reel MC74LCX74DT TSSOP−14* 96 Units / Rail MC74LCX74DTG TSSOP−14* 96 Units / Rail MC74LCX74DTR2 TSSOP−14* 2500 Tape & Reel MC74LCX74DTR2G TSSOP−14* 2500 Tape & Reel MC74LCX74MEL SOEIAJ−14 2000 Tape & Reel MC74LCX74MELG SOEIAJ−14 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 3 MC74LCX74 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH VIL VOH VOL Characteristic HIGH Level Input Voltage (Note 2) LOW Level Input Voltage (Note 2) HIGH Level Output Voltage LOW Level Output Voltage Condition Min 2.3 V ≤ VCC ≤ 2.7 V 1.7 2.7 V ≤ VCC ≤ 3.6 V 2.0 Max V 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V ≤ VCC ≤ 3.6 V 0.8 2.3 V ≤ VCC ≤ 3.6 V; IOH = −100 A Unit V VCC − 0.2 VCC = 2.3 V; IOH = −8 mA 1.8 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 V 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 A 0.2 VCC = 2.3 V; IOL = 8 mA 0.6 VCC = 2.7 V; IOL = 12 mA 0.4 VCC = 3.0 V; IOL = 16 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 V II Input Leakage Current 2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V ±5 A ICC Quiescent Supply Current 2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC 10 A ICC Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V ±10 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 A 2. These values of VI are used to test DC electrical characteristics only. AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 Limits TA = −40°C to +85°C Symbol Parameter VCC = 3.3 V 0.3 V VCC = 2.7 V VCC = 2.5 V 0.2 V CL = 50 pF CL = 50 pF CL = 30 pF Waveform Min fmax Clock Pulse Frequency 1 150 tPLH Propagation Delay 1 1.5 7.0 1.5 8.0 1.5 8.4 tPHL CPn to On or On 1.5 7.0 1.5 8.0 1.5 8.4 tPLH Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 tPHL SDn or CDn to On or On 1.5 7.0 1.5 8.0 1.5 8.4 ts Setup Time, HIGH or LOW Dn to CPn 1 2.5 2.5 4.0 ns th Hold Time, HIGH or LOW Dn to CPn 1 1.5 1.5 2.0 ns tw CPn Pulse Width, HIGH or LOW 4 3.3 3.3 4.0 ns 3.3 3.6 4.0 ns 2.5 3.0 4.5 ns 2 SDn or CDn Pulse Width, LOW 3 Max Min Max 150 trec Recovery Time SDn or CDn to CPn tOSHL Output−to−Output Skew 1.0 tOSLH (Note 3) 1.0 Min Max 150 Unit MHz ns ns ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 4 MC74LCX74 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition Min Typ Max Unit VOLP Dynamic LOW Peak Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.8 0.6 V V VOLV Dynamic LOW Valley Voltage (Note 4) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.8 −0.6 V V 4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit 7 pF CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF Vcc Dn Vmi 0V th ts Vcc tw CPn Vmi 0V fmax tPLH, tPHL VOH On, On Vmo VOL WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Vcc SDn 0V Vcc CDn 1.5 V 0V tPLH On tPHL Vmo Vmo VOL VOH tPLH On Vmo Vmo tPHL WAVEFORM 2 − PROPAGATION DELAYS tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 3. AC Waveforms http://onsemi.com 5 MC74LCX74 Vcc tw SDn, CDn Vmi 0V trec Vcc Vmi CPn 0V WAVEFORM 3 − RECOVERY TIME tR = tF = 2.5 ns from 10% to 90%; f = 1 MHz; tw = 500 ns Vcc CPn Vmi Vmi tw 0V Vcc tw SDn, CDn, CPn Vmi Vmi 0V WAVEFORM 4 − PULSE WIDTH tR = tF = 2.5 ns (or fast as required) from 10% to 90%; Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V Vcc Symbol 3.3 V + 0.3 V 2.7 V 2.5 V + 0.2 V Vmi 1.5 V 1.5 V Vcc/2 Vmo 1.5 V 1.5 V Vcc/2 Figure 3. AC Waveforms (Continued) VCC PULSE GENERATOR DUT RT CL = CL = RL = RT = CL RL 50 pF at VCC = 3.3 + 0.3 V or equivalent (includes jig and probe capacitance) 30 pF at VCC = 2.5 + 0.2 V or equivalent (includes jig and probe capacitance) R1 = 500 or equivalent ZOUT of pulse generator (typically 50 ) Figure 4. Test Circuit http://onsemi.com 6 MC74LCX74 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE G −A− 14 8 −B− P 7 PL 0.25 (0.010) B M M 7 1 G F R X 45 C −T− D 14 PL 0.25 (0.010) SEATING PLANE M T B A S DIM A B C D F G J K M P R J M K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 TSSOP−14 DT SUFFIX CASE 948G−01 ISSUE A 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E http://onsemi.com 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0 8 0 8 MC74LCX74 PACKAGE DIMENSIONS SOEIAJ−14 M SUFFIX CASE 965−01 ISSUE O 14 LE 8 Q1 E HE L 7 1 M DETAIL P Z D VIEW P A e c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 For additional information, please contact your local Sales Representative. MC74LCX74/D