FREESCALE MC908JB8ADWE

MC68HC908JB8
MC68HC08JB8
MC68HC08JT8
Technical Data
M68HC08
Microcontrollers
MC68HC908JB8/D
Rev. 2.3
9/2005
freescale.com
MC68HC908JB8
MC68HC08JB8
MC68HC08JT8
Technical Data
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Freescale and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Technical Data
3
Revision History
Revision History
Date
Revision
Level
September
2005
2.3
Added Pb-free parts.
August
2005
2.2
Updated to meet Freescale identity guidelines.
Page
Number(s)
Description
267, 284
Throughout
4.9 ROM-Resident Routines — Removed block erase
references for ROM-resident routines.
December
2003
61
9.8.8 USB Control Register 3 — Clarified bit descriptions for
OSTALL0 and ISTALL0.
149, 150
9.8.11 USB Status Register 1 — Clarified bit descriptions for
TXACK, TXNAK, and TXSTL.
153
Section 19. Mechanical Specifications — Replaced incorrect
44-pin QFP drawing, case 824E to case 824A.
263
2.1
Corrected PTD6 and PTD7: not direct LED drive pins.
February
2002
Technical Data
4
2
28, 210, 217
Removed incorrect RX1E text from USB control register 1.
146
Corrected Figure 9-30 for USB module.
159
Corrected timer discrepancies throughout Section 11. Timer
Interface Module (TIM).
177
Added Table 12-1 . Port Control Register Bits Summary.
201
Changed pullup resistor limits for D– and I/O ports in
18.6 DC Electrical Characteristics.
256
Added mechanical drawing for 20-pin SOIC package.
266
Added Appendix A. MC68HC08JB8 — ROM part.
269
Added Appendix B. MC68HC08JT8 — low-voltage ROM part.
277
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 27
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 51
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 5. Configuration Register (CONFIG) . . . . . . . . . 65
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 69
Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . 89
Section 8. System Integration Module (SIM) . . . . . . . . . 93
Section 9. Universal Serial Bus Module (USB) . . . . . . . 117
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 163
Section 11. Timer Interface Module (TIM) . . . . . . . . . . . 177
Section 12. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 199
Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . . 219
Section 14. Keyboard Interrupt Module (KBI). . . . . . . . 227
Section 15. Computer Operating Properly (COP) . . . . 237
Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 243
Section 17. Break Module (BREAK) . . . . . . . . . . . . . . . 245
Section 18. Electrical Specifications. . . . . . . . . . . . . . . 253
Section 19. Mechanical Specifications . . . . . . . . . . . . . 263
Section 20. Ordering Information . . . . . . . . . . . . . . . . . 267
Appendix A. MC68HC08JB8 . . . . . . . . . . . . . . . . . . . . . . 269
Appendix B. MC68HC08JT8 . . . . . . . . . . . . . . . . . . . . . . 277
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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List of Sections
Technical Data
5
List of Sections
Technical Data
6
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
List of Sections
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Table of Contents
Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.5.1
Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.2
Voltage Regulator Out (VREG) . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 35
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.5.5
External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . . 35
1.5.6
Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). . 36
1.5.7
Port B (I/O) Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . 36
1.5.8
Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.9
Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . . . 36
Section 2. Memory Map
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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Table of Contents
Section 3. Random-Access Memory (RAM)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 4. FLASH Memory
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.4
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5
FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.7
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.8
FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.8.1
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 60
4.9
ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.9.1
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.9.2
ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.9.3
PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.9.4
VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 5. Configuration Register (CONFIG)
Technical Data
8
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Section 6. Central Processor Unit (CPU)
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.7
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.9
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Section 7. Oscillator (OSC)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.3
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
7.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.4.1
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 91
7.4.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 91
7.4.3
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 91
7.4.4
External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 91
7.4.5
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.6
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Table of Contents
Section 8. System Integration Module (SIM)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 96
8.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3.2
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 97
8.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 97
8.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 99
8.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . 101
8.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 102
8.4.2.6
Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . 102
8.4.2.7
Registers Values After Different Resets. . . . . . . . . . . . . 102
8.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 103
8.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 104
8.5.3
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 104
8.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6.2
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.4
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 110
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.8
Technical Data
10
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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8.8.1
8.8.2
8.8.3
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116
Section 9. Universal Serial Bus Module (USB)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.5.1
USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.5.1.1
Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.5.1.2
Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.5.1.3
Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.5.1.4
Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.5.1.5
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 128
9.5.1.6
End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.2
Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5.3
Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.5.4
Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.5.4.1
Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.5.4.2
USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.3
Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.5
Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.6
Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.7
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.1
Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2
USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2.1
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 134
9.7.2.2
Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 134
9.7.2.3
Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.2.4
Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.2.5
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . 136
9.7.3
USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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9.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.8.1
USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.8.2
USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.8.3
USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.8.4
USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.8.5
USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.8.6
USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.8.7
USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.8.8
USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.8.9
USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 154
9.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 155
9.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 156
9.9
USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.9.1
USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . . 157
9.9.1.1
Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 158
9.9.1.2
Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . 160
9.9.1.3
Transmit Endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.9.1.4
Transmit Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.1.5
Receive Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.2
Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.3
End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Section 10. Monitor ROM (MON)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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10.4.6
10.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Section 11. Timer Interface Module (TIM)
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 182
11.5.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .183
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 183
11.5.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 184
11.5.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 185
11.5.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
11.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 188
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.9.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .189
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) . . . . . . . 189
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 190
11.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 193
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 194
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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Section 12. Input/Output Ports (I/O)
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 203
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 205
12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
12.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 215
12.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
12.8.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .217
Section 13. External Interrupt (IRQ)
Technical Data
14
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
13.5
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.6
PTE4/D– Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
13.7
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 223
13.8
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 224
13.9
IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 225
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Section 14. Keyboard Interrupt Module (KBI)
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
14.6
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.8
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 233
14.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.9.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 233
14.9.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 235
Section 15. Computer Operating Properly (COP)
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 240
15.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
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15.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 242
Section 16. Low Voltage Inhibit (LVI)
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.4
LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Section 17. Break Module (BREAK)
17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 248
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .248
17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 248
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 248
17.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
17.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 249
17.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.6.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 252
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Section 18. Electrical Specifications
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254
18.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 256
18.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
18.8
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
18.9
USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 258
18.10 USB Low-Speed Source Electrical Characteristics . . . . . . . . 259
18.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.12 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 260
18.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Section 19. Mechanical Specifications
19.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
19.3
44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 264
19.4
28-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 265
19.5
20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . 265
19.6
20-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 266
Section 20. Ordering Information
20.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
20.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
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Appendix A. MC68HC08JB8
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
A.3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
A.4
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
A.5
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
A.6
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
A.7.1
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .274
A.7.2
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
A.8
MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 275
Appendix B. MC68HC08JT8
B.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
B.3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
B.4
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
B.5
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
B.6
Reserved Register Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
B.7
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
B.8
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.9
Universal Serial Bus Module. . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.10 Low-Voltage Inhibit Module . . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .283
B.11.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .283
B.11.4 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
B.11.5 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
B.12 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 284
Technical Data
18
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Table of Contents
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Figures
Figure
Title
1-1
1-2
1-3
1-4
1-5
1-6
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 32
28-pin SOIC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 33
20-pin PDIP and SOIC Pin Assignments . . . . . . . . . . . . . . . . . 33
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . . 35
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .42
4-1
4-2
4-3
4-4
4-5
FLASH Memory Register Summary . . . . . . . . . . . . . . . . . . . . .54
FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . . 55
FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 59
FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . . 60
FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .60
5-1
Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . 66
6-1
6-2
6-3
6-4
6-5
6-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 74
7-1
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
8-1
8-2
8-3
SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
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Figure
Technical Data
20
Title
Page
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 107
Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . 109
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 111
Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 111
Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 113
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . 115
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . 116
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 120
USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Supported Transaction Types Per Endpoint. . . . . . . . . . . . . . 125
Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . . 126
Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . . 127
EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . . 129
EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
External Low-Speed Device Configuration . . . . . . . . . . . . . . . 132
Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . . 133
Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . . 135
Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . .136
USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . . 138
USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . . 139
USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 141
USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . . 144
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9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 145
USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 146
USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 147
USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . . 149
USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . . 151
USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . . 152
USB Status Register 1 (USR1). . . . . . . . . . . . . . . . . . . . . . . . 153
USB Endpoint 0 Data Registers (UE0D0–UE0D7). . . . . . . . . 154
USB Endpoint 1 Data Registers (UE1D0–UE1D7). . . . . . . . . 155
USB Endpoint 2 Data Registers (UE2D0–UE2D7). . . . . . . . . 156
OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . . 158
SETUP Token Data Flow for Receive Endpoint 0 . . . . . . . . . 159
IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . . . . 160
IN Token Data Flow for Transmit Endpoint 1 . . . . . . . . . . . . . 161
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 168
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .175
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .180
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 184
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 190
TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 192
TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 193
TIM Channel Status and Control Registers (TSC0:TSC1) . . . 194
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 198
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .200
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 203
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12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 205
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 208
Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 211
Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 215
Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Port Option Control Register (POCR). . . . . . . . . . . . . . . . . . . 217
13-1
13-2
13-3
13-4
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 221
IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .221
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 224
IRQ Option Control Register (IOCR) . . . . . . . . . . . . . . . . . . . 225
14-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 229
14-2 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 234
14-3 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 235
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
15-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . 240
15-3 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . . 241
16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . 244
17-1
17-2
17-3
17-4
17-5
17-6
17-7
Technical Data
22
Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 247
Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 247
Break Status and Control Register (BRKSCR). . . . . . . . . . . . 249
Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . 250
Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 250
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . 251
Break Flag Control Register High (BFCR) . . . . . . . . . . . . . . . 252
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19-1
19-2
19-3
19-4
44-Pin QFP (Case #824E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .265
20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . . 266
A-1
A-2
MC68HC08JB8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 271
MC68HC08JB8 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . 272
B-1
B-2
B-3
MC68HC08JT8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .279
MC68HC08JT8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 280
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Tables
Table
Title
1-1
Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4-1
4-2
4-3
4-4
4-5
ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ROM-Resident Routine Variables. . . . . . . . . . . . . . . . . . . . . . . 62
ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6-1
6-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8-1
8-2
8-3
8-4
SIM Module Signal Name Conventions . . . . . . . . . . . . . . . . . . 95
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Registers not Affected by Normal Reset. . . . . . . . . . . . . . . . . 103
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9-1
9-2
USB Module Pin Name Conventions . . . . . . . . . . . . . . . . . . . 120
Supported Packet Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 127
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
Mode Entry Requirements and Options . . . . . . . . . . . . . . . . . 166
Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . . 169
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 169
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 172
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 172
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 173
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 173
READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 174
RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 174
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11-1 TIM Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 196
12-1
12-2
12-3
12-4
12-5
12-6
Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .201
Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
14-1 KBI Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
A-1
A-2
B-1
B-2
Technical Data
26
Summary of MC68HC08JB8 and MC68HC908JB8
Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 275
Summary of MC68HC08JT8 and MC68HC908JB8
Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 284
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Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 1. General Description
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.5.1
Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.2
Voltage Regulator Out (VREG) . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 35
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.5.5
External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . . 35
1.5.6
Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). . 36
1.5.7
Port B (I/O) Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . 36
1.5.8
Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.9
Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . . . 36
1.2 Introduction
The MC68HC908JB8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
General Description
Technical Data
27
General Description
1.3 Features
Features of the MC68HC908JB8 include:
•
High-performance M68HC08 architecture
•
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
•
3-MHz internal bus frequency
•
8,192 bytes of on-chip FLASH memory
•
256 bytes of on-chip random-access memory (RAM)
•
FLASH program memory security1
•
On-chip programming firmware for use with host PC computer
•
Up to 37 general-purpose 3.3V input/output (I/O) pins, including:
– 13 or 10 shared-function I/O pins, depending on package
– 24, 8, or 2 dedicated I/O pins, depending on package
– 8 keyboard interrupts on port A, on all packages
– 10mA sink capability for normal LED on 4 pins
– 25mA sink capability for infrared LED on 2 pins
– 10mA sink capability for PS/2 connection on 2 pins
(with USB module disabled)
•
16-bit, 2-channel timer interface module (TIM) with selectable
input capture, output compare, PWM capability on each channel,
and external clock input option (TCLK)
•
Full Universal Serial Bus Specification 1.1 low-speed functions:
– 1.5 Mbps data rate
– On-chip 3.3V regulator
– Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer
– Endpoint 1 with 8-byte transmit buffer
– Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data
28
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
General Description
Freescale Semiconductor
General Description
Features
•
System protection features:
– Optional computer operating properly (COP) reset
– Optional low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
•
Low-power design (fully static with stop and wait modes)
•
Master reset pin with internal pullup and power-on reset
•
External interrupt pin with programmable internal pullup (IRQ)
•
44-pin quad flat pack (QFP), 28-pin small outline integrated circuit
package (SOIC), 20-pin small outline integrated circuit package
(SOIC), and 20-pin plastic dual in-line package (DIP)
•
Specific features of MC68HC908JB8 in 44-pin are:
– Port B is 8 bits: PTB0–PTB7
– Port C is 8 bits: PTC0–PTC7
– Port D is 8 bits: PTD0–PTD7
– Port E is 5 bits: PTE0–PTE4;
2-channel TIM module with TCLK input option
•
Specific features of MC68HC908JB8 in 28-pin are:
– Port B is not available
– Port C is only one bit: PTC0
– Port D is only 7 bits: PTD0–PTD6
– Port E is 5 bits: PTE0–PTE4;
2-channel TIM module with TCLK input option
•
Specific features of MC68HC908JB8 in 20-pin are:
– Port B is not available
– Port C is only one bit: PTC0
– Port D is only one bit: PTD0/1; internal PTD0 and PTD1 pads
are bonded together to a single pin, PTD0/1
– Port E is only 3 bits: PTE1, PTE3, and PTE4;
1-channel TIM module without TCLK input option
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
General Description
Technical Data
29
General Description
Features of the CPU08 include the following:
•
Enhanced HC05 programming model
•
Extensive loop control functions
•
16 addressing modes (eight more than the HC05)
•
16-bit index register and stack pointer
•
Memory-to-memory data transfers
•
Fast 8 × 8 multiply instruction
•
Fast 16/8 divide instruction
•
Binary-coded decimal (BCD) instructions
•
Optimization for controller applications
•
Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908JB8.
Technical Data
30
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
General Description
Freescale Semiconductor
PTA
DDRB
PTB
PTB7–PTB0 (3)
PTC
PTC7–PTC0 (3)
PTD
PTD7–PTD6 (4)
PTD5–PTD2 (4) (5)
DDRA
PTA7/KBA7 (3)
:
PTA0/KBA0 (3)
DDRC
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
CONTROL AND STATUS REGISTERS — 64 BYTES
TIMER INTERFACE
MODULE
USER FLASH MEMORY — 8,192 BYTES
USER RAM — 256 BYTES
BREAK
MODULE
MONITOR ROM — 976 BYTES
OSC1
OSC2
OSCILLATOR
LOW VOLTAGE INHIBIT
MODULE
DDRD
USER FLASH VECTORS — 16 BYTES
PTD1–PTD0 (4) (6)
POWER-ON RESET
MODULE
PTE4/D– (3) (4) (5)
(1), (3) IRQ
SYSTEM INTEGRATION
MODULE
PTE3/D+ (3) (4) (5)
COMPUTER OPERATING PROPERLY
MODULE
IRQ
MODULE
USB
MODULE
VDD
POWER
USB ENDPOINT 0, 1, 2
PTE
RST
DDRE
(1), (2)
LS USB
TRANSCEIVER
General Description
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
INTERNAL BUS
M68HC08 CPU
PTE2/TCH1 (3)
PTE1/TCH0 (3)
PTE0/TCLK (3)
VSS
INTERNAL VOLTAGE REGULATOR
31
Technical Data
Figure 1-1. MCU Block Diagram
General Description
MCU Block Diagram
VREG
(3.3 V)
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pullup device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
General Description
OSC2
OSC1
VSS
PTB3
PTB4
PTB5
PTB6
PTB7
RST
PTA0/KBA0
PTA1/KBA1
44
43
42
41
40
39
38
37
36
35
34
1.5 Pin Assignments
VREG
1
33
PTA2/KBA2
VDD
2
32
PTA3/KBA3
PTB2
3
31
PTC7
PTB1
4
30
PTC6
PTB0
5
29
PTC5
PTD0
6
28
PTC4
PTD1
7
27
PTE0/TCLK
PTD2
17
18
19
20
21
22
IRQ
PTD7
PTD6
PTD5
PTA7/KBA7
PTA6/KBA6
16
23
PTC3
11
PTC2
PTA5/KBA5
15
24
14
10
PTC1
PTD4
PTE1/TCH0
PTC0
PTA4/KBA4
13
9
12
PTE2/TCH1
25
PTE4/D–
26
PTE3/D+
8
PTD3
Figure 1-2. 44-Pin QFP Pin Assignments
Technical Data
32
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
General Description
Freescale Semiconductor
General Description
Pin Assignments
VSS
1
28
RST
OSC1
2
27
PTA0/KBA0
OSC2
3
26
PTA1/KBA1
VREG
4
25
PTA2/KBA2
VDD
5
24
PTA3/KBA3
PTD0
6
23
PTE0/TCLK
PTB0
Pins not available on 28-pin package:
PTD1
7
22
PTE2/TCH1
PTD2
8
21
PTA4/KBA4
PTB1
PTC1
PTD3
9
20
PTA5/KBA5
PTB2
PTC2
PTD4
10
19
PTA6/KBA6
PTB3
PTC3
PTB4
PTC4
PTB5
PTC5
PTB6
PTC6
PTB7
PTC7
PTE1/TCH0
11
18
PTA7/KBA7
PTE3/D+
12
17
PTD5
PTE4/D–
13
16
PTD6
PTC0
14
15
IRQ
PTD7
Internal pads are unconnected.
Figure 1-3. 28-Pin SOIC Pin Assignments
PTD0/1 pin: PTD0 and PTD1 internal pads are
bonded together to PTD0/1 pin.
VSS
1
20
RST
OSC1
2
19
PTA0/KBA0
18
PTA1/KBA1
PTB0
PTB1
PTC1
OSC2
3
Pins not available on 20-pin package:
PTE0/TCLK
VREG
4
17
PTA2/KBA2
VDD
5
16
PTA3/KBA3
PTB2
PTC2
PTD2
PTD0/1
6
15
PTA4/KBA4
PTB3
PTC3
PTD3
PTE1/TCH0
7
14
PTA5/KBA5
PTB4
PTC4
PTD4
PTB5
PTC5
PTD5
PTB6
PTC6
PTD6
PTB7
PTC7
PTD7
PTE3/D+
8
13
PTA6/KBA6
PTE4/D–
9
12
PTA7/KBA7
10
11
IRQ
PTC0
PTE2/TCH1
Internal pads are unconnected.
Figure 1-4. 20-Pin PDIP and SOIC Pin Assignments
NOTE:
In 20-pin package, the PTD0 and PTD1 internal pads are bonded
together to PTD0/1 pin.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
General Description
Technical Data
33
General Description
1.5.1 Power Supply Pins (VDD, VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the bypass capacitors as close to the MCU power pins as
possible. Use high-frequency-response ceramic capacitors for CBYPASS.
CBULK are optional bulk current bypass capacitors for use in applications
that require the port pins to source high current levels.
MCU
VDD
VSS
CBYPASS
0.1 µF
+
CBULK
VDD
NOTE: Values shown are typical values.
Figure 1-5. Power Supply Bypassing
1.5.2 Voltage Regulator Out (VREG)
VREG is the 3.3 V output of the on-chip voltage regulator. VREG is used
internally for the MCU operation and the USB data driver. It is also used
to supply the voltage for the external pullup resistor required on the
USB’s D– line. The VREG pin requires an external bulk capacitor 4.7µF
or larger and a 0.1 µF ceramic bypass capacitor as Figure 1-6 shows.
Place the bypass capacitors as close to the VREG pin as possible.
Technical Data
34
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
General Description
Freescale Semiconductor
General Description
Pin Assignments
VREG
MCU
VSS
CREGBYPASS
0.1 µF
+
CREGBULK
> 4.7 µF
VREG
Figure 1-6. Regulator Supply Capacitor Configuration
1.5.3 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit.
1.5.4 External Reset Pin (RST)
A logic zero on the RST pin forces the MCU to a known start-up state.
RST is bidirectional, allowing a reset of the entire system. It is driven low
when any internal reset source is asserted. The RST pin contains an
internal pullup device to VDD. (See Section 8. System Integration
Module (SIM).)
1.5.5 External Interrupt Pins (IRQ, PTE4/D–)
IRQ is an asynchronous external interrupt pin. IRQ is also the pin to
enter monitor mode. The IRQ pin contains a software configurable pullup
device to VDD. PTE4/D– can be programmed to trigger the IRQ interrupt.
(See Section 13. External Interrupt (IRQ).)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
General Description
Technical Data
35
General Description
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0)
PTA7/KBA7–PTA0/KBA0 are general-purpose bidirectional I/O port
pins. (See Section 12. Input/Output Ports (I/O).) Each pin contains a
software configurable pullup device to VREG when the pin is configured
as an input. (See 12.8 Port Options.) Each pin can also be programmed
as an external keyboard interrupt pin. (See Section 14. Keyboard
Interrupt Module (KBI).)
1.5.7 Port B (I/O) Pins (PTB7–PTB0)
PTB7–PTB0 are general-purpose bidirectional I/O port pins. Each pin
contains a software configurable pullup device to VREG when the pin is
configured as an input. (See 12.8 Port Options.)
1.5.8 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are general-purpose bidirectional I/O port pins. (See
Section 12. Input/Output Ports (I/O).) Each pin contains a software
configurable pullup device to VREG when the pin is configured as an
input. (See 12.8 Port Options.)
1.5.9 Port D I/O Pins (PTD7–PTD0)
PTD7–PTD0 are general-purpose bidirectional I/O port pins; open-drain
when configured as output. (See Section 12. Input/Output Ports (I/O).)
PTD5–PTD2 are software configurable to be 10mA sink pins for direct
LED connections. PTD1–PTD0 are software configurable to be 25mA
sink pins for direct infrared LED connections. (See 12.8 Port Options.)
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1, PTE1/TCH0, PTE0/TCLK)
Port E is a 5-bit special function port that shares two of its pins with the
USB module and three of its pins with the timer interface module.
Each PTE2–PTE0 pin contains a software configurable pullup device to
VREG when the pin is configured as an input or output.
Technical Data
36
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
General Description
Freescale Semiconductor
General Description
Pin Assignments
When the USB module is disabled, the PTE4 and PTE3 pins are
general-purpose bidirectional I/O port pins with 10mA sink capability.
Each pin is open-drain when configured as an output; and each pin
contains a software configurable 5kΩ pullup to VDD when configured as
an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt.
When the USB module is enabled, the PTE4/D– and PTE3/D+ pins
become the USB module D– and D+ pins. The D– pin contains a
software configurable 1.5kΩ pullup to VREG. (See Section 11. Timer
Interface Module (TIM), Section 9. Universal Serial Bus Module
(USB) and Section 12. Input/Output Ports (I/O).)
Summary of the pin functions are provided in Table 1-1.
Table 1-1. Summary of Pin Functions
PIN NAME
PIN DESCRIPTION
IN/OUT
VOLTAGE LEVEL
IN
4.0 to 5.5V
VDD
Power supply.
VSS
Power supply ground.
OUT
0V
VREG
Regulated 3.3V output from MCU.
OUT
VREG (3.3V)
RST
Reset input; active low.
With internal pullup to VDD and schmitt trigger input.
IN/OUT
VDD
External IRQ pin; with programmable internal pullup to VDD
and schmitt trigger input.
IN
VDD
Used for mode entry selection.
IN
VREG to VDD +VHI
OSC1
Crystal oscillator input.
IN
VREG
OSC2
Crystal oscillator output; inverting of OSC1 signal.
OUT
VREG
IN/OUT
VREG
Pins as keyboard interrupts, KBA0–KBA7.
IN
VREG
Each pin has programmable internal pullup to VREG when
configured as input.
IN
VREG
IN/OUT
VREG
IN
VREG
IRQ
8-bit general-purpose I/O port.
PTA0/KBA0
:
PTA7/KBA7
8-bit general-purpose I/O port.
PTB0–PTB7
Each pin has programmable internal pullup to VREG when
configured as input.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
General Description
Technical Data
37
General Description
Table 1-1. Summary of Pin Functions
PIN NAME
PIN DESCRIPTION
IN/OUT
VOLTAGE LEVEL
IN/OUT
VREG
IN
VREG
8-bit general-purpose I/O port;
open-drain when configured as output.
IN
OUT
VREG
VREG or VDD
PTD0–PTD1 have configurable 25mA sink for infrared LED.
OUT
VREG or VDD
PTD2–PTD5 have configurable 10mA sink for LED.
OUT
VREG or VDD
PTE0–PTE2 are general-purpose I/O pins.
IN/OUT
VREG
PTE0–PTE2 have programmable internal pullup to VREG
when configured as input or output.
IN/OUT
VREG
PTE0 as TCLK of timer interface module.
IN
VREG
PTE1 as TCH0 of timer interface module.
IN/OUT
VREG
PTE2 as TCH1 of timer interface module.
IN/OUT
VREG
IN
OUT
VDD
VREG or VDD
IN
VDD
8-bit general-purpose I/O port.
PTC0–PTC7
PTD0–PTD7
PTE0/TCLK
PTE1/TCH0
Each pin has programmable internal pullup to VREG when
configured as input.
PTE2/TCH1
PTE3–PTE4 are general-purpose I/O pins;
open-drain when configured as output.
PTE3/D+
PTE3–PTE4 have programmable internal pullup to VDD
when configured as input.
PTE4/D–
PTE3 as D+ of USB module.
IN/OUT
VREG
PTE4 as D– of USB module.
IN/OUT
VREG
IN
VDD
PTE4 as additional IRQ interrupt.
Technical Data
38
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
General Description
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 2. Memory Map
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
•
8,192 bytes of user FLASH memory
•
256 bytes of RAM
•
16 bytes of user-defined vectors
•
976 bytes of monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Memory Map
Technical Data
39
Memory Map
$0000
↓
$003F
I/O Registers
64 Bytes
$0040
↓
$013F
RAM
256 Bytes
$0140
↓
$DBFF
Unimplemented
56,000 Bytes
$DC00
↓
$FBFF
FLASH
8,192 Bytes
$FC00
↓
$FDFF
Monitor ROM 1
512 Bytes
$FE00
Break Status Register (BSR)
$FE01
Reset Status Register (RSR)
$FE02
Reserved
$FE03
Break Flag Control Register (BFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Reserved
$FE06
Reserved
$FE07
Reserved
$FE08
FLASH Control Register (FLCR)
$FE09
FLASH Block Protect Register (FLBPR)
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address High Register (BRKH)
$FE0D
Break Address Low Register (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
Reserved
$FE10
↓
$FFDF
Monitor ROM 2
464 Bytes
$FFE0
↓
$FFEF
Reserved
16 Bytes
$FFF0
↓
$FFFF
FLASH Vectors
16 Bytes
Figure 2-1. Memory Map
Technical Data
40
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor
Memory Map
I/O Section
2.3 I/O Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
•
$FE00; break status register, BSR
•
$FE01; reset status register, RSR
•
$FE02; reserved
•
$FE03; break flag control register, BFCR
•
$FE04; interrupt status register 1, INT1
•
$FE05; reserved
•
$FE06; reserved
•
$FE07; reserved
•
$FE08; FLASH control register, FLCR
•
$FE09; FLASH block protect register, FLBPR
•
$FE0A; reserved
•
$FE0B; reserved
•
$FE0C; break Address Register High, BRKH
•
$FE0D; break Address Register Low, BRKL
•
$FE0E; break status and control register, BRKSCR
•
$FFFF; COP control register, COPCTL
2.4 Monitor ROM
The 512 bytes at addresses $FC00–$FDFF and 464 bytes at addresses
$FE10–$FFDF are reserved ROM addresses that contain the
instructions for the monitor functions. (See Section 10. Monitor ROM
(MON).)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Memory Map
Technical Data
41
Memory Map
Addr.
Register Name
$0000
Read:
Port A Data Register
Write:
(PTA)
Reset:
$0001
$0002
$0003
Read:
Port B Data Register
Write:
(PTB)
Reset:
Read:
Port C Data Register
Write:
(PTC)
Reset:
Read:
Port D Data Register
Write:
(PTD)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
PTC7
PTC6
PTC5
PTC4
PTC3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
Read:
DDRA7
Data Direction Register A
$0004
Write:
(DDRA)
Reset:
0*
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
0
PTE4
PTE3
PTE2
PTE1
PTE0
* DDRA7 bit is reset by POR or LVI reset only.
Read:
DDRB7
Data Direction Register B
$0005
Write:
(DDRB)
Reset:
0
Read:
DDRC7
Data Direction Register C
$0006
Write:
(DDRC)
Reset:
0
Read:
DDRD7
Data Direction Register D
$0007
Write:
(DDRD)
Reset:
0
Read:
Port E Data Register
Write:
(PTE)
Reset:
0
Read:
Data Direction Register E
$0009
Write:
(DDRE)
Reset:
0
0
0
0
0
$0008
Unaffected by reset
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Technical Data
42
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor
Memory Map
Monitor ROM
Addr.
$000A
Register Name
Bit 7
Read:
TIM Status and Control
Register Write:
(TSC)
Reset:
6
5
TOIE
TSTOP
0
0
1
0
TOF
0
4
3
2
1
Bit 0
0
0
PS2
PS1
PS0
0
0
0
0
TRST
Read:
$000B
Unimplemented Write:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
$000C
Read:
TIM Counter Register
High Write:
(TCNTH)
Reset:
0
0
0
0
0
0
0
0
Read:
TIM Counter Register
Low Write:
(TCNTL)
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
$000D
$000E
$000F
Read:
TIM Counter Modulo
Register High Write:
(TMODH)
Reset:
Read:
TIM Counter Modulo
Register Low Write:
(TMODL)
Reset:
Read:
TIM Channel 0 Status and
$0010
Control Register Write:
(TSC0)
Reset:
$0011
$0012
Read:
TIM Channel 0
Register High Write:
(TCH0H)
Reset:
Read:
TIM Channel 0
Register Low Write:
(TCH0L)
Reset:
Read:
TIM Channel 1 Status and
$0013
Control Register Write:
(TSC1)
Reset:
CH0F
0
Indeterminate after reset
Bit7
Bit6
Bit5
Bit4
Bit3
Indeterminate after reset
CH1F
0
0
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
= Unimplemented
R
0
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Memory Map
Technical Data
43
Memory Map
Addr.
Register Name
Read:
TIM Channel 1
Register High Write:
(TCH1H)
Reset:
$0014
$0017
$0018
$0019
$001A
6
5
4
3
2
1
Bit 0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
IMASKK
MODEK
Indeterminate after reset
Read:
TIM Channel 1
Register Low Write:
(TCH1L)
Reset:
$0015
$0016
Bit 7
Bit7
0
Read:
USB Control Register 3
Write:
(UCR3)
Reset:
Bit4
Bit3
0
0
0
KEYF
0
ACKK
0
0
0
0
0
0
0
0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSTFR
TXD2FR
RXD2FR
0
0
0
0
0
0
0
T2SEQ
STALL2
TX2E
RX2E
TP2SIZ3
TP2SIZ2
TP2SIZ1
TP2SIZ0
0
0
0
0
0
0
0
0
TX1ST
0
OSTALL0
ISTALL0
Read:
0
USB Interrupt Register 2
Write: EOPFR
(UIR2)
Reset:
0
Read:
USB Control Register 2
Write:
(UCR2)
Reset:
Bit5
Indeterminate after reset
Read:
Keyboard Status and
Control Register Write:
(KBSCR)
Reset:
Read:
Keyboard Interrupt
Enable Register Write:
(KBIER)
Reset:
Bit6
TX1STR
TDX1FR RESUMFR TXD0FR
0
0
0
0
0
0
Read:
USB Control Register 4
Write:
(UCR4)
Reset:
0
0
0
0
0
0
0
0
0
Read:
IRQ Option Control
Register Write:
(IOCR)
Reset:
0
0
0
0
0
0
RXD0FR
PULLEN ENABLE2 ENABLE1
0*
0
0
FUSBO
FDP
FDM
0
0
0
0
0
0
PTE4IF
PTE4IE
IRQPD
0
0
0
0
0
PTE4P
PTE3P
PCP
PBP
PAP
0
0
0
0
0
0
= Unimplemented
R
* PULLEN bit is reset by POR or LVI reset only.
$001B
$001C
$001D
Read:
Port Option Control
PTE20P
Register Write:
(POCR)
Reset:
0
PTDLDD PTDILDD
0
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Technical Data
44
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor
Memory Map
Monitor ROM
Addr.
$001E
$001F
Register Name
Bit 7
6
5
4
3
2
Read:
IRQ Status and Control
Register Write:
(ISCR)
Reset:
0
0
0
0
IRQF
0
0
0
Read:
Configuration Register
Write:
(CONFIG)†
Reset:
0
0
0
0
ACK
1
Bit 0
IMASK
MODE
0
0
0
0
0
0
URSTD
LVID
SSREC
COPRS
STOP
COPD
0
0
0
0
0
0
† One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Read: UE0R07
USB Endpoint 0 Data
Register 0 Write: UE0T07
(UE0D0)
Reset:
UE0R06
UE0R05
UE0R04
UE0R03
UE0R02
UE0R01
UE0R00
UE0T06
UE0T05
UE0T04
UE0T03
UE0T02
UE0T01
UE0T00
Read: UE0R17
USB Endpoint 0 Data
Register 1 Write: UE0T17
(UE0D1)
Reset:
UE0R16
UE0R15
UE0R14
UE0R13
UE0R12
UE0R11
UE0R10
UE0T16
UE0T15
UE0T14
UE0T13
UE0T12
UE0T11
UE0T10
Read: UE0R27
USB Endpoint 0 Data
Register 2 Write: UE0T27
(UE0D2)
Reset:
UE0R26
UE0R25
UE0R24
UE0R23
UE0R22
UE0R21
UE0R20
UE0T26
UE0T25
UE0T24
UE0T23
UE0T22
UE0T21
UE0T20
Read: UE0R37
USB Endpoint 0 Data
Register 3 Write: UE0T37
(UE0D3)
Reset:
UE0R36
UE0R35
UE0R34
UE0R33
UE0R32
UE0R31
UE0R30
UE0T36
UE0T35
UE0T34
UE0T33
UE0T32
UE0T31
UE0T30
Read: UE0R47
USB Endpoint 0 Data
Register 4 Write: UE0T47
(UE0D4)
Reset:
UE0R46
UE0R45
UE0R44
UE0R43
UE0R42
UE0R41
UE0R40
UE0T46
UE0T45
UE0T44
UE0T43
UE0T42
UE0T41
UE0T40
Read: UE0R57
USB Endpoint 0 Data
Register 5 Write: UE0T57
(UE0D5)
Reset:
UE0R56
UE0R55
UE0R54
UE0R53
UE0R52
UE0R51
UE0R50
UE0T56
UE0T55
UE0T54
UE0T53
UE0T52
UE0T51
UE0T50
Read: UE0R67
USB Endpoint 0 Data
Register 6 Write: UE0T67
(UE0D6)
Reset:
UE0R66
UE0R65
UE0R64
UE0R63
UE0R62
UE0R61
UE0R60
UE0T66
UE0T65
UE0T64
UE0T63
UE0T62
UE0T61
UE0T60
Read: UE0R77
USB Endpoint 0 Data
Register 7 Write: UE0T77
(UE0D7)
Reset:
UE0R76
UE0R75
UE0R74
UE0R73
UE0R72
UE0R71
UE0R70
UE0T76
UE0T75
UE0T74
UE0T73
UE0T72
UE0T71
UE0T70
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Memory Map
Technical Data
45
Memory Map
Addr.
Register Name
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
Bit 7
6
5
4
3
2
1
Bit 0
Read:
USB Endpoint 1 Data
Register 0 Write: UE1T07
(UE1D0)
Reset:
UE1T06
UE1T05
UE1T04
UE1T03
UE1T02
UE1T01
UE1T00
Read:
USB Endpoint 1 Data
Register 1 Write: UE1T17
(UE1D1)
Reset:
UE1T16
UE1T12
UE1T11
UE1T10
Read:
USB Endpoint 1 Data
Register 2 Write: UE1T27
(UE1D2)
Reset:
UE1T26
UE1T22
UE1T21
UE1T20
Read:
USB Endpoint 1 Data
Register 3 Write: UE1T37
(UE1D3)
Reset:
UE1T36
UE1T32
UE1T31
UE1T30
Read:
USB Endpoint 1 Data
Register 4 Write: UE1T47
(UE1D4)
Reset:
UE1T46
UE1T42
UE1T41
UE1T40
Read:
USB Endpoint 1 Data
Register 5 Write: UE1T57
(UE1D5)
Reset:
UE1T56
UE1T52
UE1T51
UE1T50
Read:
USB Endpoint 1 Data
Register 6 Write: UE1T67
(UE1D6)
Reset:
UE1T66
UE1T62
UE1T61
UE1T60
Read:
USB Endpoint 1 Data
Register 7 Write: UE1T77
(UE1D7)
Reset:
UE1T76
UE1T72
UE1T71
UE1T70
Unaffected by reset
UE1T15
UE1T14
UE1T13
Unaffected by reset
UE1T25
UE1T24
UE1T23
Unaffected by reset
UE1T35
UE1T34
UE1T33
Unaffected by reset
UE1T45
UE1T44
UE1T43
Unaffected by reset
UE1T55
UE1T54
UE1T53
Unaffected by reset
UE1T65
UE1T64
UE1T63
Unaffected by reset
UE1T75
UE1T74
UE1T73
Unaffected by reset
Read: UE2R07
USB Endpoint 2 Data
Register 0 Write: UE2T07
(UE2D0)
Reset:
UE2R06
UE2R05
UE2R04
UE2R03
UE2R02
UE2R01
UE2R00
UE2T06
UE2T05
UE2T04
UE2T03
UE2T02
UE2T01
UE2T00
Read: UE2R17
USB Endpoint 2 Data
Register 1 Write: UE2T17
(UE2D1)
Reset:
UE2R16
UE2R15
UE2R14
UE2R13
UE2R12
UE2R11
UE2R10
UE2T16
UE2T15
UE2T14
UE2T13
UE2T12
UE2T11
UE2T10
Unaffected by reset
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
Technical Data
46
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor
Memory Map
Monitor ROM
Addr.
Register Name
$0032
$0033
$0034
$0035
$0036
$0037
$0038
Bit 7
6
5
4
3
2
1
Bit 0
Read: UE2R27
USB Endpoint 2 Data
Register 2 Write: UE2T27
(UE2D2)
Reset:
UE2R26
UE2R25
UE2R24
UE2R23
UE2R22
UE2R21
UE2R20
UE2T26
UE2T25
UE2T24
UE2T23
UE2T22
UE2T21
UE2T20
Read: UE2R37
USB Endpoint 2 Data
Register 3 Write: UE2T37
(UE2D3)
Reset:
UE2R36
UE2R35
UE2R34
UE2R33
UE2R32
UE2R31
UE2R30
UE2T36
UE2T35
UE2T34
UE2T33
UE2T32
UE2T31
UE2T30
Read: UE2R47
USB Endpoint 2 Data
Register 4 Write: UE2T47
(UE2D4)
Reset:
UE2R46
UE2R45
UE2R44
UE2R43
UE2R42
UE2R41
UE2R40
UE2T46
UE2T45
UE2T44
UE2T43
UE2T42
UE2T41
UE2T40
Read: UE2R57
USB Endpoint 2 Data
Register 5 Write: UE2T57
(UE2D5)
Reset:
UE2R56
UE2R55
UE2R54
UE2R53
UE2R52
UE2R51
UE2R50
UE2T56
UE2T55
UE2T54
UE2T53
UE2T52
UE2T51
UE2T50
Read: UE2R67
USB Endpoint 2 Data
Register 6 Write: UE2T67
(UE2D6)
Reset:
UE2R66
UE2R65
UE2R64
UE2R63
UE2R62
UE2R61
UE2R60
UE2T66
UE2T65
UE2T64
UE2T63
UE2T62
UE2T61
UE2T60
Read: UE2R77
USB Endpoint 2 Data
Register 7 Write: UE2T77
(UE2D7)
Reset:
UE2R76
UE2R75
UE2R74
UE2R73
UE2R72
UE2R71
UE2R70
UE2T76
UE2T75
UE2T74
UE2T73
UE2T72
UE2T71
UE2T70
Read:
USBEN
USB Address Register
Write:
(UADDR)
Reset:
0*
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
0
0
0
0
0
0
0
EOPIE
SUSPND
TXD2IE
RXD2IE
TXD1IE
TXD0IE
RXD0IE
0
0
0
0
0
0
0
0
EOPF
RSTF
TXD2F
RXD2F
TXD1F
RESUMF
TXD0F
RXD0F
0
0
0
0
0
0
0
0
TX0E
RX0E
TP0SIZ3
TP0SIZ2
TP0SIZ1
TP0SIZ0
0
0
0
0
0
0
= Unimplemented
R
* USBEN bit is reset by POR or LVI reset only.
$0039
$003A
$003B
Read:
USB Interrupt Register 0
Write:
(UIR0)
Reset:
Read:
USB Interrupt Register 1
Write:
(UIR1)
Reset:
Read:
USB Control Register 0
Write:
(UCR0)
Reset:
T0SEQ
0
0
0
= Reserved
0
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Memory Map
Technical Data
47
Memory Map
Addr.
$003C
$003D
$003E
Register Name
Bit 7
6
5
T1SEQ
STALL1
TX1E
0
0
0
0
Read: R0SEQ
USB Status Register 0
Write:
(USR0)
Reset:
SETUP
0
0
Read: R2SEQ
USB Status Register 1
Write:
(USR1)
Reset:
U
TXACK
TXNAK
TXSTL
0
0
R
R
Read:
USB Control Register 1
Write:
(UCR1)
Reset:
4
3
2
1
Bit 0
TP1SIZ2
TP1SIZ1
TP1SIZ0
0
0
0
0
RP0SIZ3
RP0SIZ2
RP0SIZ1
RP0SIZ0
RP2SIZ3
RP2SIZ2
RP2SIZ1
RP2SIZ0
0
U
U
U
U
R
R
R
FRESUM TP1SIZ3
Unaffected by reset
Read:
$003F
Unimplemented Write:
$FE00
Read:
Break Status Register
Write:
(BSR)
Reset:
R
SBSW
See note
R
0
Note: Writing a logic 0 clears SBSW.
$FE01
Read:
Reset Status Register
Write:
(RSR)
POR:
Read:
$FE02
Reserved Write:
$FE03
Read:
Break Flag Control
Register Write:
(BFCR)
Reset:
Read:
Interrupt Status Register 1
$FE04
Write:
(INT1)
Reset:
Read:
$FE05
Reserved Write:
POR
PIN
COP
ILOP
ILAD
USB
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
= Unimplemented
R
0
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
Technical Data
48
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor
Memory Map
Monitor ROM
Addr.
Register Name
Read:
$FE06
Reserved Write:
Read:
$FE07
Reserved Write:
$FE08
Read:
FLASH Control Register
Write:
(FLCR)
Reset:
$FE09
Read:
FLASH Block Protect
Register Write:
(FLBPR)
Reset:
Read:
$FE0A
Reserved Write:
Read:
$FE0B
Reserved Write:
$FE0C
Read:
Break Address High
Register Write:
(BRKH)
Reset:
$FE0D
Read:
Break Address low
Register Write:
(BRKL)
Reset:
Read:
Break Status and Control
$FE0E
Register Write:
(BRKSCR)
Reset:
$FFFF
Read:
COP Control Register
Write:
(COPCTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
0
0
0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Low byte of reset vector
Writing clears COP counter (any value)
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Memory Map
Technical Data
49
Memory Map
Table 2-1 is a list of vector locations.
Table 2-1. Vector Addresses
Vector Priority
INT Flag
Lowest
Address
Vector
$FFF0
Keyboard Vector (High)
$FFF1
Keyboard Vector (Low)
$FFF2
TIM Overflow Vector (High)
$FFF3
TIM Overflow Vector (Low)
$FFF4
TIM Channel 1 Vector (High)
$FFF5
TIM Channel 1 Vector (Low)
$FFF6
TIM Channel 0 Vector (High)
$FFF7
TIM Channel 0 Vector (Low)
$FFF8
IRQ Vector (High)
$FFF9
IRQ Vector (Low)
$FFFA
USB Vector (High)
$FFFB
USB Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
IF6
IF5
IF4
IF3
IF1
IF2
—
—
Highest
Technical Data
50
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2 Introduction
This section describes the 256 bytes of RAM.
3.3 Functional Description
Addresses $0040–$013F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:
For M6805 Family compatibility, the H register is not stacked.
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Random-Access Memory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE:
Technical Data
52
Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
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Random-Access Memory (RAM)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 4. FLASH Memory
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.4
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5
FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.7
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.8
FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.8.1
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 60
4.9
ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.9.1
Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.9.2
ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.9.3
PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.9.4
VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
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FLASH Memory
Addr.
$FE08
$FE09
Register Name
Bit 7
6
5
4
FLASH Control Register Read:
(FLCR) Write:
0
0
0
0
Reset:
0
0
0
BPR7
BPR6
0
0
FLASH Block Protect Read:
Register
(FLBPR) Write:
Reset:
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
0
0
0
0
0
0
Figure 4-1. FLASH Memory Register Summary
4.3 Functional Description
The FLASH memory consists of an array of 8,192 bytes for user memory
plus a small block of 16 bytes for user interrupt vectors. An erased bit
reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory is block erasable. The minimum erase block size is 512 bytes.
Program and erase operation operations are facilitated through control
bits in FLASH control register (FLCR).The address ranges for the
FLASH memory are shown as follows:
•
$DC00–$FBFF (user memory; 8,192 bytes)
•
$FFF0–$FFFF (user interrupt vectors; 16 bytes)
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE:
A security feature prevents viewing of the FLASH contents.1
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
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Freescale Semiconductor
FLASH Memory
FLASH Control Register
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address:
Read:
$FE08
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
Write:
Reset:
0
0
0
0
Figure 4-2. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the
memory for either program or erase operation. It can only be set if
either PGM or ERASE is high and the sequence for erase or
program/verify is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
1 = Mass Erase operation selected
0 = Block Erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. This bit
and the PGM bit should not be set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. This
bit and the ERASE bit should not be set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
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FLASH Memory
4.5 FLASH Block Erase Operation
Use the following procedure to erase a block of FLASH memory. A block
consists of 512 consecutive bytes starting from addresses $X000,
$X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. Any block
within the 8,192 bytes user memory area ($DC00–$FBFF) can be
erased alone.
NOTE:
The 16-byte user vectors, $FFF0–$FFFF, cannot be erased by the block
erase operation because of security reasons. Mass erase is required to
erase this block.
1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Write any data to any FLASH address within the address range of
the block to be erased.
3. Wait for a time, tnvs (5 µs).
4. Set the HVEN bit.
5. Wait for a time terase (2 ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh (5 µs).
8. Clear the HVEN bit.
9. After time, trcv (1 µs), the memory can be accessed in read mode
again.
NOTE:
Technical Data
56
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
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FLASH Memory
FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Write any data to any FLASH address within the address range
$FFE0–$FFFF.
3. Wait for a time, tnvs (5 µs).
4. Set the HVEN bit.
5. Wait for a time tme (2 ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh1 (100 µs).
8. Clear the HVEN bit.
9. After time, trcv (1 µs), the memory can be accessed in read mode
again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
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FLASH Memory
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80 or $XXC0. The procedure for programming a row of the
FLASH memory is outlined below:
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Write any data to any FLASH address within the address range of
the row to be programmed.
3. Wait for a time, tnvs (5 µs).
4. Set the HVEN bit.
5. Wait for a time, tpgs (10 µs).
6. Write data to the byte being programmed.
7. Wait for time, tPROG (20 µs).
8. Repeat step 6 and 7 until all the bytes within the row are
programmed.
9. Clear the PGM bit.
10. Wait for time, tnvh (5 µs).
11. Clear the HVEN bit.
12. After time, trcv (1 µs), the memory can be accessed in read mode
again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum (see 18.13
Memory Characteristics).
Figure 4-3 shows a flowchart representation for programming the
FLASH memory.
Technical Data
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Freescale Semiconductor
FLASH Memory
FLASH Program Operation
1
Algorithm for programming
a row (64 bytes) of FLASH memory
Set PGM bit
2
Write any data to any FLASH address
within the row address range desired
3
Wait for a time, tnvs
4
Set HVEN bit
5
Wait for a time, tpgs
6
Write data to the FLASH address
to be programmed
7
Wait for a time, tPROG
Completed
programming
this row?
Y
N
NOTE:
The time between each FLASH address change (step 6 to step 6), or
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
must not exceed the maximum programming
time, tPROG max.
9
Clear PGM bit
10
Wait for a time, tnvh
11
Clear HVEN bit
12
Wait for a time, trcv
This row program algorithm assumes the row/s
to be programmed are initially erased.
End of Programming
Figure 4-3. FLASH Programming Flowchart
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FLASH Memory
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE:
When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set,
the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register.
The content of this register determine the starting location of the
protected range within the FLASH memory.
Address:
$FE09
Bit 7
6
5
4
3
2
1
Bit 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 4-4. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0
BPR[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0]
are logic 0’s.
16-bit memory address
Start address of FLASH block protect
0 0 0 0 0 0 0 0 0
BPR[7:1]
Figure 4-5. FLASH Block Protect Start Address
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Freescale Semiconductor
FLASH Memory
ROM-Resident Routines
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be X000, X200, X400,
X600, X800, XA00, XC00, or XE00 within the FLASH memory.
Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range
$00 to $DC
The entire FLASH memory is protected.
$DE (1101 1110)
$DE00 (1101 1110 0000 0000)
$E0 (1110 0000)
$E000 (1110 0000 0000 0000)
$E2 (1110 0010)
$E200 (1110 0010 0000 0000)
$E4 (1110 0100)
$E400 (1110 0100 0000 0000)
and so on...
$FE
$FFE0–$FFFF (User vectors)
$FF
The entire FLASH memory is not protected.
Note:
The end address of the protected range is always $FFFF.
4.9 ROM-Resident Routines
ROM-resident routines can be called by a program running in user mode
or in monitor mode (see Section 10. Monitor ROM (MON)) for FLASH
programming, erasing, and verifying. The range of the FLASH memory
must be unprotected (see 4.8 FLASH Protection) before calling the
erase or programming routine.
Table 4-1. ROM-Resident Routines
Routine
Name
Call Address
VERIFY
$FC03
FLASH verify routine
ERASE
$FC06
FLASH mass erase routine
PROGRAM
$FC09
FLASH program routine
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Routine Function
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FLASH Memory
4.9.1 Variables
The ROM-resident routines use three variables: CTRLBYT, CPUSPD
and LADDR; and one data buffer. The minimum size of the data buffer
is one byte and the maximum size is 64 bytes.
CPUSPD must be set before calling the ERASE or PROGRAM routine,
and should be set to four times the value of the CPU internal bus speed
in MHz. For example: for CPU speed of 3MHz, CPUSPD should be set
to 12.
Table 4-2. ROM-Resident Routine Variables
Variable
Address
Description
CTRLBYT
$0048
Control byte for setting mass erase.
CPUSPD
$0049
Timing adjustment for different CPU
speeds.
LADDR
$004A–$004B
Last FLASH address to be programmed.
DATABUF
$004C–$008B
Data buffer for programming and verifying.
4.9.2 ERASE Routine
The ERASE routine erases the entire FLASH memory. The routine does
not check for a blank range before or after erase.
Table 4-3. ERASE Routine
Technical Data
62
Routine
ERASE
Calling Address
$FC06
Stack Use
5 Bytes
Input
CPUSPD — CPU speed
HX —
Contains any address in the range to be
erased
CTRLBYT — Mass erase
Mass erase if bit 6 = 1
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FLASH Memory
ROM-Resident Routines
4.9.3 PROGRAM Routine
The PROGRAM routine programs a range of addresses in FLASH
memory, which does not have to be on page boundaries, either at the
begin or end address.
Table 4-4. PROGRAM Routine
Routine
PROGRAM
Calling Address
$FC09
Stack Use
7 Bytes
Input
CPUSPD —
HX —
LADDR —
DATABUF —
CPU speed
FLASH start address to be programmed
FLASH end address to be programmed
Contains the data to be programmed
4.9.4 VERIFY Routine
The VERIFY routine reads and verifies a range of FLASH memory.
Table 4-5. VERIFY Routine
Routine
VERIFY
Calling Address
$FC03
Stack Use
6 Bytes
Input
HX —
FLASH start address to be verified
LADDR — FLASH end address to be verified
DATABUF — Contains the data to be verified
Output
C Bit —
C bit is set if verify passes
DATABUF — Contains the data in the range of the
FLASH memory
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FLASH Memory
Technical Data
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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.2 Introduction
This section describes the configuration register (CONFIG). This writeonce-after-reset register controls the following options:
•
USB reset
•
Low voltage inhibit
•
Stop mode recovery time (2048 or 4096 OSCXCLK cycles)
•
COP timeout period (218 – 24 or 213 – 24 OSCXCLK cycles)
•
STOP instruction
•
Computer operating properly module (COP)
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Configuration Register (CONFIG)
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65
Configuration Register (CONFIG)
5.3 Functional Description
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. Bit-5 and
bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared
during any reset. Since the various options affect the operation of the
MCU, it is recommended that this register be written immediately after
reset. The configuration register is located at $001F. The configuration
register may be read at any time.
Address:
Read:
$001F
Bit 7
6
0
0
5
4
3
2
1
Bit 0
URSTD
LVID
SSREC
COPRS
STOP
COPD
0*
0*
0
0
0
0
Write:
Reset:
0
0
= Unimplemented
* URSTD and LVID bits are reset by POR or LVI reset only.
Figure 5-1. Configuration Register (CONFIG)
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU.
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI circuit
1 = Disable LVI circuit
0 = Enable LVI circuit
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
2048×OSCXCLK cycles instead of a 4096×OSCXCLK cycle delay.
1 = Stop mode recovery after 2048×OSCXCLK cycles
0 = Stop mode recovery after 4096×OSCXCLK cycles
Technical Data
66
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Configuration Register (CONFIG)
Freescale Semiconductor
Configuration Register (CONFIG)
Functional Description
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. (See
Section 15. Computer Operating Properly (COP).)
1 = COP timeout period = (213 – 24)×OSCXCLK cycles
0 = COP timeout period = (218 – 24)×OSCXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 15. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
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Technical Data
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Configuration Register (CONFIG)
Technical Data
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Configuration Register (CONFIG)
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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.7
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.9
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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Central Processor Unit (CPU)
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
6.3 Features
Technical Data
70
•
Object code fully upward-compatible with M68HC05 Family
•
16-bit stack pointer with stack manipulation instructions
•
16-bit index register with x-register manipulation instructions
•
3-MHz CPU internal bus frequency
•
64-Kbyte program/data memory space
•
16 addressing modes
•
Memory-to-memory data moves without using accumulator
•
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•
Enhanced binary-coded decimal (BCD) data handling
•
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64-Kbytes
•
Low-power stop and wait modes
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Central Processor Unit (CPU)
CPU Registers
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
0
7
ACCUMULATOR (A)
0
15
H
X
INDEX REGISTER (H:X)
15
0
STACK POINTER (SP)
15
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
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Central Processor Unit (CPU)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 6-4. Stack Pointer (SP)
Technical Data
72
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Central Processor Unit (CPU)
CPU Registers
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
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Central Processor Unit (CPU)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Technical Data
74
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Central Processor Unit (CPU)
CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE:
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
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Central Processor Unit (CPU)
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
6.6.1 Wait Mode
The WAIT instruction:
Technical Data
76
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
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CPU During Break Interrupts
6.6.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
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Central Processor Unit (CPU)
6.8 Instruction Set Summary
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
A ← (A) + (M) + (C)
Add with Carry
IMM
DIR
EXT
IX2
R R – R R R
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
R R – R R R
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
A7
ii
2
– – – – – – IMM
AF
ii
2
IMM
DIR
EXT
IX2
0 – – R R –
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
DIR
INH
INH
R – – R R R
IX1
IX
SP1
38
48
58
68
78
9E68
dd
DIR
INH
INH
R – – R R R
IX1
IX
SP1
37
47
57
67
77
9E67
dd
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
A ← (A) & (M)
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Technical Data
78
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
0
b7
b0
C
Arithmetic Shift Right
b7
b0
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
A ← (A) + (M)
ff
ee ff
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 1 of 9)
ff
ee ff
ff
ff
ff
ff
4
1
1
4
3
5
4
1
1
4
3
5
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Central Processor Unit (CPU)
Instruction Set Summary
Effect on
CCR
V H I N Z C
BCC rel
PC ← (PC) + 2 + rel ? (C) = 0
Branch if Carry Bit Clear
Mn ← 0
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 2 of 9)
– – – – – – REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – –
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
3
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
(A) & (M)
IMM
DIR
EXT
IX2
0 – – R R –
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
– – – – – – REL
93
rr
3
BLO rel
Branch if Lower (Same as BCS)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BLS rel
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
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Central Processor Unit (CPU)
Technical Data
79
Central Processor Unit (CPU)
Effect on
CCR
V H I N Z C
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 3 of 9)
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – R
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – R
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – –
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
– – – – – – REL
AD
rr
4
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
BSR rel
Set Bit n in M
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
DIR
PC ← (PC) + 3 + rel ? (A) – (M) = $00
IMM
PC ← (PC) + 3 + rel ? (A) – (M) = $00
IMM
PC ← (PC) + 3 + rel ? (X) – (M) = $00
– – – – – –
IX1+
PC ← (PC) + 3 + rel ? (A) – (M) = $00
IX+
PC ← (PC) + 2 + rel ? (A) – (M) = $00
SP1
PC ← (PC) + 4 + rel ? (A) – (M) = $00
31
41
51
61
71
9E61
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
Technical Data
80
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Central Processor Unit (CPU)
Freescale Semiconductor
Central Processor Unit (CPU)
Instruction Set Summary
Effect on
CCR
V H I N Z C
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Clear
Compare A with M
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
(A) – (M)
IMM
DIR
EXT
IX2
R – – R R R
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
0 – – R R 1
IX1
IX
SP1
33
43
53
63
73
9E63
dd
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
ff
ff
ff
ee ff
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 4 of 9)
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
ff
4
1
1
4
3
5
65
75
ii ii+1
dd
3
4
IMM
DIR
EXT
IX2
R – – R R R
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – R R R INH
72
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
DIR
INH
– – – – – – INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
R – – R R –
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
4
1
1
4
3
5
A ← (H:A)/(X)
H ← Remainder
– – – – R R INH
52
(H:X) – (M:M + 1)
(X) – (M)
(A)10
R – – R R R
IMM
DIR
ff
ff
ee ff
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
DBNZ opr,rel
DBNZA rel
Decrement and Branch if Not Zero
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Central Processor Unit (CPU)
ff
ff
7
Technical Data
81
Central Processor Unit (CPU)
V H I N Z C
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDHX #opr
LDHX opr
Load H:X from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
Technical Data
82
ii
dd
hh ll
ee ff
ff
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
R – – R R –
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
PC ← Jump Address
DIR
EXT
– – – – – – IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A ← (M)
IMM
DIR
EXT
IX2
0 – – R R –
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ii jj
dd
3
4
2
3
4
4
3
2
4
5
A ← (A ⊕ M)
Jump
Load A from M
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
A8
B8
C8
D8
E8
F8
9EE8
9ED8
Increment
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
H:X ← (M:M + 1)
0 – – R R –
X ← (M)
Load X from M
Logical Shift Left
(Same as ASL)
2
3
4
4
3
2
4
5
IMM
DIR
EXT
IX2
0 – – R R –
IX1
IX
SP1
SP2
Exclusive OR M with A
Jump to Subroutine
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 5 of 9)
C
0
b7
b0
IMM
DIR
45
55
ff
ee ff
ff
ff
IMM
DIR
EXT
IX2
0 – – R R –
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
R – – R R R
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ee ff
ff
ff
4
1
1
4
3
5
4
1
1
4
3
5
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Central Processor Unit (CPU)
Freescale Semiconductor
Central Processor Unit (CPU)
Instruction Set Summary
V H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right
DIR
INH
INH
R – – 0 R R
IX1
IX
SP1
34
44
54
64
74
9E64
DD
DIX+
0 – – R R –
IMD
IX+D
4E
5E
6E
7E
X:A ← (X) × (A)
– 0 – – – 0 INH
42
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
R – – R R R
IX1
IX
SP1
30
40
50
60
70
9E60
0
C
b7
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
b0
(M)Destination ← (M)Source
H:X ← (H:X) + 1 (IX+D, DIX+)
dd
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 6 of 9)
ff
4
1
1
4
3
5
dd dd
dd
ii dd
dd
5
4
4
4
ff
5
dd
4
1
1
4
3
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
NOP
No Operation
None
– – – – – – INH
9D
1
NSA
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
3
A ← (A) | (M)
IMM
DIR
EXT
IX2
0 – – R R –
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
88
2
C
DIR
INH
INH
R – – R R R
IX1
IX
SP1
39
49
59
69
79
9E69
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Central Processor Unit (CPU)
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
Technical Data
83
Central Processor Unit (CPU)
V H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
RTI
Return from Interrupt
RTS
Return from Subroutine
dd
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 7 of 9)
4
1
1
4
3
5
DIR
INH
INH
R – – R R R
IX1
IX
SP1
36
46
56
66
76
9E66
SP ← $FF
– – – – – – INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
R R R R R R INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
A ← (A) – (M) – (C)
IMM
DIR
EXT
IX2
R – – R R R
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
C
b7
b0
ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
C←1
– – – – – 1 INH
99
1
SEI
Set Interrupt Mask
I←1
– – 1 – – – INH
9B
2
M ← (A)
DIR
EXT
IX2
0 – – R R – IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
(M:M + 1) ← (H:X)
0 – – R R – DIR
35
I ← 0; Stop Oscillator
– – 0 – – – INH
8E
M ← (X)
DIR
EXT
IX2
0 – – R R – IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Technical Data
84
Store X in M
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ff
ee ff
3
4
4
3
2
4
5
dd
4
dd
hh ll
ee ff
ff
1
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Central Processor Unit (CPU)
Freescale Semiconductor
Central Processor Unit (CPU)
Instruction Set Summary
Effect on
CCR
V H I N Z C
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Subtract
A ← (A) – (M)
ii
dd
hh ll
ee ff
ff
Cycles
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 8 of 9)
2
3
4
4
3
2
4
5
IMM
DIR
EXT
IX2
R – – R R R
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
– – 1 – – – INH
83
9
ff
ee ff
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR ← (A)
R R R R R R INH
84
2
TAX
Transfer A to X
X ← (A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A ← (CCR)
– – – – – – INH
85
1
(A) – $00 or (X) – $00 or (M) – $00
DIR
INH
INH
0 – – R R –
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Central Processor Unit (CPU)
dd
ff
ff
3
1
1
3
2
4
Technical Data
85
Central Processor Unit (CPU)
V H I N Z C
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
R
—
Cycles
Effect on
CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 6-1. Instruction Set Summary (Sheet 9 of 9)
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
6.9 Opcode Map
See Table 6-2.
Technical Data
86
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Central Processor Unit (CPU)
Freescale Semiconductor
Central Processor Unit (CPU)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Table 6-2. Opcode Map
Bit Manipulation
DIR
DIR
MSB
Branch
REL
DIR
INH
3
4
0
1
2
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
Read-Modify-Write
INH
IX1
5
6
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
SP1
IX
9E6
7
Control
INH
INH
8
9
Register/Memory
IX2
SP2
IMM
DIR
EXT
A
B
C
D
9ED
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
3 IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
E
9EE
F
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
E
F
87
Technical Data
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
MSB
0
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
0
Cycles
5
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
Central Processor Unit (CPU)
Opcode Map
D
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
Central Processor Unit (CPU)
Technical Data
88
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Central Processor Unit (CPU)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 7. Oscillator (OSC)
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.3
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
7.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.4.1
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 91
7.4.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 91
7.4.3
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 91
7.4.4
External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 91
7.4.5
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.6
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2 Introduction
The oscillator circuit is designed for use with crystals or ceramic
resonators. The oscillator circuit generates the crystal clock signal. The
crystal oscillator output signal passes through the clock doubler.
OSCXCLK is the output signal of the clock doubler. OSCXCLK is divided
by two before being passed on to the system integration module (SIM)
for bus clock generation.
Figure 7-1 shows the structure of the oscillator. The oscillator requires
various external components.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Oscillator (OSC)
Technical Data
89
Oscillator (OSC)
7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external
components. The crystal oscillator is normally connected in a Pierce
oscillator configuration, as shown in Figure 7-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
•
Crystal, X1
•
Fixed capacitor, C1
•
Tuning capacitor, C2 (can also be a fixed capacitor)
•
Feedback resistor, RB
•
Series resistor, RS (optional)
FROM SIM
TO USB
TO SIM
CLOCK
DOUBLER
OSCXCLK
TO SIM
÷2
OSCOUT
SIMOSCEN
MCU
OSC1
OSC2
RB
RS *
X1
C1
C2
* RS can be 0 (shorted) when used with
higher frequency crystals.
Refer to manufacturer’s data.
Figure 7-1. Oscillator External Connections
Technical Data
90
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Oscillator (OSC)
Freescale Semiconductor
Oscillator (OSC)
I/O Signals
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
7.4 I/O Signals
The following paragraphs describe the oscillator input/output (I/O)
signals.
7.4.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.4.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator.
7.4.4 External Clock Source (OSCXCLK)
The crystal oscillator output signal passes through the clock doubler and
OSCXCLK is the output signal of the clock doubler. OSCXCLK runs at
twice the speed of the crystal (fXCLK). Figure 7-1 shows only the logical
relation of OSCXCLK to OSC1 and OSC2 and may not represent the
actual circuitry. The duty cycle of OSCXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and
amplitude of OSCXCLK can be unstable at startup.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Oscillator (OSC)
Technical Data
91
Oscillator (OSC)
7.4.5 Oscillator Out (OSCOUT)
The clock driven to the SIM is OSCXCLK. This signal is driven to the SIM
for generation of the bus clocks used by the CPU and other modules on
the MCU. OSCOUT will be divided again in the SIM and results in the
internal bus frequency being one forth of the OSCXCLK frequency or
one half of the crystal frequency.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
7.5.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. OSCXCLK
continues to drive to the SIM module.
7.5.2 Stop Mode
The STOP instruction disables the OSCXCLK output.
7.6 Oscillator During Break Mode
The oscillator continues to drive OSCXCLK when the chip enters the
break state.
Technical Data
92
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Oscillator (OSC)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 8. System Integration Module (SIM)
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 96
8.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3.2
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 97
8.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 97
8.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 97
8.4.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 99
8.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . . 101
8.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 102
8.4.2.6
Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . 102
8.4.2.7
Registers Values After Different Resets. . . . . . . . . . . . . 102
8.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 103
8.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 104
8.5.3
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . 104
8.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6.2
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.4
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 110
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
93
System Integration Module (SIM)
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.8.1
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.8.2
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.8.3
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116
8.2 Introduction
This section describes the system integration module (SIM), which
supports up to 8 external and/or internal interrupts. Together with the
CPU, the SIM controls all MCU activities. The SIM is a system state
controller that coordinates CPU and exception timing. A block diagram
of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM
I/O registers. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
Master reset control, including power-on reset (POR) and COP
timeout
•
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
Technical Data
94
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
System Integration Module (SIM)
Freescale Semiconductor
System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
OSCXCLK (FROM CLOCK DOUBLER)
OSCOUT (FROM CLOCK DOUBLER)
÷2
VDD
INTERNAL
PULL-UP
RESET
PIN LOGIC
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
USB RESET (FROM USB MODULE)
RESET
INTERRUPT SOURCES
INTERRUPT CONTROL
AND PRIORITY DECODE
CPU INTERFACE
Figure 8-1. SIM Block Diagram
Table 8-1. SIM Module Signal Name Conventions
Signal Name
Description
OSCXCLK
Clock doubler output which has twice the frequency of OSC1 from the oscillator
OSCOUT
The OSCXCLK frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks.
(Bus clock = OSCXCLK ÷ 4 = fOSC ÷ 2)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
95
System Integration Module (SIM)
Addr.
$FE00
Register Name
Break Status Register Read:
(BSR)
Write:
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Reset:
1
SBSW
See note
Bit 0
R
0
Note: Writing a logic 0 clears SBSW.
$FE01
Reset Status Register Read:
(RSR)
Write:
POR:
$FE02
Reserved Read:
Write:
$FE03
Break Flag Control Read:
Register
Write:
(BFCR)
Reset:
$FE04 Interrupt Status Register 1 Read:
(INT1)
Write:
Reset:
POR
PIN
COP
ILOP
ILAD
USB
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
Figure 8-2. SIM I/O Register Summary
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 8-3.
FROM CLOCK
DOUBLER
OSCXCLK
FROM CLOCK
DOUBLER
OSCOUT
SIM COUNTER
BUS CLOCK
GENERATORS
÷2
SIM
Figure 8-3. SIM Clock Signals
Technical Data
96
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
System Integration Module (SIM)
Freescale Semiconductor
System Integration Module (SIM)
Reset and System Initialization
8.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
divided by two.
8.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 OSCXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
8.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 2048 OSCXCLK cycles. (See 8.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
8.4 Reset and System Initialization
The MCU has these reset sources:
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly module (COP)
•
Illegal opcode
•
Illegal address
•
Universal serial bus module (USB)
•
Low-voltage inhibit module (LVI)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
97
System Integration Module (SIM)
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 8.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See 8.8 SIM Registers.)
8.4.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 OSCXCLK cycles, assuming that neither the POR nor the LVI was the
source of the reset. See Table 8-2 for details. Figure 8-4 shows the
relative timing.
Table 8-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
OSCOUT
RST
IAB
PC
VECT H
VECT L
Figure 8-4. External Reset Timing
Technical Data
98
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
System Integration Module (SIM)
Freescale Semiconductor
System Integration Module (SIM)
Reset and System Initialization
8.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 OSCXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. (See Figure
8-5.) An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, the USB module or POR. (See Figure 8-6 .
Sources of Internal Reset.)
NOTE:
For LVI or POR resets, the SIM cycles through 4096 OSCXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in
Figure 8-5.
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
OSCXCLK
IAB
VECTOR HIGH
Figure 8-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
USB
INTERNAL RESET
Figure 8-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
99
System Integration Module (SIM)
8.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
•
A POR pulse is generated.
•
The internal reset signal is asserted.
•
The SIM enables the oscillator to drive OSCXCLK.
•
Internal clocks to the CPU and modules are held inactive for 4096
OSCXCLK cycles to allow stabilization of the oscillator.
•
The RST pin is driven low during the oscillator stabilization time.
•
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
OSCXCLK
OSCOUT
RST
$FFFE
IAB
$FFFF
Figure 8-7. POR Recovery
Technical Data
100
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
System Integration Module (SIM)
Freescale Semiconductor
System Integration Module (SIM)
Reset and System Initialization
8.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every 212 – 24 OSCXCLK cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at
VDD + VHI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
VDD + VHI on the RST pin disables the COP module.
8.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
8.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
101
System Integration Module (SIM)
8.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the LVI reset voltage, VTRIP. The LVI bit in the
reset status register (RSR) is set, and the external reset pin (RST) is held
low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four
OSCXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
8.4.2.6 Universal Serial Bus Reset
The USB module will detect a reset signaled on the bus by the presence
of an extended SE0 at the USB data pins of a device. The MCU seeing
a single-ended 0 on its USB data inputs for more than 2.5 µs treats that
signal as a reset. After the reset is removed, the device will be in the
attached, but not yet addressed or configured, state (refer to Section 9.1
USB Devices of the Universal Serial Bus Specification Rev. 1.1). The
device must be able to accept the device address via a SET_ADDRESS
command (refer to Section 9.4 of the Universal Serial Bus Specification
Rev. 1.1) no later than 10ms after the reset is removed.
USB reset can be disabled to generate an internal reset, instead, a USB
interrupt can be generated. (See Section 5. Configuration Register
(CONFIG).)
NOTE:
USB reset is disabled when the USB module is disabled by clearing the
USBEN bit of the USB Address Register (UADDR).
8.4.2.7 Registers Values After Different Resets
Some registers are reset by POR or LVI reset only. Table 8-3 shows the
registers or register bits which are unaffected by normal resets.
Technical Data
102
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
System Integration Module (SIM)
Freescale Semiconductor
System Integration Module (SIM)
SIM Counter
Table 8-3. Registers not Affected by Normal Reset
Bits
Registers
After Reset
(except POR or
LVI)
After POR or LVI
URSTD, LVIDIS
CONFIG
Unaffected
0
USBEN
UADDR
Unaffected
0
PULLEN
UCR3
Unaffected
0
All
USR0, USR1
Unaffected
Indeterminate
All
UE0D0–UE0D7
Unaffected
Indeterminate
All
UE1D0–UE1D7
Unaffected
Indeterminate
All
UE2D0–UE2D7
Unaffected
Indeterminate
All
PTA, PTB, PTC,
PTD, and PTE
Unaffected
Indeterminate
DDRA7
DDRA
Unaffected
0
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescalar for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of OSCXCLK.
8.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
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8.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register (CONFIG). If the SSREC bit is a logic 1, then the
stop recovery is reduced from the normal delay of 4096 OSCXCLK
cycles down to 2048 OSCXCLK cycles. This is ideal for applications
using canned oscillators that do not require long startup times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared in the configuration register (CONFIG).
8.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 8.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
8.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
8.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
8.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 8-8 flow charts the handling of
system interrupts.
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Exception Control
FROM RESET
BREAK
INTERRUPT
?
NO
YES
YES
BITSET?
SET?
IIBIT
NO
IRQ
INTERRUPT
?
NO
YES
USB
INTERRUPT
?
NO
YES
OTHER
INTERRUPTS
?
NO
YES
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
YES
NO
RTI
INSTRUCTION
?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 8-8. Interrupt Processing
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Interrupts are latched and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 8-9 shows interrupt entry timing. Figure
8-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
DUMMY
SP – 1
SP – 2
PC – 1[7:0] PC – 1[15:8]
SP – 3
X
SP – 4
A
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 8-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
IDB
SP – 4
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC –1 [15:8] PC – 1[7:0]
PC + 1
OPCODE
OPERAND
R/W
Figure 8-10. Interrupt Recovery
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System Integration Module (SIM)
Exception Control
8.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 8-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 8-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
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8.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC–1, as a hardware interrupt does.
8.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 8-4 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 8-4. Interrupt Sources
Source
Mask(1)
Flags
SWI Instruction
INT Register Flag
Priority(2)
Vector Address
—
0
$FFFC–$FFFD
IF2
1
$FFFA–$FFFB
USB Reset Interrupt
RSTF
URSTD
USB Endpoint 0 Transmit
TXD0F
TXD0IE
USB Endpoint 0 Receive
RXD0F
RXD0IE
USB Endpoint 1 Transmit
TXD1F
TXD1IE
USB Endpoint 2 Transmit
TXD2F
TXD2IE
USB Endpoint 2 Receive
RXD2F
RXD2IE
USB End of Packet
EOPF
EOPIE
RESUMF
—
IRQF
PTE4IF
IMASK
IF1
2
$FFF8–$FFF9
TIM Channel 0
CH0F
CH0IE
IF3
3
$FFF6–$FFF7
TIM Channel 1
CH1F
CH1IE
IF4
4
$FFF4–$FFF5
TOF
TOIE
IF5
5
$FFF2–$FFF3
KEYF
IMASKK
IF6
6
$FFF0–$FFF1
USB Resume Interrupt
IRQ Interrupt (IRQ, PTE4)
TIM Overflow
Keyboard Interrupt
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
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Exception Control
8.6.2.1 Interrupt Status Register 1
Address:
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 8-12. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the
sources shown in Table 8-4.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
8.6.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
8.6.4 Break Interrupts
The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. (See
Section 17. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
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8.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
8.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
here. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
8.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 8-13 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
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Low-Power Modes
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
WAIT ADDR
IAB
WAIT ADDR + 1
PREVIOUS DATA
IDB
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 8-13. Wait Mode Entry Timing
Figure 8-14 and Figure 8-15 show the timing for WAIT recovery.
IAB
IDB
$6E0B
$A6
$A6
$6E0C
$A6
$01
$00FF
$00FE
$0B
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 8-14. Wait Recovery from Interrupt or Break
32
CYCLES
$6E0B
IAB
IDB
$A6
$A6
32
CYCLES
RST VCT H RST VCT L
$A6
RST
OSCXCLK
Figure 8-15. Wait Recovery from Internal Reset
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8.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
OSCXCLK cycles down to 2048. This is ideal for applications using
canned oscillators that do not require long startup times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the break status register (BSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 8-16 shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 8-16. Stop Mode Entry Timing
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System Integration Module (SIM)
SIM Registers
STOP RECOVERY PERIOD
OSCXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 8-17. Stop Mode Recovery from Interrupt or Break
8.8 SIM Registers
The SIM has two break registers and one reset register.
8.8.1 Break Status Register
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
1
Bit 0
SBSW
R
Write:
Note 1
Reset:
0
Note 1. Writing a logic 0 clears SBSW.
R
= Reserved
Figure 8-18. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
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SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it.
The following code is an example of this. Writing 0 to the SBSW bit
clears it.
This code works if the H register has been pushed onto the stack in the break service
routine software. This code should be executed at the end of the break service routine
software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode was exited
; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
8.8.2 Reset Status Register
This register contains seven flags that show the source of the last reset.
All flag bits are cleared automatically following a read of the register. The
register is initialized on power-up as shown with the POR bit set and all
other bits cleared. However, during a POR or any other internal reset,
the RST pin is pulled low. After the pin is released, it will be sampled 32
XCLK cycles later. If the pin is not above a VIH at that time, then the PIN
bit in the RSR may be set in addition to whatever other bits are set.
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System Integration Module (SIM)
SIM Registers
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
USB
LVI
0
1
0
0
0
0
0
0
0
Write:
POR:
= Unimplemented
Figure 8-19. Reset Status Register (RSR)
POR — Power-On Reset Bit
1 = A POR has occurred
0 = Read of RSR
PIN — External Reset Bit
1 = An external reset has occurred since the last read of the RSR
0 = Read of RSR
COP — Computer Operating Properly Reset Bit
1 = A COP reset has occurred since the last read of the RSR
0 = POR or read of RSR
ILOP — Illegal Opcode Reset Bit
An illegal opcode reset has occurred since the last read of the RSR
0 = POR or read of RSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = An illegal address reset has occurred since the last read of the
RSR
0 = POR or read of RSR
USB — Universal Serial Bus Reset Bit
1 = Last reset caused by the USB module
0 = POR or read of RSR
LVI — Low voltage inhibit Reset Bit
1 = A LVI reset has occurred since the last read of PSR
0 = POR or read of RSR
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8.8.3 Break Flag Control Register
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
Write:
POR:
0
R
= Reserved
Figure 8-20. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 9. Universal Serial Bus Module (USB)
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.5.1
USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.5.1.1
Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.5.1.2
Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.5.1.3
Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.5.1.4
Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.5.1.5
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 128
9.5.1.6
End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.2
Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.5.3
Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.5.4
Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.5.4.1
Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.5.4.2
USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.3
Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.5
Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.6
Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.7
Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.1
Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2
USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2.1
Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 134
9.7.2.2
Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 134
9.7.2.3
Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.2.4
Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.2.5
Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . 136
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9.7.3
USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.8.1
USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.8.2
USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.8.3
USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.8.4
USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.8.5
USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.8.6
USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.8.7
USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9.8.8
USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.8.9
USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
9.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
9.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 154
9.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 155
9.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 156
9.9
USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.9.1
USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . . 157
9.9.1.1
Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . . 158
9.9.1.2
Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . 160
9.9.1.3
Transmit Endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.9.1.4
Transmit Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.1.5
Receive Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.2
Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.9.3
End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.2 Introduction
This section describes the universal serial bus (USB) module. The USB
module is designed to serve as a low-speed (LS) USB device per the
Universal Serial Bus Specification Rev 1.1. Control and interrupt data
transfers are supported. Endpoint 0 functions as a transmit/receive
control endpoint; endpoint 1 functions as interrupt transmit endpoint;
endpoint 2 functions as interrupt transmit or receive endpoint.
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
Features
9.3 Features
Features of the USB module include:
•
Full Universal Serial Bus Specification 1.1 low-speed functions
•
1.5 Mbps data rate
•
On-chip 3.3V regulator
•
Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer
•
Endpoint 1 with 8-byte transmit buffer
•
Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer
•
USB data control logic:
– Control endpoint 0 and interrupt endpoints 1 and 2
– Packet decoding/generation
– CRC generation and checking
– NRZI (Non-Return-to Zero Inserted) encoding/decoding
– Bit-stuffing
•
USB reset options:
– Internal MCU reset generation
– CPU interrupt request generation
•
Suspend and resume operations, with remote wakeup support
•
USB-generated interrupts:
– Transaction interrupt driven
– Resume interrupt
– End-of-packet interrupt
– USB reset
•
STALL, NAK, and ACK handshake generation
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
9.4 Pin Name Conventions
The USB share two I/O pins with two port E I/O pins. The full name of the
USB I/O pin is listed in Table 9-1. The generic pin name appear in the
text that follows.
Table 9-1. USB Module Pin Name Conventions
Addr.
$0018
$0019
$001A
Register Name
USB Generic Pin Names:
D+
D–
Full USB Pin Names:
PTE3/D+
PTE4/D–
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
RSTFR
TXD2FR
RXD2FR
0
0
0
0
0
0
0
T2SEQ
STALL2
TX2E
RX2E
TP2SIZ3
TP2SIZ2
TP2SIZ1
TP2SIZ0
0
0
0
0
0
0
0
0
TX1ST
0
OSTALL0
ISTALL0
Read:
0
USB Interrupt Register 2
Write: EOPFR
(UIR2)
Reset:
0
Read:
USB Control Register 2
Write:
(UCR2)
Reset:
Read:
USB Control Register 3
Write:
(UCR3)
Reset:
TX1STR
TXD1FR RESUMFR TXD0FR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: UE0R07
USB Endpoint 0 Data
Register 0 Write: UE0T07
(UE0D0)
Reset:
UE0R06
UE0R05
UE0T06
UE0T05
Read: UE0R17
USB Endpoint 0 Data
Register 1 Write: UE0T17
(UE0D1)
Reset:
UE0R16
UE0R15
UE0R14
UE0T16
UE0T15
UE0T14
RXD0FR
PULLEN ENABLE2 ENABLE1
0*
0
0
FUSBO
FDP
FDM
0
0
0
0
UE0R04
UE0R03
UE0R02
UE0R01
UE0R00
UE0T04
UE0T03
UE0T02
UE0T01
UE0T00
UE0R13
UE0R12
UE0R11
UE0R10
UE0T13
UE0T12
UE0T11
UE0T10
* PULLEN bit is reset by POR or LVI reset only.
$001B
$0020
$0021
Read:
USB Control Register 4
Write:
(UCR4)
Reset:
Unaffected by reset
Unaffected by reset
= Unimplemented
U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 1 of 4)
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Freescale Semiconductor
Universal Serial Bus Module (USB)
Pin Name Conventions
Addr.
Register Name
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
Bit 7
6
5
4
3
2
1
Bit 0
Read: UE0R27
USB Endpoint 0 Data
Register 2 Write: UE0T27
(UE0D2)
Reset:
UE0R26
UE0R25
UE0R24
UE0R23
UE0R22
UE0R21
UE0R20
UE0T26
UE0T25
UE0T24
UE0T23
UE0T22
UE0T21
UE0T20
Read: UE0R37
USB Endpoint 0 Data
Register 3 Write: UE0T37
(UE0D3)
Reset:
UE0R36
UE0R35
UE0R34
UE0R33
UE0R32
UE0R31
UE0R30
UE0T36
UE0T35
UE0T34
UE0T33
UE0T32
UE0T31
UE0T30
Read: UE0R47
USB Endpoint 0 Data
Register 4 Write: UE0T47
(UE0D4)
Reset:
UE0R46
UE0R45
UE0R44
UE0R43
UE0R42
UE0R41
UE0R40
UE0T46
UE0T45
UE0T44
UE0T43
UE0T42
UE0T41
UE0T40
Read: UE0R57
USB Endpoint 0 Data
Register 5 Write: UE0T57
(UE0D5)
Reset:
UE0R56
UE0R55
UE0R54
UE0R53
UE0R52
UE0R51
UE0R50
UE0T56
UE0T55
UE0T54
UE0T53
UE0T52
UE0T51
UE0T50
Read: UE0R67
USB Endpoint 0 Data
Register 6 Write: UE0T67
(UE0D6)
Reset:
UE0R66
UE0R65
UE0R64
UE0R63
UE0R62
UE0R61
UE0R60
UE0T66
UE0T65
UE0T64
UE0T63
UE0T62
UE0T61
UE0T60
Read: UE0R77
USB Endpoint 0 Data
Register 7 Write: UE0T77
(UE0D7)
Reset:
UE0R76
UE0R75
UE0R74
UE0R73
UE0R72
UE0R71
UE0R70
UE0T76
UE0T75
UE0T74
UE0T73
UE0T72
UE0T71
UE0T70
UE1T02
UE1T01
UE1T00
UE1T12
UE1T11
UE1T10
UE1T22
UE1T21
UE1T20
UE1T32
UE1T31
UE1T30
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Read:
USB Endpoint 1 Data
Register 0 Write: UE1T07
(UE1D0)
Reset:
UE1T06
Read:
USB Endpoint 1 Data
Register 1 Write: UE1T17
(UE1D1)
Reset:
UE1T16
Read:
USB Endpoint 1 Data
Register 2 Write: UE1T27
(UE1D2)
Reset:
UE1T26
Read:
USB Endpoint 1 Data
Register 3 Write: UE1T37
(UE1D3)
Reset:
UE1T36
UE1T05
UE1T04
UE1T03
Unaffected by reset
UE1T15
UE1T14
UE1T13
Unaffected by reset
UE1T25
UE1T24
UE1T23
Unaffected by reset
UE1T35
UE1T34
UE1T33
Unaffected by reset
= Unimplemented
U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 2 of 4)
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Universal Serial Bus Module (USB)
Technical Data
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Universal Serial Bus Module (USB)
Addr.
Register Name
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
Bit 7
6
5
4
3
2
1
Bit 0
Read:
USB Endpoint 1 Data
Register 4 Write: UE1T47
(UE1D4)
Reset:
UE1T46
UE1T45
UE1T44
UE1T43
UE1T42
UE1T41
UE1T40
Read:
USB Endpoint 1 Data
Register5 Write: UE1T57
(UE1D5)
Reset:
UE1T56
UE1T52
UE1T51
UE1T50
Read:
USB Endpoint 1 Data
Register 6 Write: UE1T67
(UE1D6)
Reset:
UE1T66
UE1T62
UE1T61
UE1T60
Read:
USB Endpoint 1 Data
Register 7 Write: UE1T77
(UE1D7)
Reset:
UE1T76
UE1T72
UE1T71
UE1T70
Unaffected by reset
UE1T55
UE1T54
UE1T53
Unaffected by reset
UE1T65
UE1T64
UE1T63
Unaffected by reset
UE1T75
UE1T74
UE1T73
Unaffected by reset
Read: UE2R07
USB Endpoint 2 Data
Register 0 Write: UE2T07
(UE2D0)
Reset:
UE2R06
UE2R05
UE2R04
UE2R03
UE2R02
UE2R01
UE2R00
UE2T06
UE2T05
UE2T04
UE2T03
UE2T02
UE2T01
UE2T00
Read: UE2R17
USB Endpoint 2 Data
Register 1 Write: UE2T17
(UE2D1)
Reset:
UE2R16
UE2R15
UE2R14
UE2R13
UE2R12
UE2R11
UE2R10
UE2T16
UE2T15
UE2T14
UE2T13
UE2T12
UE2T11
UE2T10
Read: UE2R27
USB Endpoint 2 Data
Register 2 Write: UE2T27
(UE2D2)
Reset:
UE2R26
UE2R25
UE2R24
UE2R23
UE2R22
UE2R21
UE2R20
UE2T26
UE2T25
UE2T24
UE2T23
UE2T22
UE2T21
UE2T20
Read: UE2R37
USB Endpoint 2 Data
Register 3 Write: UE2T37
(UE2D3)
Reset:
UE2R36
UE2R35
UE2R34
UE2R33
UE2R32
UE2R31
UE2R30
UE2T36
UE2T35
UE2T34
UE2T33
UE2T32
UE2T31
UE2T30
Read: UE2R47
USB Endpoint 2 Data
Register 4 Write: UE2T47
(UE2D4)
Reset:
UE2R46
UE2R45
UE2R44
UE2R43
UE2R42
UE2R41
UE2R40
UE2T46
UE2T45
UE2T44
UE2T43
UE2T42
UE2T41
UE2T40
Read: UE2R57
USB Endpoint 2 Data
Register 5 Write: UE2T57
(UE2D5)
Reset:
UE2R56
UE2R55
UE2R54
UE2R53
UE2R52
UE2R51
UE2R50
UE2T56
UE2T55
UE2T54
UE2T53
UE2T52
UE2T51
UE2T50
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
= Unimplemented
U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 3 of 4)
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Freescale Semiconductor
Universal Serial Bus Module (USB)
Pin Name Conventions
Addr.
Register Name
$0036
$0037
$0038
Bit 7
6
5
4
3
2
1
Bit 0
Read: UE2R67
USB Endpoint 2 Data
Register 6 Write: UE2T67
(UE2D6)
Reset:
UE2R66
UE2R65
UE2R64
UE2R63
UE2R62
UE2R61
UE2R60
UE2T66
UE2T65
UE2T64
UE2T63
UE2T62
UE2T61
UE2T60
Read: UE2R77
USB Endpoint 2 Data
Register 7 Write: UE2T77
(UE2D7)
Reset:
UE2R76
UE2R75
UE2R74
UE2R73
UE2R72
UE2R71
UE2R70
UE2T76
UE2T75
UE2T74
UE2T73
UE2T72
UE2T71
UE2T70
USB Address Register Read:
USBEN
(UADDR)
Write:
Unaffected by reset
Unaffected by reset
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
0*
0
0
0
0
0
0
0
EOPIE
SUSPND
TXD2IE
RXD2IE
TXD1IE
TXD0IE
RXD0IE
0
0
0
0
0
0
0
0
EOPF
RSTF
TXD2F
RXD2F
TXD1F
RESUMF
TXD0F
RXD0F
0
0
0
0
0
0
0
0
TX0E
RX0E
TP0SIZ3
TP0SIZ2
TP0SIZ1
TP0SIZ0
0
0
0
0
0
TP1SIZ2
TP1SIZ1
TP1SIZ0
Reset:
* USBEN bit is reset by POR or LVI reset only.
$0039
USB Interrupt Register 0 Read:
(UIR0)
Write:
Reset:
$003A
USB Interrupt Register 1 Read:
(UIR1)
Write:
Reset:
$003B
USB Control Register 0 Read:
(UCR0)
Write:
Reset:
$003C
USB Control Register 1 Read:
(UCR1)
Write:
Reset:
$003D
T0SEQ
0
0
0
0
T1SEQ
STALL1
TX1E
0
0
0
0
0
0
0
0
SETUP
0
0
RP0SIZ3
RP0SIZ2
RP0SIZ1
RP0SIZ0
USB Status Register 0 Read: R0SEQ
(USR0)
Write:
Reset:
$003E
FRESUM TP1SIZ3
Unaffected by reset
USB Status Register 1 Read: R2SEQ
(USR1)
Write:
Reset:
0
U
TXACK
TXNAK
TXSTL
RP2SIZ3
RP2SIZ2
RP2SIZ1
RP2SIZ0
0
0
0
U
U
U
U
= Unimplemented
U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 4 of 4)
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Universal Serial Bus Module (USB)
9.5 Functional Description
Figure 9-2 shows the block diagram of the USB module. The USB
module manages communications between the host and the USB
function. The module is partitioned into three functional blocks. These
blocks consist of a dual-function transceiver, the USB control logic, and
the endpoint registers. The blocks are further detailed later in this section
(see 9.7 Hardware Description).
USB
VPIN
CONTROL
VMIN
LOGIC
TRANSCEIVER
RCV
D+
D–
USB
UPSTREAM
PORT
VPOUT
VMOUT
CPU BUS
USB REGISTERS
Figure 9-2. USB Block Diagram
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
Functional Description
9.5.1 USB Protocol
Figure 9-3 shows the various transaction types supported by the USB
module. The transactions are portrayed as error free. The effect of errors
in the data flow are discussed later.
ENDPOINT 0 TRANSACTIONS:
Control Write
SETUP
DATA0
ACK
OUT
DATA0
OUT
ACK
DATA1
ACK
OUT
DATA0/1
IN
DATA1
ACK
ACK
Control Read
SETUP
DATA0
ACK
IN
DATA0
IN
ACK
DATA1
ACK
IN
DATA0/1
OUT
DATA1
ACK
ACK
No-Data Control
SETUP
DATA0
ACK
IN
ACK
DATA1
ENDPOINTS 1 & 2 TRANSACTIONS:
KEY:
Interrupt
IN
DATA0/1
ACK
Unrelated Bus
Traffic
Host
Generated
Bulk Transmit
IN
DATA0/1
ACK
Device
Generated
Figure 9-3. Supported Transaction Types Per Endpoint
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Universal Serial Bus Module (USB)
Each USB transaction is comprised of a series of packets. The USB
module supports the packet types shown in Figure 9-4. Token packets
are generated by the USB host and decoded by the USB device. Data
and handshake packets are both decoded and generated by the USB
device, depending on the type of transaction.
Token Packet:
IN
OUT
SYNC
PID
PID
SYNC
PID
PID
ADDR
ENDP
CRC5
EOP
CRC16
EOP
SETUP
Data Packet:
DATA0
DATA1
DATA
0 – 8 Bytes
Handshake Packet:
ACK
NAK
SYNC
PID
PID
EOP
STALL
Figure 9-4. Supported USB Packet Types
The following sections detail each segment used to form a complete
USB transaction.
9.5.1.1 Sync Pattern
The NRZI bit pattern shown in Figure 9-5 is used as a synchronization
pattern and is prefixed to each packet. This pattern is equivalent to a
data pattern of seven 0s followed by a 1 ($80).
SYNC PATTERN
NRZI Data
Encoding
Idle
PID0
PID1
Figure 9-5. Sync Pattern
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Freescale Semiconductor
Universal Serial Bus Module (USB)
Functional Description
The start of a packet (SOP) is signaled by the originating port by driving
the D+ and D– lines from the idle state (also referred to as the J state) to
the opposite logic level (also referred to as the K state). This switch in
levels represents the first bit of the sync field. Figure 9-6 shows the data
signaling and voltage levels for the start of packet and the sync pattern.
VOH (min.)
VSE (max)
VSE (min.)
VOL (min.)
VSS
FIRST BIT OF PACKET
BUS IDLE
SOP
END OF SYNC
Figure 9-6. SOP, Sync Signaling, and Voltage Levels
9.5.1.2 Packet Identifier Field
The packet identifier field is an 8-bit number comprised of the 4-bit
packet identification and its complement. The field follows the sync
pattern and determines the direction and type of transaction on the bus.
Table 9-2 shows the packet identifier values for the supported packet
types.
Table 9-2. Supported Packet Identifiers
Packet Identifier Value
Packet Identifier Type
%1001
IN Token
%0001
OUT Token
%1101
SETUP Token
%0011
DATA0 Packet
%1011
DATA1 Packet
%0010
ACK Handshake
%1010
NAK Handshake
%1110
STALL Handshake
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Universal Serial Bus Module (USB)
9.5.1.3 Address Field (ADDR)
The address field is a 7-bit number that is used to select a particular USB
device. This field is compared to the lower seven bits of the UADDR
register to determine if a given transaction is targeting the MCU USB
device.
9.5.1.4 Endpoint Field (ENDP)
The endpoint field is a 4-bit number that is used to select a particular
endpoint within a USB device. For the MCU, this will be a binary number
between 0 and 2 inclusive. Any other value will cause the transaction to
be ignored.
9.5.1.5 Cyclic Redundancy Check (CRC)
Cyclic redundancy checks are used to verify the address and data
stream of a USB transaction. This field is five bits wide for token packets
and 16 bits wide for data packets. CRCs are generated in the transmitter
and sent on the USB data lines after both the endpoint field and the data
field.
9.5.1.6 End-of-Packet (EOP)
The single-ended 0 (SE0) state is used to signal an end-of-packet
(EOP). The single-ended 0 state is indicated by both D+ and D– being
below 0.8V. EOP will be signaled by driving D+ and D– to the
single-ended 0 state for two bit times followed by driving the lines to the
idle state for one bit time. The transition from the single-ended 0 to the
idle state defines the end of the packet. The idle state is asserted for one
bit time and then both the D+ and D– output drivers are placed in their
high-impedance state. The bus termination resistors hold the bus in the
idle state. Figure 9-7 shows the data signaling and voltage levels for an
end-of-packet transaction.
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
Functional Description
LAST BIT OF
PACKET
EOP
STROBE
BUS DRIVEN TO
IDLE STATE
BUS FLOATS
BUS IDLE
VOH (min.)
VSE (max)
VSE (min.)
VOL (min.)
VSS
Figure 9-7. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width
is measured with the same capacitive load used for maximum rise and
fall times and is measured at the same level as the differential signal
crossover points of the data lines.
tPeriod
DATA
CROSSOVER
LEVEL
DIFFERENTIAL
DATA LINES
EOP
WIDTH
Figure 9-8. EOP Width Timing
9.5.2 Reset Signaling
The USB module will detect a reset signaled on the bus by the presence
of an extended SE0 at the USB data pins of a device. The MCU seeing
a single-ended 0 on its USB data inputs for more than 8µs treats that
signal as a reset.
A USB sourced reset will hold the MCU in reset for the duration of the
reset on the USB bus. The USB bit in the reset status register (RSR) will
be set after the internal reset is removed. Refer to 8.8.2 Reset Status
Register for more detail. The MCU’s reset recovery sequence is
detailed in Section 8. System Integration Module (SIM).
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Universal Serial Bus Module (USB)
The reset flag bit (RSTF) in the USB interrupt register 1 (UIR1) also will
be set after the internal reset is removed. Refer to 9.8.3 USB Interrupt
Register 1 for more detail.
After a reset is removed, the device will be in the default, but not yet
addressed or configured state (refer to Section 9.1 USB Device States
of the Universal Serial Bus Specification Rev. 1.1). The device must be
able to accept a device address via a SET_ADDRESS command (refer
to Section 9.4 Standard Device Request in the Universal Serial Bus
Specification Rev. 1.1) no later than 10 ms after the reset is removed.
Reset can wake a device from the suspended mode.
NOTE:
USB Reset can be configured not to generate a reset signal to the CPU
by setting the URSTD bit of the configuration register (see Section 5.
Configuration Register (CONFIG)). When a USB reset is detected, the
CPU generates an USB interrupt.
9.5.3 Suspend
The MCU supports suspend mode for low power. Suspend mode should
be entered when the USB data lines are in the idle state for more than
3ms. Entry into suspend mode is controlled by the SUSPND bit in the
USB interrupt register. Any low-speed bus activity should keep the
device out of the suspend state. Low-speed devices are kept awake by
periodic low-speed EOP signals from the host. This is referred to as low
speed keep alive (refer to Section 11.8.4.1 Low-Speed Keep-alive in the
Universal Serial Bus Specification Rev. 1.1).
Firmware should monitor the EOPF flag and enter suspend mode by
setting the SUSPND bit if an EOP is not detected for 3ms.
Per the USB specification, the bus powered USB system is required to
draw less than 500µA from the VDD supply when in the suspend state.
This includes the current supplied by the voltage regulator to the 1.5kΩ
to ground termination resistors placed at the host end of the USB bus.
This low-current requirement means that firmware is responsible for
entering stop mode once the USB module has been placed in the
suspend state.
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
Functional Description
9.5.4 Resume After Suspend
The MCU can be activated from the suspend state by normal bus
activity, a USB reset signal, or by a forced resume driven from the MCU.
9.5.4.1 Host Initiated Resume
The host signals resume by initiating resume signalling (K state) for at
least 20ms followed by a standard low-speed EOP signal. This 20ms
ensures that all devices in the USB network are awakened.
After resuming the bus, the host must begin sending bus traffic within
37ms to prevent the device from re-entering suspend mode.
9.5.4.2 USB Reset Signalling
Reset can wake a device from the suspended mode.
9.5.4.3 Remote Wakeup
The MCU also supports the remote wakeup feature. The firmware has
the ability to exit suspend mode by signaling a resume state to the
upstream host or hub. A non-idle state (K state) on the USB data lines is
accomplished by asserting the FRESUM bit in the UCR1 register.
When using the remote wakeup capability, the firmware must wait for at
least 5ms after the bus is in the idle state before sending the remote
wakeup resume signaling. This allows the upstream devices to get into
their suspend state and prepare for propagating resume signaling. The
FRESUM bit should be asserted to cause the resume state on the USB
data lines for at least 10ms, but not more than 15ms. Note that the
resume signalling is controlled by the FRESUM bit and meeting the
timing specifications is dependent on the firmware. When FRESUM is
cleared by firmware, the data lines will return to their high-impedance
state.
Refer to the register definitions (see 9.8.6 USB Control Register 1) for
more information about how the force resume (FRESUM) bit can be
used to initiate the remote wakeup feature.
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Universal Serial Bus Module (USB)
9.5.5 Low-Speed Device
Low-speed devices are configured by the position of a pull-up resistor on
the USB D– pin of the MCU. Low-speed devices are terminated as
shown in Figure 9-9 with the pull-up on the D– line.
VREG (3.3V)
MCU
1.5 kΩ
D+
USB LOW-SPEED CABLE
D–
Figure 9-9. External Low-Speed Device Configuration
For low-speed transmissions, the transmitter’s EOP width must be
between 1.25µs and 1.50µs. These ranges include timing variations due
to differential buffer delay and rise/fall time mismatches and to noise and
other random effects. A low-speed receiver must accept a 670ns SE0
followed by a J transition as a valid EOP. An SE0 shorter than
330ns or an SE0 not followed by a J transition are rejected as an EOP.
Any SE0 that is 8µs or longer is automatically a reset.
9.6 Clock Requirements
The low-speed data rate is nominally 1.5 Mbps. The OSCXCLK signal
driven by the oscillator circuits is the clock source for the USB module
and requires that a 6-MHz oscillator circuit be connected to the OSC1
and OSC2 pins. The permitted frequency tolerance for low-speed
functions is approximately ±1.5% (15,000 ppm). This tolerance includes
inaccuracies from all sources: initial frequency accuracy, crystal
capacitive loading, supply voltage on the oscillator, temperature, and
aging. The jitter in the low-speed data rate must be less than 10ns.
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
Hardware Description
9.7 Hardware Description
The USB module as previously shown in Figure 9-2 contains three
functional blocks: the low-speed USB transceiver, the USB control logic,
and the USB registers. The following details the function of the regulator,
transceiver, and control logic. See 9.8 I/O Registers for details of
register settings.
9.7.1 Voltage Regulator
The USB data lines are required by the USB specification to have an
output voltage between 2.8V and 3.6V. The data lines also are required
to have an external 1.5kΩ pull-up resistor connected between a data line
and a voltage source between 3.0V and 3.6V. Figure 9-10 shows the
worst case electrical connection for the voltage regulator.
4.0V – 5.5V
3.3V
REGULATOR
USB DATA LINES
R1
LOW-SPEED
TRANSCEIVER
HOST
OR
HUB
D+
USB CABLE
D–
R1 = 1.5kΩ ±5%
R2 = 15kΩ ±5%
R2
R2
Figure 9-10. Regulator Electrical Connections
9.7.2 USB Transceiver
The USB transceiver provides the physical interface to the USB D+ and
D– data lines. The transceiver is composed of two parts: an output drive
circuit and a receiver.
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Universal Serial Bus Module (USB)
9.7.2.1 Output Driver Characteristics
The USB transceiver uses a differential output driver to drive the USB
data signal onto the USB cable. The static output swing of the driver in
its low state is below the VOL of 0.3V with a 1.5kΩ load to 3.6V and in
its high state is above the VOH of 2.8V with a 15kΩ load to ground. The
output swings between the differential high and low state are well
balanced to minimize signal skew. Slew rate control on the driver is used
to minimize the radiated noise and cross talk. The driver’s outputs
support 3-state operation to achieve bidirectional half duplex operation.
The driver can tolerate a voltage on the signal pins of –1.0V to 5.5V with
respect to local ground reference without damage.
9.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics
The rise and fall time of the signals on this cable are greater than 75ns
and less than 300ns. The edges are matched to within ±20% to minimize
RFI emissions and signal skew.
USB data transmission is done with differential signals. A differential
input receiver is used to accept the USB data signal. A differential 1 on
the bus is represented by D+ being at least 200mV more positive than
D– as seen at the receiver, and a differential 0 is represented by D–
being at least 200mV more positive than D+ as seen at the receiver. The
signal cross over point must be between 1.3V and 2.0V.
ONE BIT
TIME
(1.5 Mb/s)
VSE (max)
VSE (min.)
SIGNAL PINS
PASS OUTPUT SPEC
LEVELS WITH MINIMAL
REFLECTIONS AND RINGING
VSS
Figure 9-11. Receiver Characteristics
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
Hardware Description
The receiver features an input sensitivity of 200mV when both
differential data inputs are in the differential common mode range of
0.8V to 2.5V as shown in Figure 9-12. In addition to the differential
receiver, there is a single-ended receiver (schmitt trigger) for each of the
two data lines.
Differential Input voltage Range
Differential Output
Crossover
Voltage Range
–1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
5.5
INPUT VOLTAGE RANGE (VOLTS)
Figure 9-12. Differential Input Sensitivity Range
9.7.2.3 Receiver Data Jitter
The data receivers for all types of devices must be able to properly
decode the differential data in the presence of jitter. The more of the bit
time that any data edge can occupy and still be decoded, the more
reliable the data transfer will be. Data receivers are required to decode
differential data transitions that occur in a window plus and minus a
nominal quarter bit time from the nominal (centered) data edge position.
Jitter will be caused by the delay mismatches and by mismatches in the
source and destination data rates (frequencies). The receive data jitter
budget for low speed is given in Section 18. Electrical Specifications.
The specification includes the consecutive (next) and paired transition
values for each source of jitter.
9.7.2.4 Data Source Jitter
The source of data can have some variation (jitter) in the timing of edges
of the data transmitted. The time between any set of data transitions is
N × TPeriod ± jitter time, where N is the number of bits between the
transitions and TPeriod is defined as the actual period of the data rate.
The data jitter is measured with the same capacitive load used for
maximum rise and fall times and is measured at the crossover points of
the data lines as shown in Figure 9-13.
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Universal Serial Bus Module (USB)
tPeriod
CROSSOVER
POINTS
DIFFERENTIAL
DATA LINES
JITTER
CONSECUTIVE
TRANSITIONS
PAIRED
TRANSITIONS
Figure 9-13. Data Jitter
For low-speed transmissions, the jitter time for any consecutive
differential data transitions must be within ±25ns and within ±10ns for
any set of paired differential data transitions. These jitter numbers
include timing variations due to differential buffer delay, rise/fall time
mismatches, internal clock source jitter, noise and other random effects.
9.7.2.5 Data Signal Rise and Fall Time
The output rise time and fall time are measured between 10% and 90%
of the signal. Edge transition time for the rising and falling edges of
low-speed signals is 75ns (minimum) into a capacitive load (CL) of
200pF and 300ns (maximum) into a capacitive load of 600pF. The rising
and falling edges should be transitioning (monotonic) smoothly when
driving the cable to avoid excessive EMI.
FALL TIME
RISE TIME
+
90%
CL
90%
DIFFERENTIAL
DATA LINES
10%
10%
+
tR
CL
tF
LOW SPEED: 75ns at CL = 200pF, 300ns at CL = 600 pF
Figure 9-14. Data Signal Rise and Fall Time
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
I/O Registers
9.7.3 USB Control Logic
The USB control logic manages data movement between the CPU and
the transceiver. The control logic handles both transmit and receive
operations on the USB. It contains the logic used to manipulate the
transceiver and the endpoint registers.
The byte count buffer is loaded with the active transmit endpoints byte
count value during transmit operations. This same buffer is used for
receive transactions to count the number of bytes received and, upon
the end of the transaction, transfer that number to the receive endpoints
byte count register.
When transmitting, the control logic handles parallel-to-serial
conversion, CRC generation, NRZI encoding, and bit stuffing.
When receiving, the control logic handles sync detection, packet
identification, end-of-packet detection, bit (un)stuffing, NRZI decoding,
CRC validation, and serial-to-parallel conversion. Errors detected by the
control logic include bad CRC, timeout while waiting for EOP, and bit
stuffing violations.
9.8 I/O Registers
These I/O registers control and monitor USB operation:
•
USB address register (UADDR)
•
USB control registers 0–4 (UCR0–UCR4)
•
USB status registers 0–1 (USR0–USR1)
•
USB interrupt registers 0–2 (UIR0–UIR2)
•
USB endpoint 0 data registers 0–7 (UE0D0–UE0D7)
•
USB endpoint 1 data registers 0–7 (UE1D0–UE1D7)
•
USB endpoint 2 data registers 0–7 (UE2D0–UE2D7)
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Universal Serial Bus Module (USB)
9.8.1 USB Address Register
Address:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
0*
0
0
0
0
0
0
0
Read:
Write:
Reset:
* USBEN bit is reset by POR or LVI reset only.
Figure 9-15. USB Address Register (UADDR)
USBEN — USB Module Enable
This read/write bit enables and disables the USB module and the USB
pins. When USBEN is set, the USB module is enabled and the PTE4
interrupt is disabled. When USBEN is clear, the USB module will not
respond to any tokens, USB reset and USB related interrupts are
disabled, and pins PTE4/D– and PTE3/D+ function as high current
open-drain I/O port pins PTE4 and PTE3.
1 = USB function enabled and PTE4 interrupt is disabled
0 = USB function disabled including USB interrupt, reset and reset
interrupt
UADD[6:0] — USB Function Address
These bits specify the USB address of the device. Reset clears these
bits.
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
I/O Registers
9.8.2 USB Interrupt Register 0
Address:
$0039
Bit 7
6
5
4
3
EOPIE
SUSPND
TXD2IE
RXD2IE
TXD1IE
0
0
0
0
0
Read:
2
1
Bit 0
TXD0IE
RXD0IE
0
0
0
Write:
Reset:
0
= Unimplemented
Figure 9-16. USB Interrupt Register 0 (UIR0)
EOPIE — End-of-Packet Detect Interrupt Enable
This read/write bit enables the USB to generate CPU interrupt
requests when the EOPF bit becomes set. Reset clears the EOPIE
bit.
1 = End-of-packet sequence detection can generate a CPU
interrupt request
0 = End-of-packet sequence detection cannot generate a CPU
interrupt request
SUSPND — USB Suspend Bit
To save power, this read/write bit should be set by the software if a
3ms constant idle state is detected on the USB bus. Setting this bit
puts the transceiver into a power-saving mode. The RESUMF flag
must be cleared before setting SUSPND. Software must clear this bit
after the resume flag (RESUMF) is set while this resume interrupt flag
is serviced.
TXD2IE — Endpoint 2 Transmit Interrupt Enable
This read/write bit enables the transmit endpoint 2 to generate CPU
interrupt requests when the TXD2F bit becomes set. Reset clears the
TXD2IE bit.
1 = Transmit endpoint 2 can generate a CPU interrupt request
0 = Transmit endpoint 2 cannot generate a CPU interrupt request
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Universal Serial Bus Module (USB)
RXD2IE — Endpoint 2 Receive Interrupt Enable
This read/write bit enables the receive endpoint 2 to generate CPU
interrupt requests when the RXD2F bit becomes set. Reset clears the
RXD2IE bit.
1 = Receive endpoint 2 can generate a CPU interrupt request
0 = Receive endpoint 2 cannot generate a CPU interrupt request
TXD1IE — Endpoint 1 Transmit Interrupt Enable
This read/write bit enables the transmit endpoint 1 to generate CPU
interrupt requests when the TXD1F bit becomes set. Reset clears the
TXD1IE bit.
1 = Transmit endpoints 1 can generate a CPU interrupt request
0 = Transmit endpoints 1 cannot generate a CPU interrupt request
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the transmit endpoint 0 to generate CPU
interrupt requests when the TXD0F bit becomes set. Reset clears the
TXD0IE bit.
1 = Transmit endpoint 0 can generate a CPU interrupt request
0 = Transmit endpoint 0 cannot generate a CPU interrupt request
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the receive endpoint 0 to generate CPU
interrupt requests when the RXD0F bit becomes set. Reset clears the
RXD0IE bit.
1 = Receive endpoint 0 can generate a CPU interrupt request
0 = Receive endpoint 0 cannot generate a CPU interrupt request
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Universal Serial Bus Module (USB)
I/O Registers
9.8.3 USB Interrupt Register 1
Address:
Read:
$003A
Bit 7
6
5
4
3
2
1
Bit 0
EOPF
RSTF
TXD2F
RXD2F
TXD1F
RESUMF
TXD0F
RXD0F
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 9-17. USB Interrupt Register 1 (UIR1)
EOPF — End-of-Packet Detect Flag
This read-only bit is set when a valid end-of-packet sequence is
detected on the D+ and D– lines. Software must clear this flag by
writing a logic 1 to the EOPFR bit.
Reset clears this bit. Writing to EOPF has no effect.
1 = End-of-packet sequence has been detected
0 = End-of-packet sequence has not been detected
RSTF — USB Reset Flag
This read-only bit is set when a valid reset signal state is detected on
the D+ and D– lines. If the URSTD bit of the configuration register
(CONFIG) is clear, this reset detection will generate an internal reset
signal to reset the CPU and other peripherals including the USB
module. If the URSTD bit is set, this reset detection will generate an
USB interrupt. This bit is cleared by writing a logic 1 to the RSTFR bit.
This bit also is cleared by a POR reset.
NOTE:
The USB bit in the RSR register (see 8.8.2 Reset Status Register) is
also a USB reset indicator.
TXD2F — Endpoint 2 Data Transmit Flag
This read-only bit is set after the data stored in endpoint 2 transmit
buffers has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD2FR bit.
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Universal Serial Bus Module (USB)
To enable the next data packet transmission, TX2E also must be set.
If the TXD2F bit is not cleared, a NAK handshake will be returned in
the next IN transaction.
Reset clears this bit. Writing to TXD2F has no effect.
1 = Transmit on endpoint 2 has occurred
0 = Transmit on endpoint 2 has not occurred
RXD2F — Endpoint 2 Data Receive Flag
This read-only bit is set after the USB module has received a data
packet and responded with an ACK handshake packet. Software
must clear this flag by writing a logic 1 to the RXD2FR bit after all of
the received data has been read. Software also must set the RX2E bit
to 1 to enable the next data packet reception. If the RXD2F bit is not
cleared, a NAK handshake will be returned in the next OUT
transaction.
Reset clears this bit. Writing to RXD2F has no effect.
1 = Receive on endpoint 2 has occurred
0 = Receive on endpoint 2 has not occurred
TXD1F — Endpoint 1 Data Transmit Flag
This read-only bit is set after the data stored in the endpoint 1 transmit
buffer has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD1FR bit. To
enable the next data packet transmission, TX1E also must be set. If
the TXD1F bit is not cleared, a NAK handshake will be returned in the
next IN transaction.
Reset clears this bit. Writing to TXD1F has no effect.
1 = Transmit on endpoint 1has occurred
0 = Transmit on endpoint 1has not occurred
RESUMF — Resume Flag
This read-only bit is set when USB bus activity is detected while the
SUSPND bit is set. Software must clear this flag by writing a logic 1 to
the RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF
has no effect.
1 = USB bus activity has been detected
0 = No USB bus activity has been detected
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Universal Serial Bus Module (USB)
I/O Registers
TXD0F — Endpoint 0 Data Transmit Flag
This read-only bit is set after the data stored in endpoint 0 transmit
buffers has been sent and an ACK handshake packet from the host is
received. Once the next set of data is ready in the transmit buffers,
software must clear this flag by writing a logic 1 to the TXD0FR bit. To
enable the next data packet transmission, TX0E also must be set. If
the TXD0F bit is not cleared, a NAK handshake will be returned in the
next IN transaction.
Reset clears this bit. Writing to TXD0F has no effect.
1 = Transmit on endpoint 0 has occurred
0 = Transmit on endpoint 0 has not occurred
RXD0F — Endpoint 0 Data Receive Flag
This read-only bit is set after the USB module has received a data
packet and responded with an ACK handshake packet. Software
must clear this flag by writing a logic 1 to the RXD0FR bit after all of
the received data has been read. Software also must set the RX0E bit
to 1 to enable the next data packet reception. If the RXD0F bit is not
cleared, the USB will respond with a NAK handshake to any
endpoint 0 OUT tokens; but does not respond to a SETUP token.
Reset clears this bit. Writing to RXD0F has no effect.
1 = Receive on endpoint 0 has occurred
0 = Receive on endpoint 0 has not occurred
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Universal Serial Bus Module (USB)
9.8.4 USB Interrupt Register 2
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
EOPFR
RSTFR
TXD2FR
RXD2FR
Reset:
0
0
0
0
TXD1FR RESUMFR TXD0FR
0
0
0
RXD0FR
0
Figure 9-18. USB Interrupt Register 2 (UIR2)
EOPFR — End-of-Packet Flag Reset
Writing a logic 1 to this write-only bit will clear the EOPF bit if it is set.
Writing a logic 0 to the EOPFR has no effect. Reset clears this bit.
RSTFR — Clear Reset Indicator Bit
Writing a logic 1 to this write-only bit will clear the RSTF bit if it is set.
Writing a logic 0 to the RSTFR has no effect. Reset clears this bit.
TXD2FR — Endpoint 2 Transmit Flag Reset
Writing a logic 1 to this write-only bit will clear the TXD2F bit if it is set.
Writing a logic 0 to TXD2FR has no effect. Reset clears this bit.
RXD2FR — Endpoint 2 Receive Flag Reset
Writing a logic 1 to this write-only bit will clear the RXD2F bit if it is set.
Writing a logic 0 to RXD2FR has no effect. Reset clears this bit.
TXD1FR — Endpoint 1 Transmit Flag Reset
Writing a logic 1 to this write-only bit will clear the TXD1F bit if it is set.
Writing a logic 0 to TXD1FR has no effect. Reset clears this bit.
RESUMFR — Resume Flag Reset
Writing a logic 1 to this write-only bit will clear the RESUMF bit if it is
set. Writing to RESUMFR has no effect. Reset clears this bit.
TXD0FR — Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write-only bit will clear the TXD0F bit if it is set.
Writing a logic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write-only bit will clear the RXD0F bit if it is set.
Writing a logic 0 to RXD0FR has no effect. Reset clears this bit.
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Universal Serial Bus Module (USB)
I/O Registers
9.8.5 USB Control Register 0
Address:
$003B
Bit 7
Read:
6
5
4
3
2
1
Bit 0
TX0E
RX0E
TP0SIZ3
TP0SIZ2
TP0SIZ1
TP0SIZ0
0
0
0
0
0
0
0
T0SEQ
Write:
Reset:
0
0
Figure 9-19. USB Control Register 0 (UCR0)
T0SEQ — Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed at
endpoint 0. Toggling of this bit must be controlled by software. Reset
clears this bit.
1 = DATA1 token active for next endpoint 0 transmit
0 = DATA0 token active for next endpoint 0 transmit
TX0E — Endpoint 0 Transmit Enable
This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 0. Software should set this
bit when data is ready to be transmitted. It must be cleared by
software when no more endpoint 0 data needs to be transmitted.
If this bit is 0 or the TXD0F is set, the USB will respond with a NAK
handshake to any endpoint 0 IN tokens. Reset clears this bit.
1 = Data is ready to be sent
0 = Data is not ready. Respond with NAK
RX0E — Endpoint 0 Receive Enable
This read/write bit enables a receive to occur when the USB host
controller sends an OUT token to endpoint 0. Software should set this
bit when data is ready to be received. It must be cleared by software
when data cannot be received.
If this bit is 0 or the RXD0F is set, the USB will respond with a NAK
handshake to any endpoint 0 OUT tokens; but does not respond to a
SETUP token. Reset clears this bit.
1 = Data is ready to be received
0 = Not ready for data. Respond with NAK
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Universal Serial Bus Module (USB)
TP0SIZ3–TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 0. These bits are cleared by reset.
9.8.6 USB Control Register 1
Address:
$003C
Bit 7
6
5
T1SEQ
STALL1
TX1E
0
0
0
4
3
2
1
Bit 0
TP1SIZ2
TP1SIZ1
TP1SIZ0
0
0
0
Read:
FRESUM TP1SIZ3
Write:
Reset:
0
0
Figure 9-20. USB Control Register 1 (UCR1)
T1SEQ — Endpoint 1 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed to
endpoint 1. Toggling of this bit must be controlled by software. Reset
clears this bit.
1 = DATA1 token active for next endpoint 1 transmit
0 = DATA0 token active for next endpoint 1 transmit
STALL1 — Endpoint 1 Force Stall Bit
This read/write bit causes endpoint 1 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
Reset clears this bit.
1 = Send STALL handshake
0 = Default
TX1E — Endpoint 1 Transmit Enable
This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 1. The appropriate endpoint
enable bit, ENABLE1 bit in the UCR3 register, also should be set.
Software should set the TX1E bit when data is ready to be
transmitted. It must be cleared by software when no more data needs
to be transmitted.
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Universal Serial Bus Module (USB)
I/O Registers
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK
handshake to any endpoint 1 directed IN tokens. Reset clears this bit.
1 = Data is ready to be sent
0 = Data is not ready. Respond with NAK
FRESUM — Force Resume
This read/write bit forces a resume state (K or non-idle state) onto the
USB data lines to initiate a remote wakeup. Software should control
the timing of the forced resume to be between 10 and 15 ms. Setting
this bit will not cause the RESUMF bit to be set.
1 = Force data lines to K state
0 = Default
TP1SIZ3–TP1SIZ0 — Endpoint 1 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 1. These bits are cleared by reset.
9.8.7 USB Control Register 2
Address:
$0019
Bit 7
6
5
4
3
2
1
Bit 0
T2SEQ
STALL2
TX2E
RX2E
TP2SIZ3
TP2SIZ2
TP2SIZ1
TP2SIZ0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-21. USB Control Register 2 (UCR2)
T2SEQ — Endpoint 2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed to
endpoint 2. Toggling of this bit must be controlled by software. Reset
clears this bit.
1 = DATA1 token active for next endpoint 2 transmit
0 = DATA0 token active for next endpoint 2 transmit
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Universal Serial Bus Module (USB)
STALL2 — Endpoint 2 Force Stall Bit
This read/write bit causes endpoint 2 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
Reset clears this bit.
1 = Send STALL handshake
0 = Default
TX2E — Endpoint 2 Transmit Enable
This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 2. The appropriate endpoint
enable bit, ENABLE2 bit in the UCR3 register, also should be set.
Software should set the TX2E bit when data is ready to be
transmitted. It must be cleared by software when no more data needs
to be transmitted.
If this bit is 0 or the TXD2F is set, the USB will respond with a NAK
handshake to any endpoint 2 directed IN tokens. Reset clears this bit.
1 = Data is ready to be sent
0 = Data is not ready. Respond with NAK
RX2E — Endpoint 2 Receive Enable
This read/write bit enables a receive to occur when the USB host
controller sends an OUT token to endpoint 2. Software should set this
bit when data is ready to be received. It must be cleared by software
when data cannot be received.
If this bit is 0 or the RXD2F is set, the USB will respond with a NAK
handshake to any endpoint 2 OUT tokens. Reset clears this bit.
1 = Data is ready to be received
0 = Not ready for data. Respond with NAK
TP2SIZ3–TP2SIZ0 — Endpoint 2 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 2. These bits are cleared by reset.
Technical Data
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
I/O Registers
9.8.8 USB Control Register 3
Address:
Read:
$001A
Bit 7
6
TX1ST
0
Write:
Reset:
5
4
OSTALL0
ISTALL0
0
0
3
2
1
Bit 0
0
PULLEN ENABLE2 ENABLE1
TX1STR
0
0
0
0*
0
0
= Unimplemented
* PULLEN bit is reset by POR or LVI reset only.
Figure 9-22. USB Control Register 3 (UCR3)
TX1ST — Endpoint 0 Transmit First Flag
This read-only bit is set if the endpoint 0 data transmit flag (TXD0F) is
set when the USB control logic is setting the endpoint 0 data receive
flag (RXD0F). In other words, if an unserviced endpoint 0 transmit flag
is still set at the end of an endpoint 0 reception, then this bit will be set.
This bit lets the firmware know that the endpoint 0 transmission
happened before the endpoint 0 reception.
Reset clears this bit.
1 = IN transaction occurred before SETUP/OUT
0 = IN transaction occurred after SETUP/OUT
TX1STR — Clear Endpoint 0 Transmit First Flag
Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set.
Writing a logic 0 to the TX1STR has no effect. Reset clears this bit.
OSTALL0 — Endpoint 0 Force STALL Bit for OUT token
This read/write bit causes endpoint 0 to return a STALL handshake
when polled by an OUT token by the USB host controller. Reset
clears this bit.
1 = Send STALL handshake
0 = Default
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Universal Serial Bus Module (USB)
ISTALL0 — Endpoint 0 Force STALL Bit for IN token
This read/write bit causes endpoint 0 to return a STALL handshake
when polled by an IN token by the USB host controller.
Reset clears this bit.
1 = Send STALL handshake
0 = Default
PULLEN — Pull-up Enable
This read/write bit controls the pull-up option for the USB D– pin if the
USB module is enabled.
1 = Configure D– pin to have internal pull-up
0 = Disconnect D– pin internal pull-up
ENABLE2 — Endpoint 2 Enable
This read/write bit enables endpoint 2 and allows the USB to respond
to IN or OUT packets addressed to endpoint 2. Reset clears this bit.
1 = Endpoint 2 is enabled and can respond to an IN or OUT token
0 = Endpoint 2 is disabled
ENABLE1 — Endpoint 1 Enable
This read/write bit enables endpoint 1 and allows the USB to respond
to IN packets addressed to endpoint 1. Reset clears this bit.
1 = Endpoint 1 is enabled and can respond to an IN token
0 = Endpoint 1 is disabled
Technical Data
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
I/O Registers
9.8.9 USB Control Register 4
USB control register 4 directly controls the USB data pins D+ and D–. If
the FUSBO bit, and the USBEN bit of the USB address register
(UADDR) are set, the output buffers of the USB modules are enabled
and the corresponding levels of the USB data pins D+ and D– are equal
to the values set by the FDP and the FDM bits.
Address:
Read:
$001B
Bit 7
6
5
4
3
0
0
0
0
0
2
1
Bit 0
FUSBO
FDP
FDM
0
0
0
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 9-23. USB Control Register 4 (UCR4)
FUSBO — Force USB Output
This read/write bit enables the USB output buffers.
1 = Enables USB output buffers
0 = USB module in normal operation
FDP — Force D+
This read/write bit determinates the output level of D+.
1 = D+ at output high level
0 = D+ at output low level
FDM — Force D–
This read/write bit determinates the output level of D–.
1 = D– at output high level
0 = D– at output low level
NOTE:
Customers must be very careful when setting the UCR4 register. When
the FUSBO and the USBEN bits are set, the USB module is in output
mode and it will not recognize any USB signals including the USB reset
signal. The UCR4 register is used for some special applications.
Customers are not normally expected to use this register.
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
9.8.10 USB Status Register 0
Address:
Read:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
R0SEQ
SETUP
0
0
RP0SIZ3
RP0SIZ2
RP0SIZ1
RP0SIZ0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 9-24. USB Status Register 0 (USR0)
R0SEQ — Endpoint 0 Receive Sequence Bit
This read-only bit indicates the type of data packet last received for
endpoint 0 (DATA0 or DATA1).
1 = DATA1 token received in last endpoint 0 receive
0 = DATA0 token received in last endpoint 0 receive
SETUP — SETUP Token Detect Bit
This read-only bit indicates that a valid SETUP token has been
received.
1 = Last token received for endpoint 0 was a SETUP token
0 = Last token received for endpoint 0 was not a SETUP token
RP0SIZ3–RP0SIZ0 — Endpoint 0 Receive Data Packet Size
These read-only bits store the number of data bytes received for the
last OUT or SETUP transaction for endpoint 0.
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
I/O Registers
9.8.11 USB Status Register 1
Address:
Read:
$003E
Bit 7
6
5
4
3
2
1
Bit 0
R2SEQ
TXACK
TXNAK
TXSTL
RP2SIZ3
RP2SIZ2
RP2SIZ1
RP2SIZ0
U
0
0
0
U
U
U
U
Write:
Reset:
= Unimplemented
U = Unaffected by reset
Figure 9-25. USB Status Register 1 (USR1)
R2SEQ — Endpoint 2 Receive Sequence Bit
This read-only bit indicates the type of data packet last received for
endpoint 2 (DATA0 or DATA1).
1 = DATA1 token received in last endpoint 2 receive
0 = DATA0 token received in last endpoint 2 receive
TXACK — ACK Token Transmit Bit
This read-only bit indicates that an ACK token has been transmitted.
This bit is updated at the end of the EP0 data transmission.
1 = Last token transmitted for endpoint 0 was an ACK token
0 = Last token transmitted for endpoint 0 was not an ACK token
TXNAK — NAK Token Transmit Bit
This read-only bit indicates that a TXNAK token has been transmitted.
This bit is updated at the end of the EP0 data transmission.
1 = Last token transmitted for endpoint 0 was a NAK token
0 = Last token transmitted for endpoint 0 was not a NAK token
TXSTL — STALL Token Transmit Bit
This read-only bit indicates that a STALL token has been transmitted.
This bit is updated at the end of the EP0 data transmission.
1 = Last token transmitted for endpoint 0 was a STALL token
0 = Last token transmitted for endpoint 0 was not a STALL token
RP2SIZ3–RP2SIZ0 — Endpoint 2 Receive Data Packet Size
These read-only bits store the number of data bytes received for the
last OUT transaction for endpoint 2.
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
9.8.12 USB Endpoint 0 Data Registers
Address:
$0020
UE0D0
Bit 7
6
5
4
3
2
1
Bit 0
Read: UE0R07
UE0R06
UE0R05
UE0R04
UE0R03
UE0R02
UE0R01
UE0R00
Write: UE0T07
UE0T06
UE0T05
UE0T04
UE0T03
UE0T02
UE0T01
UE0T00
Reset:
Unaffected by reset
↓
Address:
$0027
↓
UE0D7
Read: UE0R77
UE0R76
UE0R75
UE0R74
UE0R73
UE0R72
UE0R71
UE0R70
Write: UE0T77
UE0T76
UE0T75
UE0T74
UE0T73
UE0T72
UE0T71
UE0T70
Reset:
Unaffected by reset
Figure 9-26. USB Endpoint 0 Data Registers (UE0D0–UE0D7)
UE0Rx7–UE0Rx0 — Endpoint 0 Receive Data Buffer
These read-only bits are serially loaded with OUT token or SETUP
token data directed at endpoint 0. The data is received over the USB’s
D+ and D– pins.
UE0Tx7–UE0Tx0 — Endpoint 0 Transmit Data Buffer
These write-only buffers are loaded by software with data to be sent
on the USB bus on the next IN token directed at endpoint 0.
Technical Data
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Freescale Semiconductor
Universal Serial Bus Module (USB)
I/O Registers
9.8.13 USB Endpoint 1 Data Registers
Address:
$0028
UE1D0
Bit 7
6
5
4
3
2
1
Bit 0
UE1T06
UE1T05
UE1T04
UE1T03
UE1T02
UE1T01
UE1T00
Read:
Write: UE1T07
Reset:
Unaffected by reset
↓
Address:
$002F
↓
UE1D7
Read:
Write: UE1T77
UE1T76
UE1T75
Reset:
UE1T74
UE1T73
UE1T72
UE1T71
UE1T70
Unaffected by reset
= Unimplemented
Figure 9-27. USB Endpoint 1 Data Registers (UE1D0–UE1D7)
UE1Tx7–UE1Tx0 — Endpoint 1 Transmit or Receive Data Buffer
These write-only buffers are loaded by software with data to be sent
on the USB bus on the next IN token directed at endpoint 1.
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Universal Serial Bus Module (USB)
9.8.14 USB Endpoint 2 Data Registers
Address:
$0030
UE2D0
Bit 7
6
5
4
3
2
1
Bit 0
Read: UE2R07
UE2R06
UE2R05
UE2R04
UE2R03
UE2R02
UE2R01
UE2R00
Write: UE2T07
UE2T06
UE2T05
UE2T04
UE2T03
UE2T02
UE2T01
UE2T00
Reset:
Unaffected by reset
↓
Address:
$0037
↓
UE2D7
Read: UE2R77
UE2R76
UE2R75
UE2R74
UE2R73
UE2R72
UE2R71
UE2R70
Write: UE2T77
UE2T76
UE2T75
UE2T74
UE2T73
UE2T72
UE2T71
UE2T70
Reset:
Unaffected by reset
Figure 9-28. USB Endpoint 2 Data Registers (UE2D0–UE2D7)
UE2Rx7–UE2Rx0 — Endpoint 2 Receive Data Buffer
These read-only bits are serially loaded with OUT token data directed
at endpoint 2. The data is received over the USB’s D+ and D– pins.
UE2Tx7–UE2Tx0 — Endpoint 2 Transmit Data Buffer
These write-only buffers are loaded by software with data to be sent
on the USB bus on the next IN token directed at endpoint 2.
Technical Data
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
USB Interrupts
9.9 USB Interrupts
The USB module is capable of generating interrupts and causing the
CPU to execute the USB interrupt service routine. There are three types
of USB interrupts:
•
End-of-transaction interrupts signify either a completed
transaction receive or transmit transaction.
•
Resume interrupts signify that the USB bus is reactivated after
having been suspended.
•
End-of-packet interrupts signify that a low-speed end-of-packet
signal was detected.
All USB interrupts share the same interrupt vector. Firmware is
responsible for determining which interrupt is active.
9.9.1 USB End-of-Transaction Interrupt
There are five possible end-of-transaction interrupts:
•
Endpoint 0 or 2 receive
•
Endpoint 0, 1 or 2 transmit
End-of-transaction interrupts occur as detailed in the following sections.
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Universal Serial Bus Module (USB)
9.9.1.1 Receive Control Endpoint 0
For a control OUT transaction directed at endpoint 0, the USB module
will generate an interrupt by setting the RXD0F flag in the UIR0 register.
The conditions necessary for the interrupt to occur are shown in the
flowchart in Figure 9-29.
VALID OUT TOKEN
RECEIVED FOR ENDPOINT 0
Y
VALID DATA TOKEN
RECEIVED FOR ENDPOINT 0?
N
TIMEOUT
NO RESPONSE
FROM USB FUNCTION
Y
USB MODULE ENABLED?
(USBEN = 1)
N
NO RESPONSE
FROM USB FUNCTION
N
SEND STALL
HANDSHAKE
N
SEND NAK
HANDSHAKE
Y
ENDPOINT 0 RECEIVE NOT STALLED?
(OSTALL0 = 0)
Y
ENDPOINT 0 RECEIVE READY TO RECEIVE?
(RX0E = 1) AND (RXD0F = 0)
Y
ACCEPT DATA
SET/CLEAR R0SEQ BIT
ERROR FREE DATA PACKET?
N
IGNORE TRANSACTION
NO RESPONSE FROM
USB FUNCTION
Y
SET RXD0F TO 1
RECEIVE CONTROL ENDPOINT
INTERRUPT ENABLED?
(RXD0IE = 1)
N
Y
VALID TRANSACTION
INTERRUPT GENERATED
NO INTERRUPT
Figure 9-29. OUT Token Data Flow for Receive Endpoint 0
Technical Data
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
USB Interrupts
SETUP transactions cannot be stalled by the USB function. A SETUP
received by a control endpoint will clear the ISTALL0 and OSTALL0 bits.
The conditions for receiving a SETUP interrupt are shown in
Figure 9-30.
VALID SETUP TOKEN
RECEIVED FOR ENDPOINT 0?
Y
USB MODULE ENABLED?
(USBEN = 1)
N
NO RESPONSE
FROM USB FUNCTION
N
NO RESPONSE
FROM USB FUNCTION
Y
ENDPOINT 0 RECEIVE READY TO RECEIVE?
(RX0E = 1) AND (RXD0F = 0)
Y
ACCEPT DATA
SET/CLEAR R0SEQ BIT
SET SETUP BIT TO 1
ERROR FREE DATA PACKET?
N
IGNORE TRANSACTION
NO RESPONSE FROM
USB FUNCTION
Y
SET RXD0F TO 1
RECEIVE CONTROL ENDPOINT
INTERRUPT ENABLED?
(RXD0IE = 1)
N
Y
VALID TRANSACTION
INTERRUPT GENERATED
NO INTERRUPT
Figure 9-30. SETUP Token Data Flow for Receive Endpoint 0
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Universal Serial Bus Module (USB)
9.9.1.2 Transmit Control Endpoint 0
For a control IN transaction directed at endpoint 0, the USB module will
generate an interrupt by setting the TXD0F flag in the UIR1 register. The
conditions necessary for the interrupt to occur are shown in the flowchart
in Figure 9-31.
VALID IN TOKEN
RECEIVED FOR ENDPOINT 0
Y
USB MODULE ENABLED?
(USBEN = 1)
N
NO RESPONSE
FROM USB FUNCTION
N
SEND STALL
HANDSHAKE
N
SEND NAK
HANDSHAKE
N
NO RESPONSE
FROM USB FUNCTION
Y
TRANSMIT ENDPOINT NOT STALLED
BY FIRMWARE (ISTALL0 = 0)?
Y
TRANSMIT ENDPOINT READY TO TRANSFER?
(TX0E = 1) AND (TXD0F = 0)
Y
SEND DATA
DATA PID SET BY T0SEQ
ACK RECEIVED AND NO
TIMEOUT CONDITION OCCURS?
Y
SET TXD0F TO 1
TRANSMIT ENDPOINT
INTERRUPT ENABLED?
(TXD0IE = 1)
N
Y
VALID TRANSACTION
INTERRUPT GENERATED
NO INTERRUPT
Figure 9-31. IN Token Data Flow for Transmit Endpoint 0
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Universal Serial Bus Module (USB)
Freescale Semiconductor
Universal Serial Bus Module (USB)
USB Interrupts
9.9.1.3 Transmit Endpoint 1
For an IN transaction directed at endpoint 1, the USB module will
generate an interrupt by setting the TXD1F in the UIR1 register. The
conditions necessary for the interrupt to occur are shown in
Figure 9-32.
VALID IN TOKEN
RECEIVED FOR ENDPOINT 1
Y
USB MODULE ENABLED?
(USBEN = 1)
N
NO RESPONSE
FROM USB FUNCTION
N
SEND STALL
HANDSHAKE
N
SEND NAK
HANDSHAKE
N
NO RESPONSE
FROM USB FUNCTION
N
NO RESPONSE
FROM USB FUNCTION
Y
TRANSMIT ENDPOINT NOT STALLED
BY FIRMWARE (STALL1 = 1)?
Y
TRANSMIT ENDPOINT READY TO TRANSFER?
(TX1E = 1) AND (TXD1F = 0) AND (UE1TR = 0)
Y
TRANSMIT ENDPOINT ENABLED?
(ENABLE = 1)
Y
SEND DATA
DATA PID SET BY T1SEQ
ACK RECEIVED AND NO
TIMEOUT CONDITION OCCURS?
Y
SET TXD1F TO 1
TRANSMIT ENDPOINT
INTERRUPT ENABLED?
(TXD1IE = 1)
N
Y
VALID TRANSACTION
INTERRUPT GENERATED
NO INTERRUPT
Figure 9-32. IN Token Data Flow for Transmit Endpoint 1
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Universal Serial Bus Module (USB)
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Universal Serial Bus Module (USB)
9.9.1.4 Transmit Endpoint 2
For an IN transaction directed at endpoint 2, the USB module will
generate an interrupt by setting the TXD2F in the UIR1 register.
9.9.1.5 Receive Endpoint 2
For an OUT transaction directed at endpoint 2, the USB module will
generate an interrupt by setting the RXD2F in the UIR1 register.
9.9.2 Resume Interrupt
The USB module will generate a CPU interrupt if low-speed bus activity
is detected after entering the suspend state. A transition of the USB data
lines to the non-idle state (K state) while in the suspend mode will set the
RESUMF flag in the UIR1 register. There is no interrupt enable bit for this
interrupt source and an interrupt will be executed if the I-bit in the CCR
is cleared. A resume interrupt can only occur while the MCU is in the
suspend mode.
9.9.3 End-of-Packet Interrupt
The USB module can generate a USB interrupt upon detection of an
end-of-packet signal for low-speed devices. Upon detection of an
end-of-packet signal, the USB module sets the EOPF bit and will
generate a CPU interrupt if the EOPIE bit in the UIR0 register is set.
Technical Data
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Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 10. Monitor ROM (MON)
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
10.4.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
10.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode
entry methods. The monitor ROM allows complete testing of the MCU
through a single-wire interface with host computer. This mode is also
used for programming and erasing of FLASH memory in the MCU.
Monitor mode entry can be achieved without use of the higher voltage,
VDD + VHI, as long as vector addresses $FFFE and $FFFF are blank,
thus reducing the hardware requirements for in-circuit programming.
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Monitor ROM (MON)
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Monitor ROM (MON)
10.3 Features
Features of the monitor ROM include the following:
•
Normal user-mode pin functionality
•
One pin dedicated to serial communication between monitor ROM
and host computer
•
Standard mark/space non-return-to-zero (NRZ) communication
with host computer
•
Execution of code in RAM or FLASH
•
FLASH memory security feature1
•
FLASH memory programming interface
•
976 bytes monitor ROM code size
•
Monitor mode entry without high voltage, VDD + VHI, if reset vector
is blank ($FFFE and $FFFF contain $FF)
•
Standard monitor mode entry if high voltage, VDD + VHI, is applied
to IRQ
10.4 Functional Description
The monitor ROM receives and executes commands from a host
computer. Figure 10-1 shows a example circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute host-computer code in RAM while most
MCU pins retain normal operating mode functions. All communication
between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and
the host computer. PTA0 is used in a wired-OR configuration and
requires a pull-up resistor.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data
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Monitor ROM (MON)
Freescale Semiconductor
Monitor ROM (MON)
Functional Description
VDD
10k Ω
VDD + VHI
RST
0.1 µF
10k Ω
HC908JB8
SW2
C
(SEE NOTE 2)
IRQ
D
VREG
+
4.7 µF
0.1 µF
VDD
VDD
6MHz
VDD
0.1 µF
VSS
(SEE NOTE 3)
10 µF
10 µF
MC145407
+
+
E
20
+
3
18
4
17
2
19
SW3
fXCLK
6MHz
10 µF
20 pF
OSC1
F
E
10MΩ
1
OSC2
F
+
10 µF
VDD
3.3V
20 pF
10 kΩ
DB-25
2
3
A
5
6
16
(SEE NOTE 1)
SW1
PTA3
B
15
3.3V
7
1
MC74LCX125
3.3V
14
2
3
6
5
10 kΩ
4
PTA0
3.3V
10 kΩ
7
PTA1
PTA2
NOTES:
1. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A — Bus clock = fXCLK ÷ 2
SW1: Position B — Bus clock = fXCLK
2. SW2: Position C — High-voltage entry to monitor mode.
SW2: Position D — Low-voltage entry to monitor mode (with blank reset vector).
See Section 18 for IRQ voltage level requirements.
3. SW3: Position E — OSC1 directly driven by external oscillator.
SW3: Position F — OSC1 driven by crystal oscillator circuit.
10 kΩ
Figure 10-1. Monitor Mode Circuit
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Monitor ROM (MON)
Technical Data
165
Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ = VDD + VHI:
– External clock on OSC1 is 3MHz
– PTA3 = low
2. If IRQ = VDD + VHI:
– External clock on OSC1 is 6MHz
– PTA3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
– External clock on OSC1 is 6MHz
– IRQ = VDD
Table 10-1. Mode Entry Requirements and Options
IRQ
$FFFE
and
$FFFF
PTA3
PTA2
PTA1
PTA0
Bus
Frequency,
fBUS
External Clock,
fXCLK
VDD + VHI
X
0
0
1
1
3MHz
3MHz
(fXCLK)
VDD + VHI
X
1
0
1
1
6MHz
3MHz
(fXCLK ÷ 2)
VDD
BLANK
(contain
$FF)
6MHz
3MHz
(fXCLK ÷ 2)
Low-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
VDD
NOT
BLANK
6MHz
3MHz
(fXCLK ÷ 2)
Enters user mode.
If $FFFE and $FFFF is
blank, MCU will encounter
an illegal address reset.
X
X
X
X
X
X
1
X
Comments
High-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
Notes:
1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using VDD + VHI for monitor mode entry.
2. See Section 18. Electrical Specifications for VDD + VHI voltage level requirements.
Technical Data
166
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor
Monitor ROM (MON)
Functional Description
If VDD +VHI is applied to IRQ and PTA3 is low upon monitor mode entry
(Table 10-1 condition set 1), the bus frequency is a equal to the external
clock, fXCLK. If PTA3 is high with VDD +VHI applied to IRQ upon monitor
mode entry (Table 10-1 condition set 2), the bus frequency is a divideby-two of the external clock. Holding the PTA3 pin low when entering
monitor mode causes a bypass of a divide-by-two stage at the oscillator
only if VDD +VHI is applied to IRQ. In this event, the OSCOUT frequency
is equal to the OSCXCLK frequency.
Entering monitor mode with VDD + VHI on IRQ, the COP is disabled as
long as VDD + VHI is applied to either the IRQ or the RST. (See Section
8. System Integration Module (SIM) for more information on modes of
operation.)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF) (Table 10-1 condition set 3, where IRQ
applied voltage is VDD), then all port A pin requirements and conditions,
including the PTA3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
Figure 10-2. shows a simplified diagram of the monitor mode entry when
the reset vector is blank and IRQ = VDD. An external clock of 6MHz is
required for a baud rate of 9600.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Monitor ROM (MON)
Technical Data
167
Monitor ROM (MON)
POR RESET
IS VECTOR
BLANK?
NO
NORMAL USER
MODE
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
POR
TRIGGERED?
NO
YES
Figure 10-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See 10.5 Security.) After the security bytes, the MCU sends a
break signal (10 consecutive logic zeros) to the host, indicating that it is
ready to receive a command. The break signal also provides a timing
reference to allow the host to determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and
break interrupt. The alternate vectors are in the $FE page instead of the
$FF page and allow code execution from the internal monitor firmware
instead of user code.
Technical Data
168
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor
Monitor ROM (MON)
Functional Description
Table 10-2 is a summary of the vector differences between user mode
and monitor mode.
Table 10-2. Monitor Mode Vector Differences
Functions
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
Modes
Notes:
1. If the high voltage (VDD + VHI) is removed from the IRQ pin or the RST pin, the SIM
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
10.4.2 Baud Rate
The communication baud rate is dependant on oscillator frequency,
fXCLK. The state of PTA3 also affects baud rate if entry to monitor mode
is by IRQ = VDD + VHI. When PTA3 is high, the divide by ratio is 625. If
the PTA3 pin is at logic zero upon entry into monitor mode, the divide by
ratio is 312.
Table 10-3. Monitor Baud Rate Selection
Monitor Mode
Entry By:
IRQ = VDD + VHI
Blank reset vector,
IRQ = VDD
Oscillator Clock
Frequency, fCLK
PTA3
Baud Rate
3 MHz
0
9600 bps
6 MHz
1
9600 bps
3 MHz
1
4800 bps
6 MHz
X
9600 bps
3 MHz
X
4800 bps
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Monitor ROM (MON)
Technical Data
169
Monitor ROM (MON)
10.4.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 10-3 and Figure 10-4.)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
STOP
BIT
BIT 7
NEXT
START
BIT
Figure 10-3. Monitor Data Format
$A5
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BREAK
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
STOP
BIT
NEXT
START
BIT
NEXT
START
BIT
Figure 10-4. Sample Monitor Waveforms
The data transmit and receive rate can be anywhere from 4800 baud to
28.8k-baud. Transmit and receive baud rates must be identical.
10.4.4 Echoing
As shown in Figure 10-5, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
SENT TO
MONITOR
READ
READ
ADDR. HIGH ADDR. HIGH
ADDR. LOW
ECHO
ADDR. LOW
DATA
RESULT
Figure 10-5. Read Transaction
Any result of a command appears after the echo of the last byte of the
command.
Technical Data
170
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor
Monitor ROM (MON)
Functional Description
10.4.5 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 10-6.)
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 10-6. Break Transaction
10.4.6 Commands
The monitor ROM uses the following commands:
•
READ (read memory)
•
WRITE (write memory)
•
IREAD (indexed read)
•
IWRITE (indexed write)
•
READSP (read stack pointer)
•
RUN (run user program)
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Monitor ROM (MON)
Technical Data
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Monitor ROM (MON)
Table 10-4. READ (Read Memory) Command
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of specified address
Opcode
$4A
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
ECHO
DATA
RESULT
Table 10-5. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
None
Opcode
$49
Command Sequence
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
Technical Data
172
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor
Monitor ROM (MON)
Functional Description
Table 10-6. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of next two addresses
Opcode
$1A
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
Table 10-7. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
None
Opcode
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
NOTE:
A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-Kbyte memory map.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Monitor ROM (MON)
Technical Data
173
Monitor ROM (MON)
Table 10-8. READSP (Read Stack Pointer) Command
Description
Reads stack pointer
Operand
None
Data Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
Table 10-9. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
Technical Data
174
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor
Monitor ROM (MON)
Security
10.5 Security
A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data.
NOTE:
Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTA0. If the received
bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code
from FLASH. Security remains bypassed until a power-on reset occurs.
If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. (See Figure 10-7.)
VDD
4096 + 32 OSCXCLK CYCLES
RST
COMMAND
BYTE 8
BYTE 2
BYTE 1
24 BUS CYCLES
FROM HOST
PTA0
4
BREAK
2
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
1
COMMAND ECHO
1
BYTE 8 ECHO
BYTE 1 ECHO
FROM MCU
1
BYTE 2 ECHO
4
1
Figure 10-7. Monitor Mode Entry Timing
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Monitor ROM (MON)
Technical Data
175
Monitor ROM (MON)
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $40 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on
reset and brought up in monitor mode to attempt another entry. After
failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal
RAM. The mass erase operation clears the security code locations so
that all eight security bytes become $FF (blank).
Technical Data
176
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 11. Timer Interface Module (TIM)
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.5.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 182
11.5.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .183
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 183
11.5.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 184
11.5.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 185
11.5.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
11.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 188
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.9.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .189
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) . . . . . . . 189
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 190
11.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 193
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 194
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
177
Timer Interface Module (TIM)
11.2 Introduction
This section describes the timer interface module (TIM2, Version B). The
TIM is a 2-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions.
Figure 11-1 is a block diagram of the TIM.
11.3 Features
Features of the TIM include:
•
Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
•
Buffered and unbuffered pulse width modulation (PWM) signal
generation
•
Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
– External TIM clock input (bus frequency ÷2 maximum)
•
Free-running or modulo up-count operation
•
Toggle any channel pin on overflow
•
TIM counter stop and reset bits
11.4 Pin Name Conventions
The TIM share three I/O pins with three port E I/O pins. The full name of
the TIM I/O pin is listed in Table 11-1. The generic pin name appear in
the text that follows.
Table 11-1. TIM Pin Name Conventions
Technical Data
178
TIM Generic Pin Names:
TCLK
TCH0
TCH1
Full TIM Pin Names:
PTE0/TCLK
PTE1/TCH0
PTE2/TCH1
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Timer Interface Module (TIM)
Freescale Semiconductor
Timer Interface Module (TIM)
Functional Description
11.5 Functional Description
Figure 11-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
The two TIM channels are programmable independently as input
capture or output compare channels.
TCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CHANNEL 0
ELS0B
ELS0A
CH0MAX
16-BIT COMPARATOR
TCH0H:TCH0L
PORT
LOGIC
TCH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CH0IE
MS0B
INTERNAL BUS
TOV1
CHANNEL 1
ELS1B
ELS1A
CH1MAX
PORT
LOGIC
TCH1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1F
INTERRUPT
LOGIC
16-BIT LATCH
MS1A
CH1IE
Figure 11-1. TIM Block Diagram
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
179
Timer Interface Module (TIM)
Addr.
$000A
$000C
$000D
Register Name
TIM Status and Control
Register
(TSC)
TIM Counter Register High
(TCNTH)
TIM Counter Register Low
(TCNTL)
Bit 7
Read:
$000E
TIM Counter Modulo
Register Low
(TMODL)
$000F
$0010
TIM Channel 0 Status and
Control Register
(TSC0)
TIM Channel 0
Register High
(TCH0H)
$0011
TIM Channel 0
Register Low
(TCH0L)
$0012
$0013
TIM Channel 1 Status and
Control Register
(TSC1)
5
TOIE
TSTOP
TOF
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
Write:
0
Reset:
0
0
1
0
0
0
0
0
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TRST
Reset:
0
0
0
0
0
0
0
0
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Reset:
1
1
1
1
1
1
1
1
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
0
0
0
0
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Write:
Write:
Reset:
TIM Counter Modulo
Register High
(TMODH)
6
Read:
Write:
Reset:
Read:
Write:
Read:
Write:
Reset:
Indeterminate after reset
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Write:
Reset:
Read:
Indeterminate after reset
CH1F
0
CH1IE
Write:
0
Reset:
0
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
= Unimplemented
Figure 11-2. TIM I/O Register Summary
Technical Data
180
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Timer Interface Module (TIM)
Freescale Semiconductor
Timer Interface Module (TIM)
Functional Description
$0014
$0015
TIM Channel 1
Register High
(TCH1H)
TIM Channel 1
Register Low
(TCH1L)
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Write:
Reset:
Indeterminate after reset
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 11-2. TIM I/O Register Summary
11.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, PTE0/TCLK. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register (TSC) select the TIM clock source.
11.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
11.5.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
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Timer Interface Module (TIM)
11.5.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 11.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
Technical Data
182
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
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Timer Interface Module (TIM)
Functional Description
11.5.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE1/TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the PTE1/TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (0 or 1) that control
the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
PTE2/TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
11.5.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 11-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
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Timer Interface Module (TIM)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHxA
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 11-3. PWM Period and Pulse Width
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is 000 (see 11.10.1 TIM Status and Control Register).
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
11.5.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 11.5.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
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Timer Interface Module (TIM)
Functional Description
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
NOTE:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output
compares to occur in the same PWM period.
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
11.5.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE1/TCH0 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the PTE1/TCH0 pin. Writing to the TIM
channel 1 registers enables the TIM channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls
and monitors the buffered PWM function, and TIM channel 1 status and
control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, PTE2/TCH1, is available as a general-purpose I/O pin.
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Timer Interface Module (TIM)
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
11.5.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use this initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset
bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB:MSxA. (See Table 11-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 11-3.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
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Timer Interface Module (TIM)
Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output. (See 11.10.4 TIM
Channel Status and Control Registers.)
11.6 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter reaches the modulo value programmed in the TIM counter
modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are
in the TIM status and control register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM
channel x status and control register.
11.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
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Timer Interface Module (TIM)
11.7.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
11.7.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
11.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 8.8.3 Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
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Timer Interface Module (TIM)
I/O Signals
11.9 I/O Signals
Port E shares three of its pins with the TIM. PTE0/TCLK is an external
clock input to the TIM prescaler. The two TIM channel I/O pins are
PTE1/TCH0 and PTE2/TCH1.
11.9.1 TIM Clock Pin (PTE0/TCLK)
PTE0/TCLK is an external clock input that can be the clock source for
the TIM counter instead of the prescaled internal bus clock. Select the
PTE0/TCLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See 11.10.1 TIM Status and Control Register.) The minimum
TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t SU
bus frequency
The maximum TCLK frequency is:
bus frequency ÷ 2
PTE0/TCLK is available as a general-purpose I/O pin when not used as
the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it
is an input regardless of the state of the DDRE0 bit in data direction
register E.
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0 can be configured as
buffered output compare or buffered PWM pins.
11.10 I/O Registers
The following I/O registers control and monitor operation of the TIM:
•
TIM status and control register (TSC)
•
TIM counter registers (TCNTH:TCNTL)
•
TIM counter modulo registers (TMODH:TMODL)
•
TIM channel status and control registers (TSC0 and TSC1)
•
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
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Timer Interface Module (TIM)
11.10.1 TIM Status and Control Register
The TIM status and control register:
•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
Address:
$000A
Bit 7
Read:
6
5
TOIE
TSTOP
TOF
Write:
0
Reset:
0
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
TRST
0
1
0
0
= Unimplemented
Figure 11-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a
logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
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Timer Interface Module (TIM)
I/O Registers
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTE0/TCLK pin or one of the
seven prescaler outputs as the input to the TIM counter as
Table 11-2 shows. Reset clears the PS[2:0] bits.
Table 11-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
0
0
Internal Bus Clock ÷1
0
0
1
Internal Bus Clock ÷ 2
0
1
0
Internal Bus Clock ÷ 4
0
1
1
Internal Bus Clock ÷ 8
1
0
0
Internal Bus Clock ÷ 16
1
0
1
Internal Bus Clock ÷ 32
1
1
0
Internal Bus Clock ÷ 64
1
1
1
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PTE0/TCLK
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Timer Interface Module (TIM)
11.10.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
TCNTH
Read:
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
TCNTL
Read:
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 11-5. TIM Counter Registers (TCNTH:TCNTL)
Technical Data
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Timer Interface Module (TIM)
I/O Registers
11.10.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH)
inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is
written. Reset sets the TIM counter modulo registers.
TMODH
Address: $000E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
TMODL
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 11-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
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Timer Interface Module (TIM)
11.10.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 0% and 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
TSC0
Address: $0010
Bit 7
Read:
CH0F
Write:
0
Reset:
0
TSC1
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
5
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Address: $0013
Bit 7
Read:
6
6
CH1F
0
CH1IE
Write:
0
Reset:
0
0
0
= Unimplemented
Figure 11-7. TIM Channel Status and Control Registers
(TSC0:TSC1)
Technical Data
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Timer Interface Module (TIM)
I/O Registers
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic 0 to CHxF has no effect. Therefore, an interrupt request cannot
be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input
capture operation or unbuffered output compare/PWM operation.
See Table 11-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
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Timer Interface Module (TIM)
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output
level of the TCHx pin. (See Table 11-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E, and pin PTEx/TCHx is available as a general-purpose I/O
pin. Table 11-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 11-3. Mode, Edge, and Level Selection
Technical Data
196
MSxB
MSxA
ELSxB ELSxA
X
0
0
0
X
1
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
X
0
1
1
X
1
0
1
X
1
1
Mode
Output
Preset
Configuration
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising edge only
Input
Capture
Capture on falling edge only
Capture on rising or falling edge
Output
Compare
or PWM
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Buffered
Output
Clear output on compare
Compare or
Buffered
Set output on compare
PWM
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Timer Interface Module (TIM)
I/O Registers
NOTE:
Before enabling a TIM channel register for input capture operation, make
sure that the PTEx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 11-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 11-8. CHxMAX Latency
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
197
Timer Interface Module (TIM)
11.10.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
TCH0H
Read:
Write:
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
TCH0L
Read:
Write:
Indeterminate after reset
Address:
$0012
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset:
TCH1H
Read:
Write:
Indeterminate after reset
Address:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset:
TCH1L
Read:
Write:
Reset:
Indeterminate after reset
Address:
$0015
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset
Figure 11-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
Technical Data
198
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Timer Interface Module (TIM)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 12. Input/Output Ports (I/O)
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 203
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . 205
12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 208
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
12.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 211
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
12.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 215
12.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
12.8.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .217
12.2 Introduction
Thirty-seven (37) bidirectional input-output (I/O) pins form five parallel
ports. All I/O pins are programmable as inputs or outputs.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Input/Output Ports (I/O)
Technical Data
199
Input/Output Ports (I/O)
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VREG
or VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0000
Port A Data Register Read:
(PTA)
Write:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Reset:
$0001
Port B Data Register Read:
(PTB)
Write:
Unaffected by reset
PTB7
PTB6
PTB5
Reset:
$0002
Port C Data Register Read:
(PTC)
Write:
Port D Data Register Read:
(PTD)
Write:
PTC7
PTC6
PTC5
PTC4
PTC3
Unaffected by reset
PTD7
PTD6
PTD5
Reset:
PTD4
PTD3
Unaffected by reset
$0004 Data Direction Register A Read:
DDRA7
(DDRA)
Write:
Reset:
PTB3
Unaffected by reset
Reset:
$0003
PTB4
0*
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
PTE4
PTE3
PTE2
PTE1
PTE0
* DDRA7 bit is reset by POR or LVI reset only.
$0005 Data Direction Register B Read:
DDRB7
(DDRB)
Write:
Reset:
0
$0006 Data Direction Register C Read:
DDRC7
(DDRC)
Write:
Reset:
0
$0007 Data Direction Register D Read:
DDRD7
(DDRD)
Write:
$0008
Reset:
0
0
0
Port E Data Register Read:
(PTE)
Write:
0
0
0
Reset:
Unaffected by reset
= Unimplemented
Figure 12-1. I/O Port Register Summary
Technical Data
200
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Introduction
Addr.
Register Name
Bit 7
6
5
$0009 Data Direction Register E Read:
(DDRE)
Write:
0
0
0
Reset:
0
0
0
$001D
Read:
Port Option Control
PTE20P
Register Write:
(POCR)
Reset:
0
PTDLDD PTDILDD
0
4
3
2
1
Bit 0
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
PTE4P
PTE3P
PCP
PBP
PAP
0
0
0
0
0
0
= Unimplemented
Figure 12-1. I/O Port Register Summary
Table 12-1. Port Control Register Bits Summary
Port
Module Control
Bit
DDR
0
DDRA0
KBIE0
PTA0/KBA0
1
DDRA1
KBIE1
PTA1/KBA1
2
DDRA2
KBIE2
PTA2/KBA2
3
DDRA3
KBIE3
PTA3/KBA3
A
Module
KBI
Register
Control Bit
Pin
KBIER ($0017)
4
DDRA4
KBIE4
PTA4/KBA4
5
DDRA5
KBIE5
PTA5/KBA5
6
DDRA6
KBIE6
PTA6/KBA6
7
DDRA7
KBIE7
PTA7/KBA7
B
0–7
DDRB[0:7]
—
—
—
PTB0–PTB7
C
0–7
DDRC[0:7]
—
—
—
PTC0–PTC7
D
0–7
DDRD[0:7]
—
—
—
PTD0–PTD7
0
DDRE0
TSC ($000A)
PS[2:0]
PTE0/TCLK
1
DDRE1
TSC0 ($0010)
ELS0B:ELS0A
PTE1/TCH0
2
DDRE2
TSC1 ($0013)
ELS1B:ELS1A
PTE2/TCH1
3
DDRE3
UADDR ($0038)
USBEN
E
TIM
PTE3/D+
USB
4
DDRE4
PTE4/D–
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Input/Output Ports (I/O)
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Input/Output Ports (I/O)
12.3 Port A
Port A is an 8-bit general-purpose bidirectional I/O port with software
configurable pullups, and it shares its pins with the keyboard interrupt
module (KBI).
12.3.1 Port A Data Register
The port A data register contains a data latch for each of the eight port A
pins.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Read:
Write:
Reset:
Alternativ
e
Function:
Unaffected by reset
KBA7
Additional Optional
Function: pullup
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Figure 12-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
The port A pullup enable bit, PAP, in the port option control register
(POCR) enables pullups on port A pins if the respective pin is
configured as an input. (See 12.8 Port Options.)
KBA7–KBA0 — Keyboard Interrupts
The keyboard interrupt enable bits, KBIE7–KBIE0, in the keyboard
interrupt enable register (KBIER), enable the port A pins as external
interrupt pins. (See Section 14. Keyboard Interrupt Module (KBI).)
Technical Data
202
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Port A
12.3.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0*
0
0
0
0
0
0
0
Read:
Write:
Reset:
* DDRA7 bit is reset by POR or LVI reset only.
Figure 12-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Input/Output Ports (I/O)
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Input/Output Ports (I/O)
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes
the operation of the port A pins.
Table 12-2. Port A Pin Functions
DDRA
Bit
PTA Bit
I/O Pin Mode
Accesses
to DDRA
Accesses to PTA
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRA[7:0]
Pin
PTA[7:0](3)
1
X
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
12.4 Port B
Port B is an 8-bit general-purpose bidirectional I/O port with software
configurable pullups.
12.4.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B
pins.
NOTE:
PTB7–PTB0 are not available in the 20-pin PDIP, 20-pin SOIC, and
28-pin SOIC packages.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Optional
pullup
Optional
pullup
Optional
pullup
Read:
Write:
Reset:
Additional Optional
Function: pullup
Unaffected by reset
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Figure 12-5. Port B Data Register (PTB)
Technical Data
204
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Port B
PTB[7:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
The port B pullup enable bit, PBP, in the port option control register
(POCR) enables pullups on port B pins if the respective pin is
configured as an input. (See 12.8 Port Options.)
12.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 12-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
NOTE:
For those devices packaged in a 20-pin PDIP, 20-pin SOIC, and 28-pin
SOIC package, PTB7–PTB0 are not connected. DDRB7–DDRB0
should be set to a 1 to configure PTB7–PTB0 as outputs.
Figure 12-7 shows the port B I/O logic.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Input/Output Ports (I/O)
Technical Data
205
Input/Output Ports (I/O)
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 12-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-3 summarizes
the operation of the port B pins.
Table 12-3. Port B Pin Functions
DDRB
Bit
PTB Bit
I/O Pin Mode
Accesses
to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRB[7:0]
Pin
PTB[7:0](3)
1
X
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Technical Data
206
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Port C
12.5 Port C
Port C is an 8-bit general-purpose bidirectional I/O port with software
configurable pullups and current drive options.
12.5.1 Port C Data Register
The port C data register contains a data latch for each of the eight port C
pins.
NOTE:
PTC7–PTC1 are not available in the 20-pin PDIP, 20-pin SOIC, and
28-pin SOIC packages.
Address:
$0002
Bit 7
6
5
4
3
2
1
Bit 0
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Optional
pullup
Optional
pullup
Optional
pullup
Read:
Write:
Reset:
Additional Optional
Function: pullup
Unaffected by reset
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Figure 12-8. Port C Data Register (PTC)
PTC[7:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
The port C pullup enable bit, PCP, in the port option control register
(POCR) enables pullups on port C pins if the respective pin is
configured as an input. (See 12.8 Port Options.)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Input/Output Ports (I/O)
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207
Input/Output Ports (I/O)
12.5.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for
the corresponding port C pin; a logic 0 disables the output buffer.
Address:
$0006
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 12-9. Data Direction Register C (DDRC)
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
NOTE:
For those devices packaged in a 20-pin PDIP, 20-pin SOIC, and 28-pin
SOIC package, PTC7–PTC1 are not connected. DDRC7–DDRC1
should be set to a 1 to configure PTC7–PTC1 as outputs.
Figure 12-10 shows the port C I/O logic.
Technical Data
208
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Port D
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
READ PTC ($0002)
Figure 12-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes
the operation of the port C pins.
Table 12-4. Port C Pin Functions
DDRC
Bit
PTC Bit
I/O Pin Mode
Accesses
to DDRC
Accesses to PTC
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRC[7:0]
Pin
PTC[7:0](3)
1
X
Output
DDRC[7:0]
PTC[7:0]
PTC[7:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
12.6 Port D
Port D is an 8-bit general-purpose bidirectional I/O port. In 20-pin
package, PTD1 and PTD0 internal pads are bonded together to PTD0/1
pin. Port D pins are open-drain when configured as output, and can
interface with 5V logic.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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Input/Output Ports (I/O)
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Input/Output Ports (I/O)
12.6.1 Port D Data Register
The port D data register contains a data latch for each of the eight port D
pins.
NOTE:
PTD7–PTD2 are not available in the 20-pin PDIP and 20-pin SOIC
packages. PTD7 is not available in the 28-pin SOIC package.
Address:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Read:
Write:
Reset:
Unaffected by reset
Additional Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain
Function:
10mA
10mA
10mA
10mA
25mA
25mA
sink
sink
sink
sink
sink
sink
Figure 12-11. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The LED direct drive bit, PTDLDD, in the port option control register
(POCR) controls the drive options for the PTD5–PTD2 pins. The
infrared LED drive bit, PTDILDD, in the POCR controls the drive
options for the PTD1–PTD0 pins. (See 12.8 Port Options.)
NOTE:
Technical Data
210
In 20-pin package, PTD1 and PTD0 are bonded together to PTD0/1 pin,
forming a 50mA high current sink pin. When both PTD1 and PTD0 are
configured as output, the values of PTD0 and PTD1 should be written
the same.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Port D
12.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
Address:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 12-12. Data Direction Register D (DDRD)
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Port D pins are open-drain when configured as output.
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
NOTE:
For those devices packaged in a 20-pin PDIP and 20-pin SOIC package,
PTD7–PTD2 are not connected. DDRD7–DDRD2 should be set to a 1 to
configure PTD7–PTD2 as outputs.
For those devices packaged in a 28-pin SOIC package, PTD7 is not
connected. DDRD7 should be set to a 1 to configure PTD7 as output.
Figure 12-13 shows the port D I/O circuit logic.
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Input/Output Ports (I/O)
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Input/Output Ports (I/O)
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007)
DDRDx
RESET
WRITE PTD ($0003)
PTDx
PTDx
READ PTD ($0003)
Figure 12-13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-5 summarizes
the operation of the port D pins.
Table 12-5. Port D Pin Functions
DDRD
Bit
PTD Bit
I/O Pin Mode
Accesses
to DDRD
Accesses to PTD
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRD[7:0]
Pin
PTD[7:0](3)
1
X
Output
DDRD[7:0]
PTD[7:0]
PTD[7:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
12.7 Port E
Port E is a 5-bit special function port that shares three of its pins with the
timer interface module (TIM) and two of its pins with the USB data pins
D+ and D–. PTE4 and PTE3 are open drain when configured as output.
Technical Data
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Input/Output Ports (I/O)
Freescale Semiconductor
Input/Output Ports (I/O)
Port E
12.7.1 Port E Data Register
The port E data register contains a data latch for each of the five port E
pins.
NOTE:
PTE2 and PTE0 are not available in the 20-pin PDIP and 20-pin SOIC
packages.
Address:
Read:
$0008
Bit 7
6
5
0
0
0
4
3
2
1
Bit 0
PTE4
PTE3
PTE2
PTE1
PTE0
Write:
Reset:
Unaffected by reset
Alternative
D–
D+
TCH1
TCH0
TCLK
Additional
Function:
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Additional
Function:
External
interrupt
Function:
Open-drain Open-drain
= Unimplemented
Figure 12-14. Port E Data Register (PTE)
PTE[4:0] — Port E Data Bits
PTE[4:0] are read/write, software-programmable bits. Data direction
of each port E pin is under the control of the corresponding bit in data
direction register E.
The PTE4 and PTE3 pullup enable bits, PTE4P and PTE3P, in the
port option control register (POCR) enable 5kΩ pullups on PTE4 and
PTE3 if the respective pin is configured as an input and the USB
module is disabled. (See 12.8 Port Options.)
The PTE[2:0] pullup enable bit, PTE20P, in the port option control
register (POCR) enables pullups on PTE2–PTE0, regardless of the
pin is configured as an input or an output. (See 12.8 Port Options.)
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Input/Output Ports (I/O)
PTE4 pin functions as an external interrupt when PTE4IE=1 in the
IRQ option control register (IOCR) and USBEN=0 in the USB address
register (USB disabled). (See 13.9 IRQ Option Control Register.)
D– and D+ — USB Data Pins
D– and D+ are the differential data lines used by the USB module.
(See Section 9. Universal Serial Bus Module (USB).)
The USB module enable bit, USBEN, in the USB address register
(UADDR) controls the pin options for PTE4/D– and PTE3/D+. When
the USB module is enabled, PTE4/D– and PTE3/D+ function as USB
data pins D– and D+. When the USB module is disabled, PTE4/D–
and PTE3/D+ function as 10mA open-drain pins for PS/2 clock and
data use.
The Pullup enable bit, PULLEN, in the USB control register 3 (UCR3)
enables a 1.5kΩ pullup on D– pin when the USB module is enabled.
(See 9.8.8 USB Control Register 3.)
NOTE:
PTE4/D– pin has two programmable pullup resistors. One is used for
PTE4 when the USB module is disabled and another is used for D–
when the USB module is enabled.
TCH1–TCH0 — Timer Channel I/O Bits
The PTE2/TCH1–PTE1/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB and ELSxA,
determine whether the PTE2/TCH1–PTE1/TCH0 pins are timer
channel I/O pins or general-purpose I/O pins. (See Section 11. Timer
Interface Module (TIM).)
TCLK — Timer Clock Input
The PTE0/TCLK pin is the external clock input for the TIM. The
prescaler select bits, PS[2:0], select PTE0/TCLK as the TIM clock
input. When not selected as the TIM clock, PTE0/TCLK is available
for general purpose I/O. (See Section 11. Timer Interface Module
(TIM).)
NOTE:
Technical Data
214
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins.
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Input/Output Ports (I/O)
Port E
12.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address:
Read:
$0009
Bit 7
6
5
0
0
0
4
3
2
1
Bit 0
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 12-15. Data Direction Register E (DDRE)
DDRE[4:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[4:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
PTE4 and PTE3 pins are open-drain when configured as output.
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
NOTE:
For those devices packaged in a 20-pin PDIP and 20-pin SOIC package,
PTE2 and PTE0 are not connected. DDRE2 and DDRE0 should be set
to a 1 to configure PTE2 and PTE0 as outputs.
Figure 12-16 shows the port E I/O circuit logic.
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Input/Output Ports (I/O)
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Input/Output Ports (I/O)
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C)
DDREx
RESET
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 12-16. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes
the operation of the port E pins.
Table 12-6. Port E Pin Functions
DDRE
Bit
PTE
Bit
I/O Pin Mode
Accesses
to DDRE
Accesses to PTE
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRE[4:0]
Pin
PTE[4:0](3)
1
X
Output
DDRE[4:0]
PTE[4:0]
PTE[4:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
12.8 Port Options
All pins of port A, port B, port C, and port E have programmable pullup
resistors. Port pins PTD5–PTD0 have LED drive capability. Port pins
PTE4 and PTE3 have 10mA high current drive capability.
Technical Data
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Input/Output Ports (I/O)
Port Options
12.8.1 Port Option Control Register
The port option control register controls the pullup options for port A, B,
C, and E pins. It also controls the drive configuration on port D.
Address:
$001D
Bit 7
6
5
4
3
2
1
Bit 0
PTE4P
PTE3P
PCP
PBP
PAP
0
0
0
0
0
Read:
PTE20P
PTDLDD PTDILDD
Write:
Reset:
0
0
0
Figure 12-17. Port Option Control Register (POCR)
PTE20P — Port PTE2–PTE0 Pullup Enable
This read/write bit controls the pullup option for the PTE2–PTE0 pins,
regardless whether the pins are input or output.
1 = Configure PTE2–PTE0 to have internal pullups to VREG
0 = Disconnect PTE2–PTE0 internal pullups
PTDLDD — LED Direct Drive Control
This read/write bit controls the output current capability of
PTD5–PTD2 pins. When set, each port pin has 10mA current sink
limit. An LED can be connected directly between the port pin and VDD
without the need of a series resistor.
1 = PTD5–PTD2 configured for direct LED drive capability;
when a pin is set as an output, the pin is an open-drain pin with
10mA current sink limit
0 = PTD5–PTD2 configured as standard open-drain I/O port pin
PTDILDD — Infrared LED Drive Control
This read/write bit controls the output current capability of PTD1 and
PTD0 pins. When set, each port pin has 25mA current sink capability.
An infrared LED can be connected directly between the port pin and
VDD.
1 = PTD1 and PTD0 configured for infrared LED drive capability;
when a pin is set as an output, the pin is an open-drain pin with
25mA current sink capability
0 = PTD1 and PTD0 configured as standard open-drain I/O port
pins
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Input/Output Ports (I/O)
PTE4P — Pin PTE4 Pullup Enable
This read/write bit controls the pullup option for the PTE4 pin when the
pin is configured as an input and the USB module is disabled.
1 = Configure PTE4 to have internal pullup to VDD
0 = Disconnect PTE4 internal pullup
NOTE:
When the USB module is enabled, the pullup controlled by PTE4P is
disconnected; PTE4/D– pin functions as D– which has a 1.5kΩ
programmable pullup resistor. (See 9.8.8 USB Control Register 3.)
PTE3P — Pin PTE3 Pullup Enable
This read/write bit controls the pullup option for the PTE3 pin when the
pin is configured as an input and the USB module is disabled.
1 = Configure PTE3 to have internal pullup to VDD
0 = Disconnect PTE3 internal pullup
PCP — Port C Pullup Enable
This read/write bit controls the pullup option for the PTC7–PTC0 pins.
When set, a pullup device is connected when a pin is configured as
an input.
1 = Configure port C to have internal pullups to VREG
0 = Disconnect port C internal pullups
PBP — Port B Pullup Enable
This read/write bit controls the pullup option for the PTB7–PTB0 pins.
When set, a pullup device is connected when a pin is configured as
an input.
1 = Configure port B to have internal pullups to VREG
0 = Disconnect port B internal pullups
PAP — Port A Pullup Enable
This read/write bit controls the pullup option for the PTA7–PTA0 pins.
When set, a pullup device is connected when a pin is configured as
an input.
1 = Configure port A to have internal pullups to VREG
0 = Disconnect port A internal pullups
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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 13. External Interrupt (IRQ)
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
13.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
13.5
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.6
PTE4/D– Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
13.7
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 223
13.8
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 224
13.9
IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 225
13.2 Introduction
The IRQ module provides two external interrupt inputs: one dedicated
IRQ pin and one shared port pin, PTE4/D–.
13.3 Features
Features of the IRQ module include:
•
Two external interrupt pins, IRQ (5V) and PTE4/D– (5V)
•
IRQ interrupt control bits
•
Hysteresis buffer
•
Programmable edge-only or edge and level interrupt sensitivity
•
Automatic interrupt acknowledge
•
Low leakage IRQ pin for external RC wake up input
•
Selectable internal pullup resistor
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External Interrupt (IRQ)
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External Interrupt (IRQ)
13.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 13-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
•
Software clear — Software can clear the interrupt latch by writing
to the acknowledge bit in the interrupt status and control register
(ISCR). Writing a logic 1 to the ACK bit clears the IRQ latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or low-level-triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains set until both of the following occur:
•
Vector fetch or software clear
•
Return of the interrupt pin to logic one
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
NOTE:
Technical Data
220
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 8.6
Exception Control.)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
External Interrupt (IRQ)
Freescale Semiconductor
External Interrupt (IRQ)
Functional Description
INTERNAL ADDRESS BUS
ACK
RESET
VECTOR
FETCH
DECODER
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VDD
IRQPD
"1"
IRQF
INTERNAL
PULLUP
D
DEVICE
IRQ
CLR
Q
SYNCHRONIZER
CK
IRQ
INTERRUPT
REQUEST
IRQ
FF
IMASK
MODE
TO PTE4 PULLUP
ENABLE CIRCUITRY
"1"
READ IOCR
D
PTE4
CLR
Q
PTE4IF
CK
PTE4IE
Figure 13-1. IRQ Module Block Diagram
Addr.
$001C
$001E
Register Name
Bit 7
6
5
4
3
2
IRQ Option Control Register Read:
(IOCR) Write:
0
0
0
0
0
PTE4IF
Reset:
0
0
0
0
0
0
IRQ Status and Control Register Read:
(ISCR) Write:
0
0
0
0
IRQF
0
Reset:
0
1
Bit 0
PTE4IE
IRQPD
0
0
IMASK
MODE
0
0
ACK
0
0
0
0
0
= Unimplemented
Figure 13-2. IRQ I/O Register Summary
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External Interrupt (IRQ)
Technical Data
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External Interrupt (IRQ)
13.5 IRQ Pin
The IRQ pin has a low leakage for input voltages ranging from 0V to
VDD; suitable for applications using RC discharge circuitry to wake up
the MCU.
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur
to clear IRQ:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ pin and require
software to clear the IRQ latch. Writing to the ACK bit prior to
leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ pin. A falling edge that occurs after writing
to the ACK bit latches another interrupt request. If the IRQ mask
bit, IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFF8 and $FFF9.
•
Return of the IRQ pin to logic one — As long as the IRQ pin is at
logic zero, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic
one may occur in any order. The interrupt request remains pending as
long as the IRQ pin is at logic zero. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Technical Data
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External Interrupt (IRQ)
Freescale Semiconductor
External Interrupt (IRQ)
PTE4/D– Pin
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE:
An internal pullup resistor to VDD is connected to IRQ pin; this can be
disabled by setting the IRQPD bit in the IRQ option control register
($001C).
13.6 PTE4/D– Pin
The PTE4 pin is configured as an interrupt input to trigger the IRQ
interrupt when the following conditions are satisfied:
•
The USB module is disabled (USBEN = 0)
•
PTE4 pin configured for external interrupt input (PTE4IE = 1)
Setting PTE4IE configures the PTE4 pin to an input pin with an internal
pullup device. The PTE4 interrupt is "ORed" with the IRQ input to trigger
the IRQ interrupt (see Figure 13-1 . IRQ Module Block Diagram).
Therefore, the IRQ status and control register affects both the IRQ pin
and the PTE pin. An interrupt on PTE4 also sets the PTE4 interrupt flag,
PTE4IF, in the IRQ option control register (IOCR).
13.7 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can
be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear the latches during the break
state. (See Section 8. System Integration Module (SIM).)
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
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External Interrupt (IRQ)
Technical Data
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External Interrupt (IRQ)
13.8 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has the following functions:
•
Shows the state of the IRQ flag
•
Clears the IRQ latch
•
Masks IRQ interrupt request
•
Controls triggering sensitivity of the IRQ pin
Address:
Read:
$001E
Bit 7
6
5
4
3
2
0
0
0
0
IRQF
0
Write:
Reset:
1
Bit 0
IMASK
MODE
0
0
ACK
0
0
0
0
0
0
= Unimplemented
Figure 13-3. IRQ Status and Control Register (ISCR)
IRQF — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
Technical Data
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External Interrupt (IRQ)
Freescale Semiconductor
External Interrupt (IRQ)
IRQ Option Control Register
0 = IRQ interrupt requests on falling edges only
13.9 IRQ Option Control Register
The IRQ option control register controls and monitors the external
interrupt function available on the PTE4 pin. It also disables/enables the
pullup resistor on the IRQ pin.
•
Controls pullup option on IRQ pin
•
Enables PTE4 pin for external interrupts to IRQ
•
Shows the state of the PTE4 interrupt flag
Address:
Read:
$001C
Bit 7
6
5
4
3
2
0
0
0
0
0
PTE4IF
1
Bit 0
PTE4IE
IRQPD
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 13-4. IRQ Option Control Register (IOCR)
PTE4IF — PTE4 Interrupt Flag
This read-only status bit is high when a falling edge on PTE4 pin is
detected. PTE4IF bit clears when the IOCR is read.
1 = Falling edge on PTE4 is detected and PTE4IE is set
0 = Falling edge on PTE4 is not detected or PTE4IE is clear
PTE4IE — PTE4 Interrupt Enable
This read/write bit enables or disables the interrupt function on the
PTE4 pin to trigger the IRQ interrupt. Setting the PTE4IE bit and
clearing the USBEN bit in the USB address register configure the
PTE4 pin for interrupt function to the IRQ interrupt. Setting PTE4IE
also enables the internal pullup on PTE4 pin.
1 = PTE4 interrupt enabled; triggers IRQ interrupt
0 = PTE4 interrupt disabled
IRQPD — IRQ Pullup Disable
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External Interrupt (IRQ)
Technical Data
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External Interrupt (IRQ)
This read/write bit controls the pullup option for the IRQ pin.
1 = Internal pullup is disconnected
0 = Internal pull-up is connected between IRQ pin and VDD
Technical Data
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
External Interrupt (IRQ)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
14.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
14.6
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.8
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 233
14.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
14.9.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 233
14.9.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 235
14.2 Introduction
The keyboard interrupt module (KBI) provides eight independently
maskable external interrupts which are accessible via PTA0–PTA7 pins.
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Keyboard Interrupt Module (KBI)
14.3 Features
Features of the keyboard interrupt module include:
•
Eight keyboard interrupt pins with separate keyboard interrupt
enable bits and one keyboard interrupt mask
•
Hysteresis buffers
•
Programmable edge-only or edge- and level-interrupt sensitivity
•
Exit from low-power modes
14.4 Pin Name Conventions
The KBI share eight I/O pins with eight port A I/O pins. The full name of
the I/O pins are listed in Table 14-1. The generic pin name appear in the
text that follows.
Table 14-1. KBI Pin Name Conventions
Technical Data
228
Full KBI Pin Names:
KBI Generic Pin Names:
PTA7/KBA7
KBA7
PTA7/KBA6
KBA6
PTA7/KBA5
KBA5
PTA7/KBA4
KBA4
PTA7/KBA3
KBA3
PTA7/KBA2
KBA2
PTA7/KBA1
KBA1
PTA7/KBA0
KBA0
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Keyboard Interrupt Module (KBI)
Freescale Semiconductor
Keyboard Interrupt Module (KBI)
Pin Name Conventions
INTERNAL BUS
KBA0
ACKK
VREG
VECTOR FETCH
DECODER
KEYF
RESET
.
KBIE0
D
CLR
Q
SYNCHRONIZER
.
Keyboard
Interrupt
Request
CK
TO PULLUP ENABLE
.
KEYBOARD
INTERRUPT FF
KBA7
IMASKK
MODEK
KBIE7
TO PULLUP ENABLE
Figure 14-1. Keyboard Module Block Diagram
Table 14-2. I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
$0016 Keyboard Status and Control Read:
Register
(KBSCR) Write:
0
0
0
0
KEYF
0
Reset:
0
0
0
0
0
KBIE7
KBIE6
KBIE5
KBIE4
0
0
0
0
$0017
Keyboard Interrupt Enable Read:
Register
(KBIER) Write:
Reset:
1
Bit 0
IMASKK
MODEK
0
0
0
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
ACKK
= Unimplemented
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Keyboard Interrupt Module (KBI)
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Keyboard Interrupt Module (KBI)
14.5 Functional Description
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port A pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin also enables its internal
pullup device. A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
NOTE:
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low.
•
If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
To prevent losing an interrupt request on one pin because another pin is
still low, software can disable the latter pin while it is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
•
Technical Data
230
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (KBSCR). The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine also can prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFF0 and
$FFF1.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Keyboard Interrupt Module (KBI)
Freescale Semiconductor
Keyboard Interrupt Module (KBI)
Keyboard Initialization
•
Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
14.6 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the pullup
device to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
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Keyboard Interrupt Module (KBI)
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Keyboard Interrupt Module (KBI)
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in data direction register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
14.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
14.7.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
14.7.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
Technical Data
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Keyboard Interrupt Module (KBI)
Freescale Semiconductor
Keyboard Interrupt Module (KBI)
Keyboard Module During Break Interrupts
14.8 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state.
To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect. (See 14.9.1 Keyboard Status and
Control Register.)
14.9 I/O Registers
These registers control and monitor operation of the keyboard module:
•
Keyboard status and control register (KBSCR)
•
Keyboard interrupt enable register (KBIER)
14.9.1 Keyboard Status and Control Register
The keyboard status and control register:
•
Flags keyboard interrupt requests
•
Acknowledges keyboard interrupt requests
•
Masks keyboard interrupt requests
•
Controls keyboard interrupt triggering sensitivity
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Keyboard Interrupt Module (KBI)
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Keyboard Interrupt Module (KBI)
Address: $0016
Read:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Write:
Reset:
1
Bit 0
IMASKK
MODEK
0
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 14-2. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
Technical Data
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Keyboard Interrupt Module (KBI)
Freescale Semiconductor
Keyboard Interrupt Module (KBI)
I/O Registers
14.9.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A
pin to operate as a keyboard interrupt pin.
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 14-3. Keyboard Interrupt Enable Register (KBIER)
KBIE7–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PTAx pin enabled as keyboard interrupt pin
0 = PTAx pin not enabled as keyboard interrupt pin
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Keyboard Interrupt Module (KBI)
Technical Data
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Keyboard Interrupt Module (KBI)
Technical Data
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Keyboard Interrupt Module (KBI)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 15. Computer Operating Properly (COP)
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
15.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 240
15.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 242
15.2 Introduction
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG register.
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Computer Operating Properly (COP)
15.3 Functional Description
Figure 15-1 shows the structure of the COP module.
SIM
OSCXCLK
SIM RESET CIRCUIT
RESET VECTOR FETCH
RESET STATUS REGISTER
COP TIMEOUT
CLEAR ALL STAGES
INTERNAL RESET SOURCES(1)
CLEAR STAGES 5–12
12-BIT SIM COUNTER
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG)
RESET
COPCTL WRITE
CLEAR
COP COUNTER
COP RATE SEL
(COPRS FROM CONFIG)
NOTE:
1. See SIM section for more details.
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
218 – 24 or 213 – 24 OSCXCLK cycles, depending on the state of the
COP rate select bit, COPRS in the configuration register. With a 218 – 24
OSCXCLK cycle overflow option (COPRS = 0), a 12MHz OSCXCLK
clock (6MHz crystal) gives a COP timeout period of 21.84 ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
Technical Data
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Computer Operating Properly (COP)
Freescale Semiconductor
Computer Operating Properly (COP)
I/O Signals
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at VDD + VHI. During the break state, VDD + VHI on the RST pin disables
the COP.
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
15.4 I/O Signals
The following paragraphs describe the signals shown in Figure 15-1.
15.4.1 OSCXCLK
OSCXCLK is the clock doubler output signal. OSCXCLK frequency is
double of the crystal frequency.
15.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
15.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 15.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
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Computer Operating Properly (COP)
15.4.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the COP prescaler
4096 OSCXCLK cycles after power-up.
15.4.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
15.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
15.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG).
15.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register (CONFIG).
Address:
Read:
$001F
Bit 7
6
0
0
5
4
3
2
1
Bit 0
URSTD
LVID
SSREC
COPRS
STOP
COPD
0
0
0
0
0
0
Write:
Reset:
0
0
= Unimplemented
Figure 15-2. Configuration Register (CONFIG)
Technical Data
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Computer Operating Properly (COP)
Freescale Semiconductor
Computer Operating Properly (COP)
COP Control Register
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (213 – 24) × OSCXOUT cycles
0 = COP timeout period is (218 – 24) × OSCXOUT cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
15.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
2
1
Bit 0
Figure 15-3. COP Control Register (COPCTL)
15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when VDD + VHI is present on the
IRQ pin or on the RST pin.
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Computer Operating Properly (COP)
15.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
15.8.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.
15.8.2 Stop Mode
Stop mode turns off the OSCXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
15.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VDD + VHI is present
on the RST pin.
Technical Data
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Computer Operating Properly (COP)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 16. Low Voltage Inhibit (LVI)
16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.4
LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.2 Introduction
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the VDD pin and generates a reset when the VDD
voltage falls to the LVI trip (VLVR) voltage.
16.3 Functional Description
Figure 16-1 shows the structure of the LVI module. The LVI is enabled
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
VDD voltage.
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
VDD drops to below the set trip point.
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Low Voltage Inhibit (LVI)
Technical Data
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Low Voltage Inhibit (LVI)
VDD
LVID
LOW VDD
VDD > VLVR = 0
DETECTOR
VDD < VLVR = 1
LVI RESET
Figure 16-1. LVI Module Block Diagram
16.4 LVI Control Register (CONFIG)
Address:
Read:
$001F
Bit 7
6
0
0
5
4
3
2
1
Bit 0
URSTD
LVID
SSREC
COPRS
STOP
COPD
0
0
0
0
0
0
Write:
Reset:
0
0
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
= Unimplemented
Figure 16-2. Configuration Register (CONFIG)
LVID —þLow Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
16.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
16.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
16.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
Technical Data
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Low Voltage Inhibit (LVI)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 17. Break Module (BREAK)
17.1 Contents
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 248
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .248
17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 248
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 248
17.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
17.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
17.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . . 249
17.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
17.6.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . 252
17.2 Introduction
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Break Module (BREAK)
Technical Data
245
Break Module (BREAK)
17.3 Features
Features of the break module include the following:
•
Accessible i/o registers during the break interrupt
•
CPU-generated break interrupts
•
Software-generated break interrupts
•
COP disabling during break interrupts
17.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
•
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 17-1 shows the structure of the break module.
Technical Data
246
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Break Module (BREAK)
Freescale Semiconductor
Break Module (BREAK)
Functional Description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
BKPT
(TO SIM)
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 17-1. Break Module Block Diagram
Addr.
$FE00
Register Name
Break Status Register Read:
(BSR)
Write:
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Reset:
$FE03
$FE0C
$FE0D
Break Flag Control Read:
Register
Write:
(BFCR)
Reset:
Break Address High Read:
Register
Write:
(BRKH)
Reset:
Break Address low Read:
Register
Write:
(BRKL)
Reset:
$FE0E Break Status and Control Read:
Register
Write:
(BRKSCR)
Reset:
Note: Writing a logic 0 clears
SBSW.
1
SBSW
See note
Bit 0
R
0
BCFE
R
R
R
R
R
R
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 17-2. Break I/O Register Summary
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Break Module (BREAK)
Technical Data
247
Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
17.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
17.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
17.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VREG + VHI is present
on the RST pin.
17.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
17.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see 8.7 Low-Power Modes). Clear the SBSW bit by writing logic
0 to it.
Technical Data
248
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Break Module (BREAK)
Freescale Semiconductor
Break Module (BREAK)
Break Module Registers
17.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register. See 8.8 SIM Registers.
17.6 Break Module Registers
These registers control and monitor operation of the break module:
•
Break status and control register (BRKSCR)
•
Break address register high (BRKH)
•
Break address register low (BRKL)
•
Break status register (BSR)
•
Break flag control register (BFCR)
17.6.1 Break Status and Control Register
The break status and control register contains break module enable and
status bits.
Address:
$FE0E
Bit 7
6
BRKE
BRKA
0
0
Read:
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 17-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Break Module (BREAK)
Technical Data
249
Break Module (BREAK)
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
17.6.2 Break Address Registers
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Address:
$FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 17-4. Break Address Register High (BRKH)
Address:
$FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 17-5. Break Address Register Low (BRKL)
17.6.3 Break Status Register
The break status register (BSR) contains a flag to indicate that a break
caused an exit from stop or wait mode. This status bit is useful in
applications requiring a return to wait or stop mode after exiting from a
break interrupt.
Technical Data
250
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Break Module (BREAK)
Freescale Semiconductor
Break Module (BREAK)
Break Module Registers
Address:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
1
Bit 0
SBSW
Write:
Note(1)
Reset:
0
R
= Reserved
R
1. Writing a logic zero clears SBSW.
Figure 17-6. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This read/write bit is set when a break interrupt causes an exit from
wait or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode
; was exited by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Break Module (BREAK)
Technical Data
251
Break Module (BREAK)
17.6.4 Break Flag Control Register (BFCR)
The break control register contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
Write:
Reset:
0
R
= Reserved
Figure 17-7. Break Flag Control Register High (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Technical Data
252
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Break Module (BREAK)
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 18. Electrical Specifications
18.1 Contents
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254
18.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 256
18.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
18.8
Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
18.9
USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 258
18.10 USB Low-Speed Source Electrical Characteristics . . . . . . . . 259
18.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.12 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 260
18.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
18.2 Introduction
This section contains electrical and timing specifications.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Electrical Specifications
Technical Data
253
Electrical Specifications
18.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 18.6 DC Electrical Characteristics for guaranteed
operating conditions.
Characteristic(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +6.0
V
Input voltage
PTE4/D–, PTE3/D+
RST, IRQ
Others
VIN
VSS – 1.0 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VREG + 0.3
V
VDD +VHI
VSS –0.3 to +11
V
I
± 25
mA
TSTG
–55 to +150
°C
Maximum current of PTD0/1
(20-pin package)
IOL
–25 to +50
mA
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
Mode entry voltage, IRQ pin
Maximum current per pin
excluding VDD and VSS
Storage temperature
NOTES:
1. Voltages referenced to VSS
NOTE:
Technical Data
254
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VREG. Reliability of operation is enhanced
if unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VREG).
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Electrical Specifications
Freescale Semiconductor
Electrical Specifications
Functional Operating Range
18.4 Functional Operating Range
Characteristic
Operating temperature range
Operating voltage range
Symbol
Value
Unit
TA
0 to 70
°C
VDD
4.0 to 5.5
V
18.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal Resistance
QFP (44 pins)
SOIC (28 pins)
SOIC (20 pins)
PDIP (20 pins)
θJA
I/O pin power dissipation
PI/O
User determined
W
Power dissipation(1)
PD
PD = (IDD × VDD) + PI/O =
K/(TJ + 273 °C)
W
Constant(2)
K
Average junction temperature
Maximum junction temperature
95
70
70
70
°C/W
PD x (TA + 273 °C)
+ PD2 × θJA
W/°C
TJ
TA + (PD × θJA)
°C
TJM
100
°C
NOTES:
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and
measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Electrical Specifications
Technical Data
255
Electrical Specifications
18.6 DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Regulator output voltage
VREG
3.0
3.3
3.6
V
Output high voltage (ILoad = –2.0 mA)
PTA0–PTA7, PTB0–PTB7, PTC0–PTC7,
PTE0–PTE2
VOH
VREG –0.8
—
—
V
Output low voltage
(ILoad = 1.6 mA) All I/O pins
(ILoad = 25 mA) PTD0–PTD1 in ILDD mode
(ILoad = 10 mA) PTE3–PTE4 with USB disabled
VOL
—
—
—
—
—
—
0.4
0.5
0.4
Input high voltage
All ports, OSC1
IRQ, RST
VIH
0.7 × VREG
0.7 × VDD
—
—
VREG
VDD
V
Input low voltage
All ports, OSC1
IRQ, RST
VIL
VSS
VSS
—
—
0.3 × VREG
0.3 × VDD
V
Output low current (VOL = 2.0 V)
PTD2–PTD5 in LDD mode
IOL
10
13
20
mA
—
—
—
—
5.0
4.5
3.0
2.5
7.5
6.5
5.0
4.0
mA
mA
mA
mA
—
300
350
µA
V
VDD supply current, VDD = 5.25V, fOP = 3MHz
Run, with low speed USB(3)
Run, with USB suspended(3)
Wait, with low speed USB(4)
Wait, with USB suspended(4)
Stop(5)
0 °C to 70°C
IDD
I/O ports Hi-Z leakage current
IIL
—
—
± 10
µA
Input current
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
POR re-arm voltage(6)
VPOR
0
—
100
mV
POR rise-time ramp rate(7)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VDD+VHI
1.4 × VDD
—
2 × VDD
V
25
4
1.2
40
5
1.5
55
6
2
2.8
3.3
3.8
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4 (with USB module disabled)
D– (with USB module enabled)
RPU
LVI reset
VLVR
Technical Data
256
kΩ
V
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Electrical Specifications
Freescale Semiconductor
Electrical Specifications
Control Timing
NOTES:
1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. CL = 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait IDD
5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ ± 5% between VREG
and D– and 15 kΩ ± 5% termination resistors on D+ and D– pins; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VREG is reached.
18.7 Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency(2)
fOP
—
3
MHz
RST input pulse width low(3)
tIRL
125
—
ns
NOTES:
1. VDD = 4.0 to 5.5 Vdc; VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
18.8 Oscillator Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Crystal frequency(1)
fXCLK
1
—
6
MHz
External clock
Reference frequency(1), (2)
fXCLK
dc
—
6
MHz
Crystal load capacitance(3)
CL
—
—
—
Crystal fixed capacitance(3)
C1
—
2 × CL
—
Crystal tuning capacitance(3)
C2
—
2 × CL
—
Feedback bias resistor
RB
—
10 MΩ
—
Series resistor(3), (4)
RS
—
—
—
NOTES:
1. The USB module is designed to function at fXCLK = 6 MHz.
2. No more than 10% duty cycle deviation from 50%.
3. Consult crystal vendor data sheet.
4. Not required for high-frequency crystals.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Electrical Specifications
Technical Data
257
Electrical Specifications
18.9 USB DC Electrical Characteristics
Characteristic(1)
Symbol
Conditions
Min
Hi-Z state data line leakage
ILO
0 V<VIN<3.3
V
–10
Voltage input high (driven)
VIH
2.0
Voltage input high (floating)
VIHZ
2.7
Voltage input low
VIL
Differential input sensitivity
VDI
|(D+) – (D–)|
0.2
Differential common mode range
VCM
Includes VDI
Range
0.8
Static output low
VOL
RL of 1.425 K
to 3.6 V
Static output high
VOH
RL of 14.25 K
to GND
Output signal crossover voltage
VCRS
Regulator bypass capacitor
CREGBYPASS
Regulator bulk capacitor
CREGBULK
Typ
+10
µA
3.6
V
0.8
V
V
—
0.1
4.7
Unit
V
2.8
1.3
Max
2.5
V
0.3
V
3.6
V
2.0
V
µF
µF
NOTES:
1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
Technical Data
258
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Electrical Specifications
Freescale Semiconductor
Electrical Specifications
USB Low-Speed Source Electrical Characteristics
18.10 USB Low-Speed Source Electrical Characteristics
Characteristic(1)
Symbol
Conditions
Min
Typ
Max
Unit
Internal operating frequency
fOP
—
—
3
—
MHz
Transition time(2)
Rise time
tR
CL = 200 pF
75
—
300
ns
CL = 600pF
Fall time
tF
CL = 200 pF
75
—
300
CL = 600pF
tRFM
tR/tF
80
—
120
%
tDRATE
1.5 Mbs ± 1.5%
1.4775
676.8
1.500
666.0
1.5225
656.8
Mbs
ns
Source differential driver jitter
To next transition
For paired transitions
tDDJ1
tDDJ2
CL = 600 pF
Measured at
crossover point
–25
–10
—
—
25
10
ns
Receiver data jitter tolerance
To next transition
For paired transitions
tDJR1
tDJR2
CL = 600 pF
Measured at
crossover point
–75
–45
—
—
75
45
ns
Source SEO interval of EOP
tLEOPT
Measured at
crossover point
1.25
—
1.50
µs
Rise/Fall time matching
Low speed data rate
Source jitter for differential transition
to SE0 transition(3)
Receiver SEO interval of EOP
Must reject as EOP
Must accept
Width of SEO interval during
differential transition
Measured at
crossover point
tLEOPR1
tLEOPR2
tLST
Measured at
crossover point
Measured at
crossover point
667
ns
210
670
—
—
—
—
ns
—
—
210
ns
NOTES:
1. All voltages are measured from local ground, unless otherwise specified. All timings use a capacitive load of 50 pF, unless
otherwise specified. Low-speed timings have a 1.5kΩ pullup to 2.8 V on the D– data line.
2. Transition times are measured from 10% to 90% of the data signal. The rising and falling edges should be smoothly transitioning (monotonic). Capacitive loading includes 50 pF of tester capacitance.
3. The two transitions are a (nominal) bit time apart.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Electrical Specifications
Technical Data
259
Electrical Specifications
18.11 USB Signaling Levels
Signaling Levels
Bus State
Transmit
Receive
Differential 1
D+ > VOH (min) and D– < VOL (max)
(D+) – (D–) > 200 mV
Differential 0
D– > VOH (min) and D– < VOL (max)
(D–) – (D+) > 200 mV
Single-ended 0 (SE0)
D+ and D– < VOL (max)
D+ and D– < VIL (max)
Data J state (low speed)
Differential 0
Differential 0
Data K state (low speed)
Differential 1
Differential 1
Idle state (low speed)
NA
D– > VIHZ (min) and D+ < VIL (max)
Resume state
Differential 1
Differential 1
Start of packet (SOP)
Data lines switch from Idle to K State
End of packet (EOP)
SE0 for approximately 2 bit times(1)
followed by a J state for 1 bit time
SE0 for ≥ 1 bit time(2) followed by a
J state for 1 bit time
Reset
NA
D+ and D– < VIL (max) for ≥ 8µs
NOTES:
1. The width of EOP is defined in bit times relative to the speed of transmission.
2. The width of EOP is defined in bit times relative to the device type receiving the EOP. The bit time is approximate.
18.12 TImer Interface Module Characteristics
Characteristic
Input capture pulse width
Input clock pulse width
Technical Data
260
Symbol
Min
Max
tTIH, tTIL
1/fOP
—
tTCH, tTCL
(1/fOP) + 5ns
—
Unit
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Electrical Specifications
Freescale Semiconductor
Electrical Specifications
Memory Characteristics
18.13 Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
Max
Unit
VRDR
1.3
—
V
FLASH block size
—
512
Bytes
FLASH programming size
—
64
Bytes
FLASH read bus clock frequency
fRead(1)
32 k
8.4 M
Hz
FLASH block erase time
tErase(2)
2
—
ms
FLASH mass erase time
tMErase(3)
2
—
ms
FLASH PGM/ERASE to HVEN set up time
tnvs
5
—
µs
FLASH high-voltage hold time
tnvh
5
—
µs
FLASH high-voltage hold time (mass erase)
tnvhl
100
—
µs
FLASH program hold time
tpgs
10
—
µs
FLASH program time
tPROG
20
—
µs
FLASH return to read time
trcv(4)
1
—
µs
FLASH cumulative program hv period
tHV(5)
—
25
ms
FLASH row erase endurance(6)
—
10k
—
Cycles
FLASH row program endurance(7)
—
10k
—
Cycles
FLASH data retention time(8)
—
10
—
Years
NOTES:
1. fREAD is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduced the endurance of the flash memory
3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduced the endurance of the flash memory
4. trcv is defined as the time it need before start the read of the flash after turn off the HVEN bit
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Electrical Specifications
Technical Data
261
Electrical Specifications
Technical Data
262
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Electrical Specifications
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 19. Mechanical Specifications
19.1 Contents
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
19.3
44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 264
19.4
28-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 265
19.5
20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . 265
19.6
20-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 266
19.2 Introduction
This section gives the dimensions for:
•
44-pin plastic quad flat pack (case 824A)
•
28-pin small outline integrated circuit package (case 751F)
•
20-pin plastic dual in-line package (case 738)
•
20-pin small outline integrated circuit package (case 751D)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Mechanical Specifications
Technical Data
263
Mechanical Specifications
19.3 44-Pin Plastic Quad Flat Pack (QFP)
B
L
B
33
23
22
S
D
S
V
F
BASE METAL
0.20 (0.008)
DETAIL A
DETAIL A
M
C A–B
S
S
H A–B
0.20 (0.008)
B
L
–B–
M
–A–
D
–A–, –B–, –D–
0.05 (0.002) A–B
34
J
N
D
44
0.20 (0.008)
12
1
11
M
C A–B
S
D
S
SECTION B–B
VIEW ROTATED 90°
–D–
A
0.20 (0.008)
M
H A–B
S
D
S
S
D
S
0.05 (0.002) A–B
S
0.20 (0.008)
M
C A–B
M
DETAIL C
C E
–H–
–C–
DATUM
PLANE
0.10 (0.004)
H
SEATING
PLANE
G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
M
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
M
T
DATUM
PLANE
–H–
R
K
W
Q
X
DETAIL C
MILLIMETERS
MIN
MAX
9.90
10.10
9.90
10.10
2.10
2.45
0.30
0.45
2.00
2.10
0.30
0.40
0.80 BSC
—
0.25
0.13
0.23
0.65
0.95
8.00 REF
5°
10°
0.13
0.17
0°
7°
0.13
0.30
12.95
13.45
0.13
—
0°
—
12.95
13.45
0.40
—
1.6 REF
INCHES
MIN
MAX
0.390
0.398
0.390
0.398
0.083
0.096
0.012
0.018
0.079
0.083
0.012
0.016
0.031 BSC
—
0.010
0.005
0.009
0.026
0.037
0.315 REF
5°
10°
0.005
0.007
0°
7°
0.005
0.012
0.510
0.530
0.005
—
0°
—
0.510
0.530
0.016
—
0.063 REF
Figure 19-1. 44-Pin QFP (Case 824A)
Technical Data
264
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Mechanical Specifications
Freescale Semiconductor
Mechanical Specifications
28-Pin Small Outline Integrated Circuit (SOIC)
19.4 28-Pin Small Outline Integrated Circuit (SOIC)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
-A15
28
14X
-B1
P
0.010 (0.25)
M
B
M
14
28X
D
0.010 (0.25)
M
T A
S
B
M
S
R
DIM
A
B
C
D
F
G
J
K
M
P
R
X 45
C
26X
-T-
G
SEATING
PLANE
K
F
J
MILLIMETERS
MIN
MAX
17.80
18.05
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0°
8°
10.01
10.55
0.25
0.75
INCHES
MIN
MAX
0.701
0.711
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0°
8°
0.395
0.415
0.010
0.029
Figure 19-2. 28-Pin SOIC (Case 751F)
19.5 20-Pin Dual In-Line Package (PDIP)
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
Figure 19-3. 20-Pin PDIP (Case 738)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Mechanical Specifications
Technical Data
265
Mechanical Specifications
19.6 20-Pin Small Outline Integrated Circuit (SOIC)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
20
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
K
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
Figure 19-4. 20-Pin SOIC (Case 751D)
Technical Data
266
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Mechanical Specifications
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 20. Ordering Information
20.1 Contents
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
20.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
20.2 Introduction
This section contains ordering numbers for the MC68HC908JB8.
20.3 MC Order Numbers
Table 20-1. MC Order Numbers
Package
Operating
Temperature Range
MC68HC908JB8JP
20-pin PDIP
0 to +70 °C
MC68HC908JB8JDW
20-pin SOIC
0 to +70 °C
MC68HC908JB8ADW
28-pin SOIC
0 to +70 °C
MC68HC908JB8FB
44-pin QFP
0 to +70 °C
MC68HC908JB8JPE
20-pin PDIP
0 to +70 °C
MC908JB8JDWE
20-pin SOIC
0 to +70 °C
MC908JB8ADWE
28-pin SOIC
0 to +70 °C
MC908JB8FBE
44-pin QFP
0 to +70 °C
MC Order Number
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Ordering Information
Compliance
—
Pb-Free and RoHS
compliant.
Technical Data
267
Ordering Information
Technical Data
268
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Ordering Information
Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Appendix A. MC68HC08JB8
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
A.3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
A.4
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
A.5
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
A.6
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
A.7.1
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .274
A.7.2
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
A.8
MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 275
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
MC68HC08JB8
Technical Data
269
MC68HC08JB8
A.2 Introduction
This section introduces the MC68HC08JB8, the ROM part equivalent to
the MC68HC908JB8. The entire data book apply to this ROM device,
with exceptions outlined in this appendix.
Table A-1. Summary of MC68HC08JB8 and MC68HC908JB8 Differences
MC68HC08JB8
MC68HC908JB8
Memory ($DC00–$FBFF)
8,192 bytes ROM
8,192 bytes FLASH
User vectors ($FFF0–$FFFF)
16 bytes ROM
16 bytes FLASH
Registers at $FE08 and $FF09
Not used;
locations are reserved.
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Monitor ROM
($FC00–$FDFF and $FE10–$FFDF)
$FC00–$FDFF: Not used.
$FE10–$FFDF: Used for
testing purposes only.
Used for testing and FLASH
programming/erasing.
A.3 MCU Block Diagram
Figure A-1 shows the block diagram of the MC68HC08JB8.
A.4 Memory Map
The MC68HC08JB8 has 8,192 bytes of user ROM from $DC00 to
$FBFF, and 16 bytes of user ROM vectors from $FFF0 to $FFFF. On the
MC68HC908JB8, these memory locations are FLASH memory.
Figure A-2 shows the memory map of the MC68HC08JB8.
Technical Data
270
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
MC68HC08JB8
Freescale Semiconductor
PTA
PTB
PTC
PTC7–PTC0 (3)
PTD
PTD7–PTD6 (4)
PTD5–PTD2 (4) (5)
DDRA
DDRB
PTB7–PTB0 (3)
DDRC
CPU
REGISTERS
PTA7/KBA7 (3)
:
PTA0/KBA0 (3)
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
CONTROL AND STATUS REGISTERS — 64 BYTES
TIMER INTERFACE
MODULE
USER ROM — 8,192 BYTES
USER RAM — 256 BYTES
BREAK
MODULE
MONITOR ROM — 464 BYTES
LOW VOLTAGE INHIBIT
MODULE
OSC1
OSC2
DDRD
USER ROM VECTORS — 16 BYTES
PTD1–PTD0 (4) (6)
POWER-ON RESET
MODULE
OSCILLATOR
PTE4/D– (3) (4) (5)
(1), (3) IRQ
SYSTEM INTEGRATION
MODULE
PTE3/D+
COMPUTER OPERATING PROPERLY
MODULE
IRQ
MODULE
USB
MODULE
VDD
USB ENDPOINT 0, 1, 2
POWER
PTE
RST
DDRE
(1), (2)
LS USB
TRANSCEIVER
MC68HC08JB8
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
INTERNAL BUS
M68HC08 CPU
(3) (4) (5)
PTE2/TCH1 (3)
PTE1/TCH0 (3)
PTE0/TCLK (3)
VSS
VREG
(3.3 V)
INTERNAL VOLTAGE REGULATOR
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pull-up device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
Figure A-1. MC68HC08JB8 Block Diagram
MC68HC08JB8
271
Technical Data
Shaded blocks indicate differences to MC68HC908JB8
MC68HC08JB8
$0000
↓
$003F
I/O Registers
64 Bytes
$0040
↓
$013F
RAM
256 Bytes
$0140
↓
$DBFF
Unimplemented
56,000 Bytes
$DC00
↓
$FBFF
ROM
8,192 Bytes
$FC00
↓
$FDFF
Unimplemented
512 Bytes
$FE00
Break Status Register (BSR)
$FE01
Reset Status Register (RSR)
$FE02
Reserved
$FE03
Break Flag Control Register (BFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Reserved
$FE06
Reserved
$FE07
Reserved
$FE08
Reserved
$FE09
Reserved
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address High Register (BRKH)
$FE0D
Break Address Low Register (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
Reserved
$FE10
↓
$FFDF
Monitor ROM
464 Bytes
$FFE0
↓
$FFEF
Reserved
16 Bytes
$FFF0
↓
$FFFF
ROM Vectors
16 Bytes
Figure A-2. MC68HC08JB8 Memory Map
Technical Data
272
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
MC68HC08JB8
Freescale Semiconductor
MC68HC08JB8
A.5 Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08JB8.
On the MC68HC908JB8, these two locations are the FLASH control
register and the FLASH block protect register respectively.
A.6 Monitor ROM
The monitor program (monitor ROM: $FE10–$FFDF) on the
MC68HC08JB8 is for device testing only. $FC00–$FDFF are unused.
A.7 Electrical Specifications
Electrical specifications for the MC68HC908JB8 apply to the
MC68HC08JB8, except for the parameters indicated below.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
MC68HC08JB8
Technical Data
273
MC68HC08JB8
A.7.1 DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Regulator output voltage
VREG
3.0
3.3
3.6
V
Output high voltage (ILoad = –2.0 mA)
PTA0–PTA7, PTB0–PTB7, PTC0–PTC7,
PTE0–PTE2
VOH
VREG –0.8
—
—
V
Output low voltage
(ILoad = 1.6 mA) All I/O pins
(ILoad = 25 mA) PTD0–PTD1 in ILDD mode
(ILoad = 10 mA) PTE3–PTE4 with USB disabled
VOL
—
—
—
—
—
—
0.4
0.5
0.4
Input high voltage
All ports, OSC1
IRQ, RST
VIH
0.7 × VREG
0.7 × VDD
—
—
VREG
VDD
V
Input low voltage
All ports, OSC1
IRQ, RST
VIL
VSS
VSS
—
—
0.3 × VREG
0.3 × VDD
V
Output low current (VOL = 2.0 V)
PTD2–PTD5 in LDD mode
IOL
17
22
27
mA
—
—
—
—
5.0
4.5
3.0
2.5
7.5
6.5
5.0
4.0
mA
mA
mA
mA
—
30
100
µA
V
VDD supply current, VDD = 5.25V, fOP = 3MHz
Run, with low speed USB(3)
Run, with USB suspended(3)
Wait, with low speed USB(4)
Wait, with USB suspended(4)
Stop(5)
0 °C to 70°C
IDD
I/O ports Hi-Z leakage current
IIL
—
—
± 10
µA
Input current
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
POR re-arm voltage(6)
VPOR
0
—
100
mV
POR rise-time ramp rate(7)
RPOR
0.035
—
—
V/ms
Monitor mode entry voltage
VDD+VHI
1.4 × VDD
2 × VDD
V
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4 (with USB module disabled)
D– (with USB module enabled)
RPU
LVI reset
VLVR
Technical Data
274
25
4
1.2
40
5
1.5
55
6
2.0
2.4
2.7
3.0
kΩ
V
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
MC68HC08JB8
Freescale Semiconductor
MC68HC08JB8
NOTES:
1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. CL = 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait IDD
5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ ± 5% between VREG
and D– pins and 15 kΩ ± 5% termination resistor on D+ pin; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VREG is reached.
A.7.2 Memory Characteristics
Characteristic
Symbol
Min
Max
Unit
VRDR
1.3
—
V
RAM data retention voltage
Notes:
Since MC68HC08JB8 is a ROM device, FLASH memory electrical characteristics do not apply.
A.8 MC68HC08JB8 Order Numbers
These part numbers are generic numbers only. To place an order, ROM
code must be submitted to the ROM Processing Center (RPC).
Table A-2. MC68HC08JB8 Order Numbers
Package
Operating
Temperature Range
MC68HC08JB8JP
20-pin PDIP
0 to +70 °C
MC68HC08JB8JDW
20-pin SOIC
0 to +70 °C
MC68HC08JB8ADW
28-pin SOIC
0 to +70 °C
MC68HC08JB8FB
44-pin QFP
0 to +70 °C
MC Order Number
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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MC68HC08JB8
Technical Data
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MC68HC08JB8
Technical Data
276
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Freescale Semiconductor
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Appendix B. MC68HC08JT8
B.1 Contents
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
B.3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
B.4
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
B.5
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
B.6
Reserved Register Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
B.7
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
B.8
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.9
Universal Serial Bus Module. . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.10 Low-Voltage Inhibit Module . . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 282
B.11.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .283
B.11.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .283
B.11.4 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
B.11.5 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
B.12 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . 284
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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MC68HC08JT8
Technical Data
277
MC68HC08JT8
B.2 Introduction
This section introduces the MC68HC08JT8, a low-voltage ROM part
version to the MC68HC908JB8. The entire data book apply to this ROM
device, with exceptions outlined in this appendix.
Table B-1. Summary of MC68HC08JT8 and MC68HC908JB8 Differences
MC68HC08JT8
MC68HC908JB8
Memory ($DC00–$FBFF)
8,192 bytes ROM
8,192 bytes FLASH
User vectors ($FFF0–$FFFF)
16 bytes ROM
16 bytes FLASH
Registers at $FE08 and $FF09
Not used;
locations are reserved
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Bit 4 at CONFIG ($001F)
Not used;
bit is reserved.
LVID: low-voltage inhibit
disable bit
Monitor ROM
($FC00–$FDFF and $FE10–$FFDF)
$FC00–$FDFF: Not used.
$FE10–$FFDF: Used for
testing purposes only.
Used for testing and FLASH
programming/erasing.
Low voltage inhibit module
Not available (disabled)
Available
Universal Serial Bus (USB) module
Not available. User should set
the SUSPND bit to logic 1 to
reduce power consumption.
Available
On-chip 3.3V regulator
Not available (disabled)
Available
Operating voltage
2.0 to 3.6V
4.0 to 5.5V
Operating frequency
fOPMAX = 2.5MHz at 2V
fOPMAX = 3MHz at 3V
3MHz
B.3 MCU Block Diagram
Figure B-1 shows the block diagram of the MC68HC08JT8.
B.4 Memory Map
The MC68HC08JT8 has 8,192 bytes of user ROM from $DC00 to
$FBFF, and 16 bytes of user ROM vectors from $FFF0 to $FFFF. On the
MC68HC908JB8, these memory locations are FLASH memory.
Figure B-2 shows the memory map of the MC68HC08JT8.
Technical Data
278
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MC68HC08JT8
Freescale Semiconductor
PTA
PTB
PTC
PTC7–PTC0 (3)
PTD
PTD7–PTD6 (4)
PTD5–PTD2 (4) (5)
DDRA
DDRB
PTB7–PTB0 (3)
DDRC
CPU
REGISTERS
PTA7/KBA7 (3)
:
PTA0/KBA0 (3)
ARITHMETIC/LOGIC
UNIT (ALU)
KEYBOARD INTERRUPT
MODULE
CONTROL AND STATUS REGISTERS — 64 BYTES
TIMER INTERFACE
MODULE
USER ROM — 8,192 BYTES
USER RAM — 256 BYTES
BREAK
MODULE
MONITOR ROM — 464 BYTES
DISABLED
LOW VOLTAGE INHIBIT
MODULE
OSC1
OSC2
DDRD
USER ROM VECTORS — 16 BYTES
PTD1–PTD0 (4) (6)
POWER-ON RESET
MODULE
OSCILLATOR
PTE4 (3) (4) (5)
(1), (3) IRQ
SYSTEM INTEGRATION
MODULE
PTE3
COMPUTER OPERATING PROPERLY
MODULE
IRQ
MODULE
NOT AVAILABLE
USB
MODULE
VDD
USB ENDPOINT 0, 1, 2
POWER
PTE
RST
DDRE
(1), (2)
LS USB
TRANSCEIVER
MC68HC08JT8
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
INTERNAL BUS
M68HC08 CPU
(3) (4) (5)
PTE2/TCH1 (3)
PTE1/TCH0 (3)
PTE0/TCLK (3)
VSS
DISABLED
VREG
(3.3 V)
INTERNAL VOLTAGE REGULATOR
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pull-up device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
Figure B-1. MC68HC08JT8 Block Diagram
MC68HC08JT8
279
Technical Data
Shaded blocks indicate differences to MC68HC908JB8
MC68HC08JT8
$0000
↓
$003F
I/O Registers
64 Bytes
$0040
↓
$013F
RAM
256 Bytes
$0140
↓
$DBFF
Unimplemented
56,000 Bytes
$DC00
↓
$FBFF
ROM
8,192 Bytes
$FC00
↓
$FDFF
Unimplemented
512 Bytes
$FE00
Break Status Register (BSR)
$FE01
Reset Status Register (RSR)
$FE02
Reserved
$FE03
Break Flag Control Register (BFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Reserved
$FE06
Reserved
$FE07
Reserved
$FE08
Reserved
$FE09
Reserved
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address High Register (BRKH)
$FE0D
Break Address Low Register (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
Reserved
$FE10
↓
$FFDF
Monitor ROM
464 Bytes
$FFE0
↓
$FFEF
Reserved
16 Bytes
$FFF0
↓
$FFFF
ROM Vectors
16 Bytes
Figure B-2. MC68HC08JT8 Memory Map
Technical Data
280
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
MC68HC08JT8
Freescale Semiconductor
MC68HC08JT8
B.5 Power Supply Pins
The MC68HC08JT8 is design for low voltage operation. Connect VDD
and VREG for normal operation.
The VREG voltage regulator is disabled on the MC68HC08JT8.
MCU
VDD
VREG
VSS
CBYPASS 0.1 µF
+
CBULK 10 µF
VDD
NOTE: Values shown are typical values.
Figure B-3. Power Supply Bypassing
B.6 Reserved Register Bit
Bit 4 of the configuration register ($001F) is a reserved bit on the
MC68HC08JT8. The bit will always read as zero.
On the MC68HC908JB8, bit 4 of the configuration register is the lowvoltage inhibit disable bit, LVID.
B.7 Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08JT8.
On the MC68HC908JB8, these two locations are the FLASH control
register and the FLASH block protect register respectively.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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MC68HC08JT8
Technical Data
281
MC68HC08JT8
B.8 Monitor ROM
The monitor program (monitor ROM: $FE10–$FFDF) on the
MC68HC08JT8 is for device testing only. $FC00–$FDFF are unused.
B.9 Universal Serial Bus Module
The USB module is designed for operation with VDD = 4V to 5.5V,
therefore, it should not be used on the MC68HC08JT8 device. To further
reduce current consumption in stop mode, set the SUSPND bit in the
USB interrupt register 0 (UIR0) to logic 1. Other USB registers should be
left in their default state.
B.10 Low-Voltage Inhibit Module
The LVI module is disabled on the MC68HC08JT8.
B.11 Electrical Specifications
Electrical specifications for the MC68HC908JB8 apply to the
MC68HC08JT8, except for the parameters indicated below.
B.11.1 Absolute Maximum Ratings
Characteristic(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.9
V
Input voltage
VIN
VSS – 0.3 to VDD + 0.3
V
I
± 25
mA
TSTG
–55 to +150
°C
Maximum current of PTD0/1
(20-pin package)
IOL
–15 to +30
mA
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
Maximum current per pin
excluding VDD and VSS
Storage temperature
NOTES:
1. Voltages referenced to VSS.
Technical Data
282
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MC68HC08JT8
Freescale Semiconductor
MC68HC08JT8
B.11.2 Functional Operating Range
Characteristic
Symbol
Value
Unit
TA
0 to 70
°C
VDD
2.0 to 3.6
V
Operating temperature range
Operating voltage range
B.11.3 DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILoad = –1.6 mA)
PTA0–PTA7, PTB0–PTB7, PTC0–PTC7,
PTE0–PTE2
VOH
VDD –0.4
—
—
V
Output low voltage
(ILoad = 1.6 mA) All I/O pins
(ILoad = 15 mA) PTD0–PTD1 in ILDD mode
(ILoad = 5 mA) PTE3–PTE4
VOL
—
—
—
—
—
—
0.4
0.5
0.4
Input high voltage
All ports, OSC1, IRQ, RST
VIH
0.7 × VDD
—
VDD
V
Input low voltage
All ports, OSC1, IRQ, RST
VIL
VSS
—
0.3 × VDD
V
Output low current (VOL = 2.0 V)(3)
PTD2–PTD5 in LDD mode (VDD = 2V)
PTD2–PTD5 in LDD mode (VDD = 3V)
IOL
—
—
6
16
—
—
mA
—
—
3.5
2.5
6.5
4.5
mA
mA
—
20
30
µA
V
VDD supply current, VDD = 3V, fOP = 3MHz
Run(4)
Wait(5)
Stop(6)
0 °C to 70°C
IDD
I/O ports Hi-Z leakage current
IIL
—
—
± 10
µA
Input current
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
POR re-arm voltage(7)
VPOR
0
—
100
mV
POR rise-time ramp rate
RPOR
0.02
—
—
V/ms
VDD+VHI
1.4 × VDD
2 × VDD
V
RPU
25
4
55
6
kΩ
kΩ
Monitor mode entry voltage
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
MC68HC08JT8
40
5
Technical Data
283
MC68HC08JT8
NOTES:
1. VDD = 2.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at 3V, 25 °C only.
3. In LDD mode, the specified IOL is achieved when the external pullup voltage is equal to or higher than the voltage:
VOL + voltage dropped across LED.
4. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
5. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
6. Stop IDD measured with OSC1 grounded; no port pins sourcing current.
7. Maximum is highest voltage that POR is guaranteed.
B.11.4 Control Timing
Characteristic
Symbol
Min
Max
Unit
fOP
—
—
2.5
3.0
MHz
MHz
Symbol
Min
Max
Unit
VRDR
1.3
—
V
Internal operating frequency
VDD = 2.0V
VDD = 3.0V
B.11.5 Memory Characteristics
Characteristic
RAM data retention voltage
NOTES: Since MC68HC08JT8 is a ROM device, FLASH memory electrical characteristics do not apply.
B.12 MC68HC08JT8 Order Numbers
These part numbers are generic numbers only. To place an order, ROM
code must be submitted to the ROM Processing Center (RPC).
Table B-2. MC68HC08JT8 Order Numbers
Package
Operating
Temperature Range
MC68HC08JT8ADW
28-pin SOIC
0 to +70 °C
MC68HC08JT8FB
44-pin QFP
0 to +70 °C
MC68HC08JT8FBE
44-pin QFP
0 to +70 °C
MC Order Number
Technical Data
284
Compliance
—
Pb-Free and RoHS
compliant.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
MC68HC08JT8
Freescale Semiconductor
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MC68HC908JB8/D
Rev. 2.3, 9/2005
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