MCP3002
2.7V Dual Channel 10-Bit A/D Converter
with SPI™ Serial Interface
Features
•
•
•
•
•
•
•
•
10-bit resolution
±1 LSB max DNL
±1 LSB max INL
Analog inputs programmable as single-ended or
pseudo-differential pairs
On-chip sample and hold
SPI™ serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
200 ksps max sampling rate at VDD = 5V
75 ksps max sampling rate at VDD = 2.7V
Low power CMOS technology:
- 5 nA typical standby current, 2 µA max
- 550 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP, PDIP, SOIC and TSSOP packages
Applications
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
Description
The Microchip Technology Inc. MCP3002 is a successive approximation 10-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The
MCP3002 is programmable to provide a single pseudodifferential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity
(INL) are both specified at ±1 LSB. Communication
with the device is done using a simple serial interface
compatible with the SPI protocol. The device is capable
of conversion rates of up to 200 ksps at 5V and 75 ksps
at 2.7V. The MCP3002 device operates over a broad
voltage range (2.7V - 5.5V). Low current design permits
operation with a typical standby current of 5 nA and a
typical active current of 375 µA. The MCP3002 is
offered in 8-pin MSOP, PDIP, TSSOP and 150 mil
SOIC packages.
© 2007 Microchip Technology Inc.
MSOP, PDIP, SOIC, TSSOP
CS/SHDN
1
CH0
2
CH1
3
VSS
4
MCP3002
•
•
•
•
Package Types
8
VDD/VREF
7
CLK
6
DOUT
5
DIN
Functional Block Diagram
VDD
CH0
CH1
Input
Channel
Mux
VSS
DAC
Comparator
10-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN
DIN
CLK
Shift
Register
DOUT
DS21294C-page 1
MCP3002
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
PIN FUNCTION TABLE
Name
VDD/VREF
VDD.........................................................................7.0V
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
ESD protection on all pins (HBM)........................> 4kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Function
+2.7V to 5.5V Power Supply and
Reference Voltage Input
CH0
Channel 0 Analog Input
CH1
Channel 1 Analog Input
CLK
Serial Clock
DIN
Serial Data In
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 16*fSAMPLE unless otherwise noted.
Typical values apply for VDD = 5V, TAMB = 25°C unless otherwise noted.
PARAMETER
SYM
MIN
TYP
MAX
UNITS
tCONV
—
—
10
clock
cycles
CONDITIONS
Conversion Rate:
Conversion Time
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
—
—
Integral Nonlinearity
INL
—
Differential Nonlinearity
DNL
1.5
clock
cycles
200
75
ksps
ksps
VDD = 5V
VDD = 2.7V
±0.5
±1
LSB
—
±0.25
±1
LSB
Offset Error
—
—
±1.5
LSB
Gain Error
—
—
±1
LSB
THD
—
-76
—
dB
VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion
(SINAD)
SINAD
—
61
—
dB
VIN = 0.1V to 4.9V@1 kHz
Spurious Free Dynamic Range
SFDR
—
78
—
dB
VIN = 0.1V to 4.9V@1 kHz
VSS
—
VDD
V
DC Accuracy:
Resolution
10
bits
No missing codes over
temperature
Dynamic Performance:
Total Harmonic Distortion
Analog Inputs:
Input Voltage Range for CH0 or CH1
in Single-Ended Mode
Input Voltage Range for IN+ In
pseudo-differential Mode
IN+
IN-
—
VDD+IN-
Input Voltage Range for IN- In
pseudo-differential Mode
IN-
VSS-100
—
VSS+100
mV
—
0.001
±1
µA
Switch Resistance
RSS
—
1K
—
Ω
See Figure 4-1
Sample Capacitor
CSAMPLE
—
20
—
pF
See Figure 4-1
Leakage Current
Note 1:
2:
This parameter is established by characterization and not 100% tested.
The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK ≥10 kHz for temperatures
at or above 70°C.
DS21294C-page 2
© 2007 Microchip Technology Inc.
MCP3002
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 16*fSAMPLE unless otherwise noted.
Typical values apply for VDD = 5V, TAMB = 25°C unless otherwise noted.
PARAMETER
SYM
MIN
TYP
VIH
0.7 VDD
MAX
UNITS
—
—
V
CONDITIONS
Digital Input/Output:
Data Coding Format
High Level Input Voltage
Straight Binary
Low Level Input Voltage
VIL
—
—
0.3 VDD
V
High Level Output Voltage
VOH
4.1
—
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
—
—
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
µA
VOUT = VSS or VDD
CIN, COUT
—
—
10
pF
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Clock Frequency
fCLK
—
—
—
—
3.2
1.2
MHz
MHz
Clock High Time
tHI
140
—
—
ns
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters:
Clock Low Time
VDD = 5V (Note 2)
VDD = 2.7V (Note 2)
tLO
140
—
—
ns
tSUCS
100
—
—
ns
tSU
—
—
50
ns
Data Input Hold Time
tHD
—
—
50
ns
CLK Fall To Output Data Valid
tDO
—
—
—
—
125
200
ns
ns
VDD = 5V, see Figure 1-2
VDD = 2.7V, see Figure 1-2
CLK Fall To Output Enable
tEN
—
—
125
200
ns
ns
VDD = 5V, see Figure 1-2
VDD = 2.7V, see Figure 1-2
CS Rise To Output Disable
tDIS
—
—
100
ns
See Test Circuits, Figure 1-2
Note 1
CS Disable Time
CS Fall To First Rising CLK Edge
Data Input Setup Time
tCSH
310
—
—
ns
DOUT Rise Time
tR
—
—
100
ns
See Test Circuits, Figure 1-2
Note 1
DOUT Fall Time
tF
—
—
100
ns
See Test Circuits, Figure 1-2
Note 1
Operating Voltage
VDD
2.7
—
5.5
V
Operating Current
IDD
—
—
525
300
650
—
µA
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
—
0.005
2
µA
CS = VDD = 5.0V
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
Power Requirements:
Temperature Ranges:
Thermal Package Resistance:
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
124
—
°C/W
Note 1:
2:
This parameter is established by characterization and not 100% tested.
The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK ≥10 kHz for temperatures
at or above 70°C.
© 2007 Microchip Technology Inc.
DS21294C-page 3
MCP3002
tCSH
CS
tSUCS
tLO
tHI
CLK
tHD
tSU
DIN
MSB IN
tEN
DOUT
NULL BIT
FIGURE 1-1:
tR
tDO
tF
tDIS
LSB
MSB OUT
Serial Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
3 kΩ
Test Point
DOUT
3 kΩ
DOUT
tEN Waveform
30 pF
CL = 30 pF
tDIS Waveform 1
VSS
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
Voltage Waveforms for tEN
CS
tF
tR
tDIS Waveform 2
VDD/2
1
CLK
2
3
4
B9
DOUT
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
CS
CLK
tDO
VIH
DOUT
Waveform 1*
90%
tDIS
DOUT
DOUT
Waveform 2†
10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled
by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
DS21294C-page 4
© 2007 Microchip Technology Inc.
MCP3002
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
0.6
0.6
VDD = 2.7V
0.4
Positive INL
0.2
INL (LSB)
INL (LSB)
0.4
0.0
-0.2
Negative INL
-0.4
Positive INL
0.2
0.0
-0.2
Negative INL
-0.4
-0.6
-0.6
0
25
50
75
0
100 125 150 175 200 225 250
25
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
100
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
1.0
VDD = 5V
0.8
VDD = 2.7V
0.8
fSAMPLE = 200 ksps
0.6
fSAMPLE = 75 ksps
0.6
0.4
INL (LSB)
0.4
0.2
0.0
-0.2
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
128
256
384
512
640
768
896
1024
0
128
256
384
Digital Code
FIGURE 2-2:
FIGURE 2-5:
(VDD = 2.7V).
0.5
0.5
0.4
0.4
0.3
0.3
Positive INL
640
768
896
1024
Integral Nonlinearity (INL) vs. Code
VDD = 2.7V
fSAMPLE = 75 ksps
INL (LSB)
0.2
0.1
0.0
-0.1
-0.2
512
Digital Code
Integral Nonlinearity (INL) vs. Code.
0.2
INL (LSB)
75
Sample Rate (ksps)
1.0
INL (LSB)
50
Negative INL
Positive INL
0.1
0.0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
Negative INL
-0.5
-0.5
-50
-25
0
25
50
75
-50
100
Temperature (°C)
FIGURE 2-3:
Temperature.
Integral
Nonlinearity
© 2007 Microchip Technology Inc.
-25
0
25
50
75
100
Temperature (°C)
(INL)
vs.
FIGURE 2-6: Integral
Nonlinearity
Temperature (VDD = 2.7V).
(INL)
vs.
DS21294C-page 5
MCP3002
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
1.0
0.8
0.8
0.6
0.6
Positive INL
0.4
DNL (LSB)
INL(LSB)
0.4
0.2
0.0
-0.2
-0.4
Negative INL
-0.6
0.0
-0.2
Negative
-0.4
All points taken at fSAMPLE = 200 ksps except
-0.8
Positive DNL
0.2
All points taken at fSAMPLE = 200 ksps except
-0.6
VDD = 2.7V, fSAMPLE = 75 ksps
VDD = 2.7V, fSAMPLE = 75 ksps
-1.0
-0.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
VDD (V)
Integral Nonlinearity (INL) vs. VDD.
0.6
0.6
0.4
0.4
5.5
VDD = 2.7V
0.2
Positive DNL
0.0
-0.2
Negative DNL
-0.4
Positive DNL
0.2
0.0
-0.2
Negative DNL
-0.4
-0.6
-0.6
0
25
50
75
100 125 150 175 200 225 250
0
25
FIGURE 2-8: Differential
Sample Rate.
50
75
100
Sample Rate (ksps)
Sample Rate (ksps)
Nonlinearity
(DNL)
vs.
FIGURE 2-11: Differential
Sample Rate (VDD = 2.7V).
Nonlinearity
(DNL)
512
896
vs.
1.0
1.0
VDD = 5V
0.8
VDD = 2.7V
0.8
fSAMPLE = 200 ksps
0.6
fSAMPLE = 75 ksps
0.6
0.4
DNL (LSB)
DNL (LSB)
5.0
FIGURE 2-10: Differential Nonlinearity (DNL) vs. VDD.
DNL (LSB)
DNL (LSB)
FIGURE 2-7:
4.5
VDD (V)
0.2
0.0
-0.2
-0.4
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
128
256
384
512
640
768
896
1024
0
Digital Code
FIGURE 2-9: Differential Nonlinearity
Code (Representative Part).
DS21294C-page 6
128
256
384
640
768
1024
Digital Code
(DNL)
vs.
FIGURE 2-12: Differential Nonlinearity
Code (Representative Part, VDD = 2.7V).
(DNL)
vs.
© 2007 Microchip Technology Inc.
MCP3002
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
0.4
0.4
0.3
0.3
VDD = 2.7V
Positive DNL
0.1
0.0
-0.1
Negative DNL
-0.2
fSAMPLE = 75 ksps
0.2
DNL (LSB)
DNL (LSB)
0.2
Positive DNL
0.1
0.0
-0.1
Negative DNL
-0.2
-0.3
-0.3
-0.4
-0.4
-50
-25
0
25
50
75
-50
100
-25
Temperature (°C)
FIGURE 2-13: Differential
Temperature.
Nonlinearity
(DNL)
50
75
100
vs.
FIGURE 2-16: Differential
Temperature (VDD = 2.7V).
Nonlinearity
(DNL)
vs.
1.0
All points taken at fSAMPLE = 200 ksps except
0.6
V DD = 2.7V, fSAMPLE = 75 ksps
All points taken at fSAMPLE = 200 ksps except
Offset Error (LSB)
0.8
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
VDD = 2.7V, fSAMPLE = 75 ksps
0.8
0.6
0.4
0.2
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 2-14: Gain Error vs. VDD.
FIGURE 2-17: Offset Error vs. VDD.
0.0
0.8
0.7
VDD = 2.7V
-0.1
fSAMPLE = 75 ksps
-0.2
-0.3
VDD = 5V
fSAMPLE = 200 ksps
-0.4
Offset Error (LSB)
Gain Error (LSB)
25
Temperature (°C)
1.0
Gain Error (LSB)
0
0.6
0.5
VDD = 2.7V
VDD = 5V
0.4
fSAMPLE = 75 ksps
fSAMPLE = 200 ksps
0.3
0.2
0.1
0.0
-0.5
-50
-25
0
25
50
75
Temperature (°C)
FIGURE 2-15: Gain Error vs. Temperature.
© 2007 Microchip Technology Inc.
100
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-18: Offset Error vs. Temperature.
DS21294C-page 7
MCP3002
80
80
70
70
60
60
VDD = 5V
SINAD (dB)
SNR (dB)
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
50
VDD = 2.7V
40
fSAMPLE = 75 ksps
30
VDD = 5V
fSAMPLE = 200 ksps
50
VDD = 2.7V
40
fSAMPLE = 75 ksps
30
20
20
10
10
0
fSAMPLE = 200 ksps
0
1
10
100
1
10
Input Frequency (kHz)
100
Input Frequency (kHz)
FIGURE 2-19: Signal to Noise Ratio (SNR) vs. Input
Frequency.
FIGURE 2-22:
Signal to Noise and Distortion
(SINAD) vs. Input Frequency.
0
80
-10
70
VDD = 5V
60
-30
V DD = 2.7V
-40
fSAMPLE = 75 ksps
SINAD (dB)
THD (dB)
-20
-50
-60
-70
fSAMPLE = 200 ksps
50
40
30
20
-80
V DD = 5V
-90
fSAMPLE = 200 ksps
VDD = 2.7V
10
fSAMPLE = 75 ksps
0
-100
1
10
-40
100
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
Input Frequency (kHz)
FIGURE 2-20: Total Harmonic Distortion (THD) vs.
Input Frequency.
FIGURE 2-23:
Signal to Noise and Distortion
(SINAD) vs. Signal Level.
10.0
10.0
9.9
ENOB (rms)
9.5
ENOB
9.8
9.7
9.6
9.0
V DD = 2.7V
fSAMPLE = 75 ksps
8.5
9.5
All points at fSAMPLE = 200 ksps
V DD = 5V
except VDD = 2.7V, fSAMPLE = 75 ksps
fSAMPLE = 200 ksps
9.4
8.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 2-21: Effective number of bits (ENOB) vs.
VDD.
DS21294C-page 8
1
10
100
Input Frequency (kHz)
FIGURE 2-24: Effective Number of Bits (ENOB) vs.
Input Frequency.
© 2007 Microchip Technology Inc.
MCP3002
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
600
100
90
V DD = 5V
80
fSAMPLE = 200 ksps
500
400
IDD (µA)
SFDR (dB)
70
60
50
VDD = 2.7V
40
fSAMPLE = 75 ksps
300
200
30
20
100
All points at fCLK = 3.2 MHz
10
except at V DD = 2.5V, fCLK = 1.2 MHz
0
0
1
10
100
2.0
2.5
3.0
3.5
Dynamic
Range
VDD = 5V
fSAMPLE = 200 ksps
fINPUT = 10.976 kHz
4096 points
0
20000
40000
60000
80000
600
550
500
450
400
350
300
250
200
150
100
50
0
100000
FIGURE 2-26: Frequency Spectrum of 10 kHz input
(Representative Part).
6.0
V DD = 2.7V
10
100
1000
10000
Clock Frequency (kHz)
FIGURE 2-29: IDD vs. Clock Frequency.
600
VDD = 2.7V
fSAMPLE = 75 ksps
500
fINPUT = 1.00708 kHz
4096 points
V DD = 5V
400
IDD (µA)
Amplitude (dB)
5.5
VDD = 5V
Frequency (Hz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
5.0
FIGURE 2-28: IDD vs. VDD.
IDD (µA)
Amplitude (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
4.5
VDD (V)
Input Frequency (kHz)
FIGURE 2-25: Spurious Free
(SFDR) vs. Input Frequency.
4.0
fCLK = 3.2 MHz
300
200
VDD = 2.7V
fCLK = 1.2 MHz
100
0
0
5000 10000 15000 20000 25000 30000 35000
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 1 kHz input
(Representative Part, VDD = 2.7V).
© 2007 Microchip Technology Inc.
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-30: IDD vs. Temperature.
DS21294C-page 9
MCP3002
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
70
2.0
Analog Input Leakage (nA)
CS = VDD
60
IDDS (pA)
50
40
30
20
10
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V DD = 5V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
75
100
Temperature (°C)
VDD (V)
FIGURE 2-31: IDDS vs. VDD.
FIGURE 2-33: Analog Input leakage current vs.
Temperature.
100.00
VDD = CS = 5V
IDDS (nA)
10.00
1.00
0.10
0.01
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-32: IDDS vs. Temperature.
DS21294C-page 10
© 2007 Microchip Technology Inc.
MCP3002
3.0
PIN DESCRIPTIONS
3.1
CH0/CH1
Analog inputs for channels 0 and 1 respectively. These
channels can programmed to be used as two independent channels in single ended-mode or as a single
pseudo-differential input where one channel is IN+ and
one channel is IN-. See Section 5.0 for information on
programming the channel configuration.
3.2
Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.3
Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.4
Serial Data Input (DIN)
The SPI port serial data input pin is used to clock in
input channel configuration data.
3.5
Serial Data Output (DOUT)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
4.0
DEVICE OPERATION
The MCP3002 A/D converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the second rising edge of
the serial clock after the start bit has been received.
Following this sample time, the input switch of the converter opens and the device uses the collected charge
on the internal sample and hold capacitor to produce a
serial 10-bit digital output code. Conversion rates of
200 ksps are possible on the MCP3002. See
Section 6.2 for information on minimum clock rates.
Communication with the device is done using a 3-wire
SPI compatible interface.
4.1
of the command string transmitted to the device. The
IN+ input can range from IN- to the reference voltage,
VDD. The IN- input is limited to ±100 mV from the VSS
rail. The IN- input can be used to cancel small signal
common-mode noise which is present on both the IN+
and IN- inputs.
For the A/D converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough time
to acquire a 10-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to
charge the capacitor, CSAMPLE. Consequently, larger
source impedances increase the offset, gain, and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above VSS,
then the 3FFh code will not be seen unless the IN+
input level goes above VDD level. If the voltage at IN+
is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then
the output code will be 3FFh.
4.2
The digital output code produced by an A/D Converter
is a function of the input signal and the reference voltage. For the MCP3002, VDD is used as the reference
voltage.
V REF
LSB Size = ------------1024
As the VDD level is reduced, the LSB size is reduced
accordingly. The theoretical digital output code produced by the A/D Converter is shown below.
1024*V IN
Digital Output Code = -----------------------V DD
Analog Inputs
The MCP3002 device offers the choice of using the analog input channels configured as two single-ended
inputs that are referenced to VSS or a single pseudo-differential input. The configuration setup is done as part of
the serial command before each conversion begins.
When used in the psuedo-differential mode, CH0 and
CH1 are programmed as the IN+ and IN- inputs as part
© 2007 Microchip Technology Inc.
Digital Output Code
where:
VIN = analog input voltage
VDD = supply voltage
DS21294C-page 11
MCP3002
VDD
RSS
Sampling
Switch
VT = 0.6V
CHx
CPIN
7 pF
VA
VT = 0.6V
SS
ILEAKAGE
±1 nA
RS = 1 kΩ
CSAMPLE
= DAC capacitance
= 20 pF
VSS
Legend
VA
RSS
CHx
CPIN
VT
ILEAKAGE
SS
RS
CSAMPLE
FIGURE 4-1:
=
=
=
=
=
=
signal source
source impedance
input channel pad
input pin capacitance
threshold voltage
leakage current at the pin
due to various junctions
sampling switch
sampling switch resistor
sample/hold capacitance
=
=
=
Analog Input Model.
Clock Frequency (MHz)
4.0
V DD = 5V
3.5
fSAMPLE = 200 ksps
3.0
2.5
2.0
1.5
VDD = 2.7V
fSAMPLE = 75 ksps
1.0
0.5
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input
resistance (RS) to maintain less than a 0.1 LSB
deviation in INL from nominal conditions.
DS21294C-page 12
© 2007 Microchip Technology Inc.
MCP3002
5.0
SERIAL COMMUNICATIONS
5.1
Overview
Communication with the MCP3002 is done using a
standard SPI-compatible serial interface. Initiating
communication with the device is done by bringing the
CS line low. See Figure 5-1. If the device was powered
up with the CS pin low, it must be brought high and
back low to initiate communication. The first clock
received with CS low and DIN high will constitute a start
bit. The SGL/DIFF bit and the ODD/SIGN bit follow the
start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended
or psuedo-differential mode. The ODD/SIGN bit selects
which channel is used in single ended mode, and is
used to determine polarity in psuedo-differential mode.
Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the
device. If the MSBF bit is high, then the data will come
from the device in MSB first format and any further
clocks with CS low, will cause the device to output
zeros. If the MSBF bit is low, then the device will output
the converted word LSB first after the word has been
transmitted in the MSB first format. Table 5-1 shows the
configuration bits for the MCP3002. The device will
begin to sample the analog input on the second rising
edge of the clock, after the start bit has been received.
The sample period will end on the falling edge of the
third clock following the start bit.
If necessary, it is possible to bring CS low and clock in
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 for more details on using the MCP3002
devices with hardware SPI ports.
If it is desired, the CS can be raised to end the conversion period at any time during the transmission. Faster
conversion rates can be obtained by using this technique if not all the bits are captured before starting a
new cycle. Some system designers use this method by
capturing only the highest order 8 bits and ‘throwing
away’ the lower 2 bits.
TABLE 5-1:
Configuration Bits for the MCP3002.
CONFIG
BITS
CHANNEL
SELECTION
SGL/
DIFF
ODD/
SIGN
0
SINGLE
ENDED MODE
1
0
+
1
1
PSEUDODIFFERENTIAL
MODE
0
0
IN+
IN-
0
1
IN-
IN+
GND
1
+
-
On the falling edge of the clock for the MSBF bit, the
device will output a low null bit. The next sequential 10
clocks will output the result of the conversion with MSB
first as shown in Figure 5-1. Data is always output from
the device on the falling edge of the clock. If all 10 data
bits have been transmitted and the device continues to
receive clocks while the CS is held low (and the MSBF
bit is high), the device will output the conversion result
LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
© 2007 Microchip Technology Inc.
DS21294C-page 13
MCP3002
tCYC
tCYC
tCSH
CS
tSUCS
HI-Z
DOUT
MS
BF
ODD/
SIGN
DIN
SGL/
DIFF
Start
CLK
ODD/
SIGN
Don’t Care
HI-Z
Null B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Bit
tSAMPLE
tCONV
tDATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See
Figure 5-2 for details on obtaining LSB first data.
** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes a high impedance
node.
FIGURE 5-1:
Communication with the MCP3002 using MSB first format only.
tCYC
tCSH
CS
tSUCS
Power Down
HI-Z
DOUT
tSAMPLE
MSBF
Start
DIN
SGL/
DIFF
ODD/
SIGN
CLK
Don’t Care
Null
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7* B8 B9
Bit
HI-Z
(MSB)
tCONV
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes a high impedance
node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
Communication with MCP3002 using LSB first format.
DS21294C-page 14
© 2007 Microchip Technology Inc.
MCP3002
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3002 with
Microcontroller (MCU) SPI Ports
with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the
SCLK from the MCU idles in the ‘low’ state, while
Figure 6-2 shows the similar case of SPI Mode 1,1
where the clock idles in the ‘high’ state.
With most microcontroller SPI ports, it is required to send
groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge.
Depending on how communication routines are used, it
is very possible that the number of clocks required for
communication will not be a multiple of eight. Therefore,
it may be necessary for the MCU to send more clocks
than are actually required. This is usually done by sending ‘leading zeros’ before the start bit, which are ignored
by the device. As an example, Figure 6-1 and Figure 62 show how the MCP3002 can be interfaced to a MCU
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains one leading zero before the
start bit. Arranging the leading zero this way produces
the output 10 bits to fall in positions easily manipulated
by the MCU. When the first 8 bits are transmitted to the
device, the MSB data bit is clocked out of the A/D Converter on the falling edge of clock number 6. After the
second eight clocks have been sent to the device, the
receive register will contain the lowest order eight bits of
the conversion results. Easier manipulation of the converted data can be obtained by using this method.
CS
SCLK
MCU latches data from A/D Converter
on rising edges of SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
MSBF
Start
SGL/
DIFF
ODD/
SIGN
Data is clocked out of
A/D Converter on falling edges
Don’t Care
NULL B9
BIT
DOUT
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
Start
Bit
MCU Transmitted Data
(Aligned with falling
edge of clock)
X
MCU Received Data
(Aligned with rising
edge of clock)
1
X
X
SGL/ ODD/ MSBF X
DIFF SIGN
X
X
X
X
0
(Null) B9
X
B8
B7
Data stored into MCU receive register
after transmission of first 8 bits
X = Don’t Care Bits
FIGURE 6-1:
B8
B6
B5
B4
B3
B2
B1
X
B0
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication with the MCP3002 using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D Converter
on rising edges of SCLK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HI-Z
DOUT
MCU Received Data
(Aligned with rising
edge of clock)
X = Don’t Care Bits
FIGURE 6-2:
MSBF
Start
DIN
MCU Transmitted Data
(Aligned with falling
edge of clock)
SGL/
DIFF
ODD/
SIGN
Data is clocked out of
A/D Converter on falling edges
Don’t Care
NULL B9
BIT
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
Start
Bit
X
1
SGL/ ODD/ MSBF X
DIFF SIGN
X
X
X
X
X
0
X (Null)
B9
X
B8
Data stored into MCU receive register
after transmission of first 8 bits
B7
B6
B5
B4
B3
B2
B1
B0
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication with the MCP3002 using 8-bit segments (Mode 1,1: SCLK idles high).
© 2007 Microchip Technology Inc.
DS21294C-page 15
MCP3002
6.2
Maintaining Minimum Clock Speed
When the MCP3002 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst case condition), the part will maintain
proper charge on the sample cap for 700 µs at
VDD = 2.7V and 1.5 ms at VDD = 5V. This means that at
VDD = 2.7V, the time it takes to transmit the 1.5 clocks
for the sample period and the 10 clocks for the actual
conversion must not exceed 700 µs. Failure to meet
this criteria may induce linearity errors into the conversion outside the rated specifications.
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals
that may be aliased back in to the conversion results.
This is illustrated in Figure 6-3 below where an op amp
is used to drive, filter, and gain the analog input of the
MCP3002. This amplifier provides a low impedance
output for the converter input and a low pass filter,
which eliminates unwanted high frequency noise.
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistors values, as well as,
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
6.4
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D converters, refer to AN-688 “Layout Tips for 12-Bit A/D Converter Applications”.
VDD
Connection
Device 4
Device 1
Device 3
VDD
Device 2
10 µF
VIN
R1
C1
+
R2
IN+
-
C2
MCP3002
FIGURE 6-4: VDD traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
INR3
R4
FIGURE 6-3: Typical
(2 pole Active Filter).
DS21294C-page 16
1 µF
MCP601
Anti-Aliasing
Filter
Circuit
© 2007 Microchip Technology Inc.
MCP3002
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Example:
MCP3002
I/PNNN e3
0725
8-Lead SOIC (150 mil)
Example:
MCP3002
ISN e3 0726
NNN
XXXXXXXX
XXXXYYWW
NNN
Example:
8-Lead MSOP
3002I e3
XXXXXX
YWWNNN
725NNN
Example:
8-Lead TSSOP
XXXX
3002 e3
YYWW
0725
NNN
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS21294C-page 17
MCP3002
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
8
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.348
.365
.400
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
DS21294C-page 18
© 2007 Microchip Technology Inc.
MCP3002
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
β
MILLMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
Overall Width
E
Molded Package Width
E1
3.90 BSC
Overall Length
D
4.90 BSC
1.75
6.00 BSC
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
1.04 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
© 2007 Microchip Technology Inc.
DS21294C-page 19
MCP3002
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.75
0.85
0.95
Standoff
A1
0.00
–
0.15
Overall Width
E
Molded Package Width
E1
3.00 BSC
Overall Length
D
3.00 BSC
Foot Length
L
Footprint
L1
1.10
4.90 BSC
0.40
0.60
0.80
0.95 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.08
–
0.23
Lead Width
b
0.22
–
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B
DS21294C-page 20
© 2007 Microchip Technology Inc.
MCP3002
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
2.90
3.00
3.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
© 2007 Microchip Technology Inc.
DS21294C-page 21
MCP3002
NOTES:
DS21294C-page 22
© 2007 Microchip Technology Inc.
MCP3002
APPENDIX A:
REVISION HISTORY
Revision C (January 2007)
This revision includes updates to the packaging
diagrams.
© 2007 Microchip Technology Inc.
DS21294C-page 23
MCP3002
NOTES:
DS21294C-page 24
© 2007 Microchip Technology Inc.
MCP3002
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
X
/XX
Temperature
Range
Package
MCP3002: 10-Bit Serial A/D Converter
MCP3002T: 10-Bit Serial A/D Converter
(Tape and Reel) (SOIC and TSSOP only)
Temperature Range:
I
= -40°C to +85°C
Package:
MS
P
SN
ST
=
=
=
=
Examples:
a)
MCP3002-I/P: Industrial Temperature,
PDIP package.
b)
MCP3002-I/SN: Industrial Temperature,
SOIC package.
c)
MCP3002-I/ST: Industrial Temperature,
TSSOP package.
d)
MCP3002-I/MS: Industrial Temperature,
MSOP package.
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
© 2007 Microchip Technology Inc.
DS21294C-page25
MCP3002
NOTES:
DS21294C-page 26
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS21294C-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
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EUROPE
Corporate Office
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Tel: 480-792-7200
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Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS21294C-page 28
© 2007 Microchip Technology Inc.