Implementing IIR Digital Filters AN540 Implementing IIR Digital Filters INTRODUCTION THEORY OF OPERATION This application note describes the implementation of various digital filters using the PIC17C42, the first member of Microchip’s 2nd generation 8-bit microcontrollers. The PIC17C42 is a very high speed 8-bit microcontroller with an instruction cycle time of 250ns (@ 16 MHz input clock). Even though PIC17C42 is an 8-bit device, it’s high speed and efficient instruction set allows implementation of digital filters for practical applications. Traditionally digital filters are implemented using expensive Digital Signal Processors (DSPs). In a system the DSP is normally a slave processor being controlled by either an 8- or 16-bit microcontroller. Where sampling rates are not high (esp. in mechanical control systems), a single chip solution is possible using the PIC17C42. Digital filters in most cases assume the following form of relationship between the output and input sequences. N i=o j=o The above equation basically states that the present output is a weighted sum of the past inputs and past outputs. In case of FIR filters, the weighted constants ai=0 and in case of IIR filters, at least one of the ai constant is non zero. In case of IIR, the above formula may be re written in terms of Z transform as: M This application note provides a few examples of implementing digital filters. Example code for 2nd order Infinite Impulse Response (IIR) filters is given. The following type of filters are implemented: • • • • M y(n) = - ∑ aiy(n - i) + ∑ bjx(n - j) H(z) = Y(z) X(z) ∑ bkZ -k k=0 N = 1 + ∑ akZ -k k=1 The above equation can further be rewritten in difference equation format as follows: Low Pass High Pass Band Pass Band Stop (notch) filter M N i=1 j=o y(n) = - ∑ aiy(n - i) + ∑ bjx(n - j) Realization of the above equation is called as the Direct Form II structure. For example, in case of a second order structure, M=N=2, gives the following difference equations : This application note does not explain how to design a filter. Filter design theory is well established and is beyond the scope of this application note. It is assumed that a filter is designed according to the desired specifications. The desired digital filters may be designed using either standard techniques or using commonly available digital filter design software packages. Finite Impulse Response (FIR) filters have many advantages over IIR filters, but are much more resource intensive (both in terms of execution time and RAM). On the other hand, IIR filters are quite attractive for implementing with the PIC17C42 resources. Especially where phase information is not so important, IIR filters are a good choice (FIR filters have a linear phase response). Of the various forms used for realizing digital filters (like, Direct form, Direct II form, Cascade form, Parallel, Lattice structure, etc.) the Direct II form is used in this application note. It is easy to understand and simple macros can be built using these structures. d(n) = x(n) + a1d(n-1) + a2d(n-2) (1) y(n) = b0d(n) + b1d(n-1) + b2(d(n-2) (2) The above difference equations may be represented as shown in Figure 1. FIGURE 1 - 2ND ORDER DIRECT FORM II STRUCTURE (TRANSPOSED) X(n) Y(n) + b0 b1 Z -1 -a1 Z -1 b2 © 1993 Microchip Technology Inc. -a2 DS00540B-page 1 4-129 4 Implementing IIR Digital Filters TABLE 2 - FILTER COEFFICIENTS The structure as shown in Figure 1 may be cascaded to attain a higher order filter. For example, if two stages are cascaded together, a 4th Order IIR Filter is obtained. This way, the output of the 1st stage becomes the input to the second stage. Multiple order filters are thus implemented by cascading a 2nd order filter structure as shown in Figure 1. Co-efficients a1 A 4th order IIR Filter is implemented by cascading two structures shown in Figure 1. The output Y (output of each filter stage) is computed by direct implementation of Equations (1) & (2). Since each stage is similar algorithmically, it is implemented as a Macro using Microchip’s Assembler/Linker for PIC17C42. This Macro (labelled “BIQUAD”) is called twice for implementing a 4th order filter. The output of the 1st stage is directly fed to the input of the second stage without any scaling. The BIQUAD macro is a generic macro and can be used for all IIR filters whether it is Low Pass, High Pass, Band Pass or Band Stop. A general purpose 16x16 multiplier routine is also provided. This routine is implemented as a straight line code for speed considerations. Stage 2 0.147827 0.765900 0.698273 0.499908 0.698273 TABLE 1 - FILTER CONSTANTS Impulse Response 8000 600 Hz Upper Band Edge 500 Hz 1 Khz Nominal Gain 1.0 0.0 Nominal Ripple 0.01 0.05 Maximum Ripple 0.00906 0.04601 Ripple in dB 0.07830 -26.75 6000 Magnitude 0.0 b2 FIGURE 2 - IMPULSE RESPONSE CAPTURED FROM PIC-MASTER The 4th order IIR filter implemented is a Low Pass Filter with the specifications as shown in Table 1. Lower Band Edge b1 The sample 4th order Low Pass IIR Filter is tested by analyzing the impulse response of the filter. An impulse signal is fed as input to the filter. This is simulated by forcing the input to the filter by a large quantity (say 7F00h) on the first input sample, and the all zeros from the 2nd sample onwards. The output sequence is the filter’s impulse response and is captured into the PICMASTER’s (Microchip’s Universal In-Circuit Emulator) real time trace buffer. This captured data from PICMASTER is saved to file and analyzed. Analysis was done using MathCad for Windows and DSP Analysis program from Burr-Brown (DSPLAY). The Fourier Transform of this Impulse response of the filter should display the Filter’s frequency response, in this case being a Low Pass type. The plots of the impulse response and the frequency response are shown in figures below. Scaling is required depending on the particular application. The user can modify the code very easily without any penalty on speed. Also, saturation arithmetic is not used. Overflows can be avoided by limiting the input sequence amplitude. All numbers are assumed to be 16 bits in Q15 format (15 decimal points, MSB is sign bit). Thus the user must scale and sign extend the input sequence accordingly. For example, if the input is from a 12-bit A/D converter, the user must sign extend the 12-bit input if bit 11 is a one. BAND2 b0 -0.133331 0.167145 0.285431 0.462921 0.285431 The above filter co-efficients (5 per stage) are quantized to Q15 format (i.e they are multiplied by 32768) and saved in program memory (starting at label “_coeff_lpass”). The constants for both the stages are read into data memory using TLRD and TABLRD instructions in the Initialization Routine (labelled “initFilter”). The user may read the coefficients of only one stage at a time and save some RAM at the expense of speed. IMPLEMENTATION BAND1 a2 Stage 1 4000 2000 0 0 8 16 24 32 40 48 56 64 -2000 -4000 Sampling Frequency = 2 Khz The Low Pass Filter is designed using a digital filter design package (DFDP by Atlanta Signal Processors Inc.). The filter package produces filter constants of the structure shown in Table 1. Table 2 shows the filter coefficients that are obtained for the above Low Pass filter specification. Time *0.5 (mSec) DSPLAY is a trademark of Burr-Brown DFDP is a trademark of Atlanta Signal Processing Inc. Windows is a trademark of Microsoft Corporation MathCad is a registered trademark of MathSoft, Inc. DS00540B-page 2 © 1993 Microchip Technology Inc. 4-130 Implementing IIR Digital Filters FIGURE 3 - SPECTRUM COMPUTED FROM IMPULSE RESPONSE FIGURE 4 - LOG MAGNITUDE SPECTRUM OF IMPULSE RESPONSE Frequency Response Frequency Response 600 10 500 -10 Magnitude (dB) Magnitude 0 400 300 200 -20 -30 -40 -50 -60 -70 100 -80 -90 0 0 64 128 192 256 320 384 448 0 512 64 128 192 256 320 384 448 512 Frequency/512 (KHz) Frequency/512 (KHz) 4 PERFORMANCE The resource requirements for filter implementations using PIC17C42 is given below. These numbers can be used to determine whether a higher order filter can be executed in real time. The same information may be used to determine the highest sampling rate possible. Digital filters are also needed in Process Control where notch filters and low pass filters are desired because the signals from sensors are transmitted over long lines, especially in a very noisy environment. In this case typically a notch filter (centering 50Hz or 60Hz) is used. In case of eliminating background noise, a band stop filter (e.g. 40Hz to 120Hz) is used. The sample code given in this application note can be used to design a feedback control system's digital compensator. For example, a typical DC Motor's digital compensator (like dead beat compensator) is of second order and has the same filter structure as is implemented in this application note. FILTER APPLICATIONS Digital filters find applications in many areas especially involving processing of real world signals. In some applications like ABS systems in an automobile, digital filtering becomes a must. In this case elimination of noise (especially glitches and false readings of sensors) is very critical and thus the requirement of digital signal processing. TABLE 3 - RESOURCE REQUIREMENTS Timing (Cycles)† #of Filter Stages*775 + 16 Author: Amar Palacherla Logic Products Division Program Memory (locations)† #of Filter Stages*68 + 290 RAM (File Registers) #of Filter Stages*16+16 †: The above numbers do not include the initialization routine. TABLE 4 - RESOURCE REQUIREMENTS Filter Order Cycles 2 791 4 6 8 10 Real Time (@ 16 MHz) Maximum Sampling Program Memory† 358 RAM 197.75 uSec 5.05 Khz 32 1566 391.5 uSec 2.55 Khz 426 48 2341 585.25 uSec 1.7 Khz 494 64 3116 779.0 uSec 1.28 Khz 562 80 3891 972.75 uSec 1.0 Khz 630 96 †: The above numbers do not include the initialization routine. © 1993 Microchip Technology Inc. DS00540B-page 3 4-131 Implementing IIR Digital Filters APPENDIX A: IIR.LST MPASM B0.54 Digital IIR Filter Using PIC17C42 TITLE LIST PAGE 1 “Digital IIR Filter Using PIC17C42” P=17C42, C=120, T=ON, R=DEC, N=0 ; include “17c42.h” ; include “17c42.mac” 0001 ; include “17c42iir.mac” ;******************************************************************* ; PIC17C42 MACRO ; ; Macro For A Bi-Quad IIR Filter ; 2nd order Direct Form (Transposed) Type ; ; Filter co-efficients B0 & B2 are assumed equal ; ; The difference equations for each cascade section is given by : ; Y(n) = B0*D(n) + B1*D(n-1) + B2*D(n-2) ; D(n) = X(n) - A1*D(n-1) - A2*D(n-2) ; where X(n) = input sample, Y(n) = output of filter ; and A1, A2, B0, B1, B2 are the Filter Co-efficients ; ; The above difference equations are only for 1 section of a ; 2nd order Direct_Form II Filter structure (IIR) ; ; NOTE : ; It is possible to design the above structures ; such that the co-efficients B0 = B2. If this is the ; case, ; Y(n) = B0*[D(n) + D(n-2)] = B2*[D(n) + D(n-2)] ; This way, one multiplication can be avoided ; ; If a 4th order filter is to be implemented, the output of ; the 1st structure should be input to the 2nd cascade section ; ; Timing (WORST CASE) : ; 59+4*179 = 775 Cycles ; (194 uS @ 16 Mhz) ; Program Memory : ; 63 locations ; ;******************************************************************* ; The sample filters are desined so that B0=B2 ; This saves 1 multiplication ; B0_EQUALS_B2 equ TRUE ; ;******************************************************************* ; Parameters to BIQUAD Macro : ; Filter Constants A1, A2, B0, B1, B2 ; & D(n), D(n-1), D(n-2), filter stage # ; BIQUAD MACRO Ax1,Ax2,Bx0,Bx1,Dn,Dn_1,Dn_2,stage ; ; Compute Ax2*D(n-2) DS00540B-page 4 © 1993 Microchip Technology Inc. 4-132 Implementing IIR Digital Filters ; MOVFP16 Dn_2,AARG ; D(n-2) = multiplier MOVFP16 Ax2,BARG ; A2 = multiplicand call DblMult ; (ACCd,ACCc) = A2*D(n-2) ; ; Add product to output of 1st section ; Save result in 32 bit Accumulator ; ADD32 DPX,ACC ; ; Compute A1*D(n-1) ; MOVFP16 Dn_1,AARG ; AARG = D(n-2) = multiplier MOVFP16 Ax1,BARG ; BARG = A2 = multiplicand call DblMult ; (ACCd,ACCc) = A1*D(n-1) ; ; Compute A1*D(n-1) + A2*D(n-2) + output of previous section ; multiplications already done, so simply perform a 32 bit add ; of previously obtained multiplication results ; ADD32 DPX,ACC ; ACC = A1*D(n-1)+A2*D(n-2)+(output of 1st ; ; ; save the upper 16 bits of D(n) from the 32 bit accumulator ; left shift the result by 1, to adjust the decimal point after ; a Q15*Q15 multiplication ; rlcf ACC+B1,w rlcf ACC+B2,w movwf Dn rlcf ACC+B3,w ; decimal adjust ( mult by 2) movwf Dn+B1 ; ; Compute B2 * [D(n) + D(n-2)] ; if B0_EQUALS_B2 ADD16ACC Dn_2,Dn,AARG ; AARG = Dn + D(n-2) = multiplier MOVFP16 Bx0,BARG ; BARG = A2 = multiplicand call DblMult ; (ACCd,ACCc) = B2*[D(n)+D(n-2)] MOVPF32 DPX,ACC else MOVFP16 MOVFP16 call MOVPF32 Bx0,BARG Dn,AARG DblMult DPX,ACC ; B0*D(n) MOVFP16 Bx2,BARG MOVFP16 Dn_2,AARG call DblMult ; B2*D(n-2) ADD32 DPX,ACC endif ; ; Shift down D(n-1) to D(n-2) after D(n-2) usage is no longer required. ; This way in the next iteration D(n-2) is equal to the present D(n-1) ; movfp Dn_1,AARG+B0 movpf AARG+B0,Dn_2 ; Shift down D(n-1) movfp Dn_1+B1,AARG+B1 movpf AARG+B1,Dn_2+B1 ; AARG = D(n-1) = multiplier MOVFP16 Bx1,BARG ; BARG = B1 = multiplicand call DblMult ; (ACCd,ACCc) = B1*D(n-1) ; ; Compute Output Y = B1*D(n-1) + B2*D(n-2) + B0*D(n) ; = B1*D(n-1) + B0*[D(n) + D(n-2)] ; Since all multiplications are already done, simply perform a ; 32 bit addition ; ADD32 DPX,ACC ; ACC = B1*D(n-1) + B2*D(n-2) + B0*D(n) © 1993 Microchip Technology Inc. DS00540B-page 5 4-133 4 Implementing IIR Digital Filters ; ; Shift down D(n) to D(n-1) so that in the next iteration, the new ; D(n-1) is the present D(n) ; MOV16 Dn,Dn_1 ; Shift down D(n) to D(n-1) ; ENDM ; ;******************************************************************* ; Second Order Direct Form IIR Filter ; ; ; In the code given below, a 4th order IIR Elliptic Lowpass Filter ; is implemented. Other order filters may be implemented by ; taking the following example code as a basis. ; ; The specifications of the filter are : ; ; Sampling Frequency = 2.0 Khz ; ; Filter Type = 4th Order Elliptic Lowpass Filter ; ; Band1 Band2 ; Lower Band Edge 0.0 600 Hz ; Upper Band Edge 500 Hz 1 Khz ; Nominal Gain 1.0 0.0 ; Nominal Ripple 0.01 0.05 ; Maximum Ripple 0.00906 0.04601 ; Ripple in dB 0.07830 -26.75 ; ; The Filter Co-efficients for the above specifications ; of the filter are computed as follows : ; ; 1st Section : ; A11 = -0.133331 ; A12 = 0.167145 ; B10 = 0.285431 ; B11 = 0.462921 ; B12 = 0.285431 ; 2nd Section ; A21 = 0.147827 ; A22 = 0.765900 ; B20 = 0.698273 ; B21 = 0.499908 ; B22 = 0.698273 ; ; ; Performance (WORST Case): ; ; Cycles = #of Filter Stages*775 + 16 ; = 2*775+16 = 1566 Cycles ; ( 391 uSec) ; per each sample. Initialization ; time after reset is not counted ; Timing measured with B0_EQUALS_B2 ; set to TRUE (see BIQUAD Macro for ; explanation ; ; Program Memory : ; = 16+ # of FilterStages * (BIQUAD ; + filter co-efficients) ; + multiplier ; = 16+2*(63+5)+274 = 421 locations ; (excluding initialization) ; ; RAM usage = 48 file registers ; RAM usage/each additional stage = 16 file regs ; DS00540B-page 6 © 1993 Microchip Technology Inc. 4-134 Implementing IIR Digital Filters ; ; This time is less than 2 Khz (500 uSec), ; which means real time filtering is possible ; ;******************************************************************* 0000 0004 0018 0004 001C 0004 0020 0022 0024 0026 0026 0028 002A 0002 0002 0002 0000 0002 0002 0002 002C 002E 0030 0032 0034 0036 0036 0038 003A 003C 003E 0002 0002 0002 0002 0002 0000 0002 0002 0002 0002 0002 0040 0042 0044 0044 0002 0002 0000 0004 0002 000A 0001 0000 0000 0000 0001 ;******************************************************************* ; ; CBLOCK 0 B0,B1,B2,B3 ENDC ;******************************************************************* ; CBLOCK 0x18 DPX,DPX1,DPX2,DPX3 ; arithmetic accumulator AARG,AARG1,BARG,BARG1 ; multiply arguments ENDC ; CBLOCK Dn1, Dn1_Hi Dn1_1, Dn1_1_Hi Dn1_2, Dn1_2_Hi Dn2, Dn2_Hi Dn2_1, Dn2_1_Hi Dn2_2, Dn2_2_Hi ENDC CBLOCK A11, A11_Hi A12, A12_Hi B10, B10_Hi B11, B11_Hi B12, B12_Hi A21, A22, B20, B21, B22, ENDC ; 1st Section Filter Co-efficients A21_Hi A22_Hi B20_Hi B21_Hi B22_Hi ; 2nd Section Filter Co-efficients CBLOCK X, X1 Y, Y1 ; 16 bits of input stream ; 16 bits of filter output ACC, ACC1, ACC2, ACC3 ENDC ; 32 bit accumulator for computations ; FltStage .set 2 NumCoeff equ (5*FltStage) ; 5 Co-eff per stage ; LPASS .set TRUE HPASS .set FALSE BPASS .set FALSE ; select the desired filter type BSTOP .set FALSE ; SIGNED equ TRUE ; Set This To ‘TRUE’ for signed multi ; ; and ‘FALSE’ for unsigned. ; ;******************************************************************* ; Test Program For Low Pass Filter ;******************************************************************* ORG 0x0000 call initFilter ; start 0000 E00D © 1993 Microchip Technology Inc. DS00540B-page 7 4-135 4 Implementing IIR Digital Filters 0001 0002 0003 0004 B000 0140 B07F 0141 0005 E022 0006 A442 0007 0008 0009 000A 000B AE43 0000 2940 2941 C005 000C C00C movlw movwf movlw movwf 0x00 X 0x7f X+B1 ; set initial Xn = X(0) = 0x7f00 ; test for impulse response ; NextPoint call IIR_Filter tlwt _LOW,Y tracePoint tablwt _HIGH,0,Y+B1 nop clrf X ; set X(n) = 0 , n <> 0 clrf X+B1 ; for simulating an Impulse goto NextPoint ; self goto self ; ;******************************************************************* ; initFilter ; ; ; At first read the Filter Co-efficients from Prog. Mem to Data RAM if 000D 000E 000F 0010 B0C1 010D B001 010E endif if endif if endif if LPASS movlw movwf movlw movwf _coeff_lpass tblptrl page _coeff_lpass tblptrh HPASS movlw movwf movlw movwf _coeff_hpass tblptrl page _coeff_hpass tblptrh BPASS movlw movwf movlw movwf _coeff_bpass tblptrl page _coeff_bpass tblptrh BSTOP movlw movwf movlw movwf _coeff_bstop tblptrl page _coeff_bstop tblptrh endif ; 0011 0012 0013 0014 B02C 0101 8404 8D04 0015 B00A 0016 A92C 0017 0018 0019 001A A000 AB00 1700 C017 001B B020 movlw movwf bsf bcf A11 fsr0 _fs0 _fs1 ; auto increment ; ; Read Filter Co-efficients from Program Memory ; movlw NumCoeff tablrd _LOW,_INC,A11 ; garbage NextCoeff tlrd _LOW,indf0 tablrd _HIGH,_INC,indf0 decfsz wreg goto NextCoeff ; ; Initilize “Dn”s to zero ; movlw Dn1 DS00540B-page 8 © 1993 Microchip Technology Inc. 4-136 Implementing IIR Digital Filters 001C 0101 001D B00C movwf movlw fsr0 6*FltStage clrf decfsz goto indf0 wreg NextClr NextClr 001E 2900 001F 1700 0020 C01E ; 0021 0002 return ; ;******************************************************************* ; 1st Cascade Section ;******************************************************************* ; IIR_Filter 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 8804 1941 1940 2900 1900 0145 6040 0146 6041 0147 ; ; Compute D(n) = X(n) + A1*D(n-1) + A2*D(n-2) ; Since the filter constants are computated in Q15 format, ; X(n) must be multiplied by 2**15 and then added to the ; other terms. ; ; Move Input to accumulator after proper scaling ; bcf _carry rrcf X+B1 rrcf X clrf wreg ; Scale the input X rrcf wreg movwf ACC+B1 movfp X,wreg movwf ACC+B2 movfp X+B1,wreg movwf ACC+B3 ; ACC = scaled input : X*(2**15) ; ; 1st Biquad filter section ; BIQUAD A11,A12,B10,B11,Dn1,Dn1_1,Dn1_2,1 ; ; Compute A12*D(n-2) ; 002C 7C24 002D 7D25 MOVFP MOVFP Dn1_2+B0,AARG+B0 Dn1_2+B1,AARG+B1 ; move Dn1_2(B0) to AARG(B0) ; move Dn1_2(B1) to AARG(B1) 002E 7E2E 002F 7F2F MOVFP MOVFP A12+B0,BARG+B0 A12+B1,BARG+B1 ; move A12(B0) to BARG(B0) ; move A12(B1) to BARG(B1) 0030 E0AF 0031 0032 0033 0034 0035 0036 call DblMult ; ; Add product to output of 1st section ; Save result in 32 bit Accumulator ; 6018 0F44 6019 1145 601A 1146 MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0 DPX+B1,WREG ACC+B1 DPX+B2,WREG ACC+B2 © 1993 Microchip Technology Inc. ; (ACCd,ACCc) = A2*D(n-2) ; ; ; ; ; ; get add get add get add lowest byte lowest byte 2nd byte of 2nd byte of 3rd byte of 3rd byte of of DPX into w of ACC, save in ACC(B0) DPX into w ACC, save in ACC(B1) DPX into w ACC, save in ACC(B2) DS00540B-page 9 4-137 4 Implementing IIR Digital Filters 0037 601B 0038 1147 MOVFP ADDWFC ; ; ; DPX+B3,WREG ACC+B3 ; get 4th byte of DPX into w ; add 4th byte of ACC, save in ACC(B3) Compute A1*D(n-1) 0039 7C22 003A 7D23 MOVFP MOVFP Dn1_1+B0,AARG+B0 Dn1_1+B1,AARG+B1 ; move Dn1_1(B0) to AARG(B0) ; move Dn1_1(B1) to AARG(B1) 003B 7E2C 003C 7F2D MOVFP MOVFP A11+B0,BARG+B0 A11+B1,BARG+B1 ; move A11(B0) to BARG(B0) ; move A11(B1) to BARG(B1) 003D E0AF 003E 003F 0040 0041 0042 0043 0044 0045 6018 0F44 6019 1145 601A 1146 601B 1147 0046 0047 0048 0049 004A 1A45 1A46 0120 1A47 0121 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 6024 0E20 011C 6025 1021 011D 7E30 7F31 E0AF 5844 5945 5A46 5B47 call DblMult ; (ACCd,ACCc) = A1*D(n-1) ; ; Compute A1*D(n-1) + A2*D(n-2) + output of previous section ; multiplications already done, so simply perform a 32 bit add ; of previously obtained multiplication results ; MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0 DPX+B1,WREG ACC+B1 DPX+B2,WREG ACC+B2 DPX+B3,WREG ACC+B3 ; ; ; ; ; ; ; ; get add get add get add get add lowest byte lowest byte 2nd byte of 2nd byte of 3rd byte of 3rd byte of 4th byte of 4th byte of of DPX into w of ACC,save in ACC(B0) DPX into w ACC, save in ACC(B1) DPX into w ACC, save in ACC(B2) DPX into w ACC, save in ACC(B3) ; ; ; save the upper 16 bits of D(n) from the 32 bit accumulator ; left shift the result by 1, to adjust the decimal point after ; a Q15*Q15 multiplication ; rlcf ACC+B1,w rlcf ACC+B2,w movwf Dn1 rlcf ACC+B3,w ; decimal adjust ( mult by 2) movwf Dn1+B1 ; ; Compute B2 * [D(n) + D(n-2)] ; if B0_EQUALS_B2 movfp addwf movwf movfp addwfc movwf MOVFP MOVFP call MOVPF MOVPF MOVPF MOVPF Dn1_2+B0,wreg Dn1+B0,w AARG+B0 Dn1_2+B1,wreg Dn1+B1,w AARG+B1 B10+B0,BARG+B0 B10+B1,BARG+B1 DblMult DPX+B0,ACC+B0 DPX+B1,ACC+B1 DPX+B2,ACC+B2 DPX+B3,ACC+B3 DS00540B-page 10 ; ; ; ; ; ; ; move B10(B0) to BARG(B0) move B10(B1) to BARG(B1) (ACCd,ACCc) = B2*[D(n)+D(n-2)] move DPX(B0) to ACC(B0) move DPX(B1) to ACC(B1) move DPX(B2) to ACC(B2) move DPX(B3) to ACC(B3) © 1993 Microchip Technology Inc. 4-138 Implementing IIR Digital Filters else MOVFP16 MOVFP16 call MOVPF32 MOVFP16 MOVFP16 call ADD32 0058 0059 005A 005B 005C 005D 005E 7C22 5C24 7D23 5D25 7E32 7F33 E0AF 005F 0060 0061 0062 0063 0064 0065 0066 6018 0F44 6019 1145 601A 1146 601B 1147 0067 0068 0069 006A 6020 0122 6021 0123 006B 7C2A 006C 7D2B 006E 7F39 006F E0AF 0070 0071 0072 0073 0074 0075 0076 B10,BARG Dn1,AARG DblMult DPX,ACC Bx2,BARG Dn1_2,AARG DblMult DPX,ACC ; B0*D(n) ; B2*D(n-2) endif ; ; Shift down D(n-1) to D(n-2) after D(n-2) usage is no longer required. ; This way in the next iteration D(n-2) is equal to the present D(n-1) ; movfp Dn1_1,AARG+B0 movpf AARG+B0,Dn1_2 ; Shift down D(n-1) movfp Dn1_1+B1,AARG+B1 movpf AARG+B1,Dn1_2+B1 ; AARG = D(n-1) = multiplier MOVFP B11+B0,BARG+B0 ; move B11(B0) to BARG(B0) MOVFP B11+B1,BARG+B1 ; move B11(B1) to BARG(B1) call DblMult ; (ACCd,ACCc) = B1*D(n-1) ; ; Compute Output Y = B1*D(n-1) + B2*D(n-2) + B0*D(n) ; = B1*D(n-1) + B0*[D(n) + D(n-2)] ; Since all multiplications are already done, simply perform a ; 32 bit addition ; MOVFP DPX+B0,WREG ; get lowest byte of DPX into w ADDWF ACC+B0 ; add lowest byte of ACC, save in ACC(B0) MOVFP DPX+B1,WREG ; get 2nd byte of DPX into w ADDWFC ACC+B1 ; add 2nd byte of ACC, save in ACC(B1) MOVFP DPX+B2,WREG ; get 3rd byte of DPX into w ADDWFC ACC+B2 ; add 3rd byte of ACC, save in ACC(B2) MOVFP DPX+B3,WREG ; get 4th byte of DPX into w ADDWFC ACC+B3 ; add 4th byte of ACC, save in ACC(B3) ; ; Shift down D(n) to D(n-1) so that in the next iteration, the new ; D(n-1) is the present D(n) ; MOVFP Dn1+B0,WREG ; get byte of Dn1 into w MOVWF Dn1_1+B0 ; move to Dn1_1(B0) MOVFP Dn1+B1,WREG ; get byte of Dn1 into w MOVWF Dn1_1+B1 ; move to Dn1_1(B1) ; ; ; 2nd Biquad filter section ; BIQUAD A21,A22,B20,B21,Dn2,Dn2_1,Dn2_2,2 ; ; Compute A22*D(n-2) ; MOVFP Dn2_2+B0,AARG+B0 ; move Dn2_2(B0) to AARG(B0) MOVFP Dn2_2+B1,AARG+B1 ; move Dn2_2(B1) to AARG(B1) 006D 7E38 MOVFP A22+B0,BARG+B0 ; move A22(B0) to BARG(B0) MOVFP A22+B1,BARG+B1 ; move A22(B1) to BARG(B1) call DblMult ; (ACCd,ACCc) = A2*D(n-2) ; ; Add product to output of 1st section ; Save result in 32 bit Accumulator ; 6018 0F44 6019 1145 601A 1146 601B MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP DPX+B0,WREG ACC+B0 DPX+B1,WREG ACC+B1 DPX+B2,WREG ACC+B2 DPX+B3,WREG © 1993 Microchip Technology Inc. ; ; ; ; ; ; ; get add get add get add get lowest byte of DPX into w lowest byte of ACC, save in ACC(B0) 2nd byte of DPX into w 2nd byte of ACC, save in ACC(B1) 3rd byte of DPX into w 3rd byte of ACC, save in ACC(B2) 4th byte of DPX into w DS00540B-page 11 4-139 4 Implementing IIR Digital Filters 0077 1147 ADDWFC ; ; ; ACC+B3 ; add 4th byte of ACC, save in ACC(B3) Compute A1*D(n-1) 0078 7C28 0079 7D29 MOVFP MOVFP Dn2_1+B0,AARG+B0 Dn2_1+B1,AARG+B1 ; move Dn2_1(B0) to AARG(B0) ; move Dn2_1(B1) to AARG(B1) 007A 7E36 007B 7F37 MOVFP MOVFP A21+B0,BARG+B0 A21+B1,BARG+B1 ; move A21(B0) to BARG(B0) ; move A21(B1) to BARG(B1) 007C E0AF 007D 007E 007F 0080 0081 0082 0083 0084 call DblMult ; (ACCd,ACCc) = A1*D(n-1) ; ; Compute A1*D(n-1) + A2*D(n-2) + output of previous section ; multiplications already done, so simply perform a 32 bit add ; of previously obtained multiplication results ; 6018 0F44 6019 1145 601A 1146 601B 1147 0085 0086 0087 0088 0089 1A45 1A46 0126 1A47 0127 008A 008B 008C 008D 008E 008F 602A 0E26 011C 602B 1027 011D MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0 DPX+B1,WREG ACC+B1 DPX+B2,WREG ACC+B2 DPX+B3,WREG ACC+B3 ; ; ; ; ; ; ; ; get add get add get add get add lowest byte of DPX into w lowest byte of ACC, save in ACC(B0) 2nd byte of DPX into w 2nd byte of ACC, save in ACC(B1) 3rd byte of DPX into w 3rd byte of ACC, save in ACC(B2) 4th byte of DPX into w 4th byte of ACC, save in ACC(B3) ; ; ; save the upper 16 bits of D(n) from the 32 bit accumulator ; left shift the result by 1, to adjust the decimal point after ; a Q15*Q15 multiplication ; rlcf ACC+B1,w rlcf ACC+B2,w movwf Dn2 rlcf ACC+B3,w ; decimal adjust ( mult by 2) movwf Dn2+B1 ; ; Compute B2 * [D(n) + D(n-2)] ; if B0_EQUALS_B2 movfp addwf movwf movfp addwfc movwf Dn2_2+B0,wreg Dn2+B0,w AARG+B0 Dn2_2+B1,wreg Dn2+B1,w AARG+B1 0090 7E3A 0091 7F3B MOVFP MOVFP B20+B0,BARG+B0 B20+B1,BARG+B1 0092 0093 0094 0095 0096 call MOVPF MOVPF MOVPF MOVPF DblMult DPX+B0,ACC+B0 DPX+B1,ACC+B1 DPX+B2,ACC+B2 DPX+B3,ACC+B3 E0AF 5844 5945 5A46 5B47 ; move B20(B0) to BARG(B0) ; move B20(B1) to BARG(B1) ; ; ; ; ; (ACCd,ACCc) = B2*[D(n)+D(n-2)] move DPX(B0) to ACC(B0) move DPX(B1) to ACC(B1) move DPX(B2) to ACC(B2) move DPX(B3) to ACC(B3) else DS00540B-page 12 © 1993 Microchip Technology Inc. 4-140 Implementing IIR Digital Filters MOVFP16 MOVFP16 call MOVPF32 MOVFP16 MOVFP16 call ADD32 0097 0098 0099 009A 009B 009C 009D 7C28 5C2A 7D29 5D2B 7E3C 7F3D E0AF 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 6018 0F44 6019 1145 601A 1146 601B 1147 00A6 00A7 00A8 00A9 6026 0128 6027 0129 B20,BARG Dn2,AARG DblMult DPX,ACC Bx2,BARG Dn2_2,AARG DblMult DPX,ACC ; B0*D(n) ; B2*D(n-2) endif ; ; Shift down D(n-1) to D(n-2) after D(n-2) usage is no longer required. ; This way in the next iteration D(n-2) is equal to the present D(n-1) ; movfp Dn2_1,AARG+B0 movpf AARG+B0,Dn2_2 ; Shift down D(n-1) movfp Dn2_1+B1,AARG+B1 movpf AARG+B1,Dn2_2+B1 ; AARG = D(n-1) = multiplier MOVFP B21+B0,BARG+B0 ; move B21(B0) to BARG(B0) MOVFP B21+B1,BARG+B1 ; move B21(B1) to BARG(B1) call DblMult ; (ACCd,ACCc) = B1*D(n-1) ; ; Compute Output Y = B1*D(n-1) + B2*D(n-2) + B0*D(n) ; = B1*D(n-1) + B0*[D(n) + D(n-2)] ; Since all multiplications are already done, simply perform a ; 32 bit addition ; MOVFP DPX+B0,WREG ; get lowest byte of DPX into w ADDWF ACC+B0 ; add lowest byte of ACC, save in ACC(B0) MOVFP DPX+B1,WREG ; get 2nd byte of DPX into w ADDWFC ACC+B1 ; add 2nd byte of ACC, save in ACC(B1) MOVFP DPX+B2,WREG ; get 3rd byte of DPX into w ADDWFC ACC+B2 ; add 3rd byte of ACC, save in ACC(B2) MOVFP DPX+B3,WREG ; get 4th byte of DPX into w ADDWFC ACC+B3 ; add 4th byte of ACC, save in ACC(B3) ; ; Shift down D(n) to D(n-1) so that in the next iteration, the new ; D(n-1) is the present D(n) ; MOVFP Dn2+B0,WREG ; get byte of Dn2 into w MOVWF Dn2_1+B0 ; move to Dn2_1(B0) MOVFP Dn2+B1,WREG ; get byte of Dn2 into w MOVWF Dn2_1+B1 ; move to Dn2_1(B1) ; ; ; The filter output is now computed ; Save the Upper 16 Bits of 32 bit Accumulator into Y after ; adjusting the decimal point ; MOV16 00AA 00AB 00AC 00AD 6046 0142 6047 0143 ACC+B2,Y MOVFP MOVWF MOVFP MOVWF ACC+B2+B0,WREG Y+B0 ACC+B2+B1,WREG Y+B1 ; ; ; ; get byte of ACC+B2 into w move to Y(B0) get byte of ACC+B2 into w move to Y(B1) ; 00AE 0002 return ; Output Y(n) computed ; ;******************************************************************* ; Set SIGNED/UNSIGNED Flag Before Including 17c42MPY.mac ; include “17c42MPY.mac” ;******************************************************************* ; Low Pass Filter Co-efficients ; ; © 1993 Microchip Technology Inc. DS00540B-page 13 4-141 4 Implementing IIR Digital Filters ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 01C1 01C2 01C3 01C4 01C5 1111 EA9B 2489 3B41 2489 01C6 01C7 01C8 01C9 01CA ED14 9DF7 5961 3FFD 5961 01CB 01CC 01CD 01CE 01CF DC8F E6F5 2079 CB57 2079 ELLIPTIC LOWPASS FILTER FILTER ORDER = 4 Sampling frequency = 2.000 BAND BAND LOWER BAND EDGE UPPER BAND EDGE NOMINAL GAIN NOMINAL RIPPLE MAXIMUM RIPPLE RIPPLE IN dB 1 .00000 .50000 1.00000 .01000 .00906 .07830 KiloHertz 2 .60000 1.00000 .00000 .05000 .04601 -26.74235 I A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) 1 2 -.133331 .147827 .167145 .765900 .285431 .698273 .462921 .499908 .285431 .698273 _coeff_lpass ; co-efficients for 1st Cascade data 4369 ; -A11 data -5477 ; -A12 data 9353 ; B10 data 15169 ; B11 data 9353 ; B12 ; ; co-efficients for 2nd Cascade data -4844 ; -A21 data -25097 ; -A22 data 22881 ; B20 data 16381 ; B21 data 22881 ; B22 ; ;******************************************************************* ; ; ;******************************************************************* ; High Pass Filter Co-efficients ; ; ; ELLIPTIC HIGHPASS FILTER ; ; FILTER ORDER = 4 ; Sampling frequency = 2.000 KiloHertz ; ; BAND 1 BAND 2 ; ; ; LOWER BAND EDGE .00000 .50000 ; UPPER BAND EDGE .40000 1.00000 ; NOMINAL GAIN .00000 1.00000 ; NOMINAL RIPPLE .04000 .02000 ; MAXIMUM RIPPLE .03368 .01686 ; RIPPLE IN dB -29.45335 .14526 ; ; I A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) ; ; 1 .276886 .195648 .253677 -.411407 .253677 ; 2 -.094299 .780396 .678650 -.485840 .678650 ; ; _coeff_hpass ; co-efficients for 1st Cascade section data -9073 ; -A11 data -6411 ; -A12 data 8313 ; B10 data -13481 ; B11 data 8313 ; B12 ; ; co-efficients for 2nd Cascade section DS00540B-page 14 © 1993 Microchip Technology Inc. 4-142 Implementing IIR Digital Filters 01D0 01D1 01D2 01D3 01D4 0C12 9C1C 56DE C1D0 56DE data data data data data 3090 -25572 22238 -15920 22238 ; ; ; ; ; -A21 -A22 B20 B21 B22 ; ;******************************************************************* ; ;******************************************************************* ; Band Pass Filter Co-efficients ; ; ; ELLIPTIC BANDPASS FILTER ; ; FILTER ORDER = 4 ; Sampling frequency = 2.000 KiloHertz ; ; BAND 1 BAND 2 BAND 3 ; ; ; LOWER BAND EDGE .00000 .30000 .90000 ; UPPER BAND EDGE .10000 .70000 1.00000 ; NOMINAL GAIN .00000 1.00000 .00000 ; NOMINAL RIPPLE .05000 .05000 .05000 ; MAXIMUM RIPPLE .03644 .03867 .03641 ; RIPPLE IN dB -28.76779 .32956 -28.77647 ; ; ; I A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) ; ; 1 -.936676 .550568 .444000 -.865173 .444000 ; 2 .936707 .550568 .615540 1.199402 .615540 ; 01D5 01D6 01D7 01D8 01D9 3BF2 DCC4 1C6A C8A1 1C6A 01DA 01DB 01DC 01DD 01DE C40D DCC4 2765 4CC3 2765 _coeff_bpass ; co-efficients for 1st Cascade section data 30693/2 ; -A11 data -18041/2 ; -A12 data 14549/2 ; B10 data -28350/2 ; B11 data 14549/2 ; B12 ; ; co-efficients for 2nd Cascade section data -30694/2 ; -A21 data -18041/2 ; -A22 data 20170/2 ; B20 data 39302/2 ; B21 data 20170/2 ; B22 ; ;******************************************************************* ; ;******************************************************************* ; Band Stop Filter Co-efficients ; ; ; ELLIPTIC BANDSTOP FILTER ; ; FILTER ORDER = 4 ; Sampling frequency = 2.000 KiloHertz ; ; BAND 1 BAND 2 BAND 3 ; ; ;LOWER BAND EDGE .00000 .45000 .70000 ;UPPER BAND EDGE .30000 .55000 1.00000 ;NOMINAL GAIN 1.00000 .00000 1.00000 ;NOMINAL RIPPLE .05000 .05000 .05000 ;MAXIMUM RIPPLE .03516 .03241 .03517 ;RIPPLE IN dB .30015 -29.78523 .30027 ; ; © 1993 Microchip Technology Inc. DS00540B-page 15 4-143 4 Implementing IIR Digital Filters 01DF 01E0 01E1 01E2 01E3 D00A DAAC 1922 05A0 1922 01E4 01E5 01E6 01E7 01E8 2FF6 DAAC 4D71 EEA9 4D71 ; I A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) ; ; 1 .749420 .583282 .392685 .087936 .392685 ; 2 -.749390 .583282 1.210022 -.270935 1.210022 ; _coeff_bstop ; co-efficients for 1st Cascade section data -24557/2 ; -A11 data -19113/2 ; -A12 data 12868/2 ; B10 data 2881/2 ; B11 data 12868/2 ; B12 ; co-efficients for 2nd Cascade section data 24556/2 ; -A21 data -19113/2 ; -A22 data 39650/2 ; B20 data -8878/2 ; B21 data 39650/2 ; B22 ; ;******************************************************************* END Errors : Warnings : 0 0 DS00540B-page 16 © 1993 Microchip Technology Inc. 4-144 WORLDWIDE SALES & SERVICE AMERICAS AMERICAS (continued) EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.mchip.com/microhip Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 214 991-7177 Fax: 214 991-8588 Dayton Microchip Technology Inc. 35 Rockridge Road Englewood, OH 45322 Tel: 513 832-2543 Fax: 513 832-2841 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 455 Irvine, CA 92715 Tel: 714 263-1888 Fax: 714 263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 United Kingdom Arizona Microchip Technology Ltd. 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