MDT10P23(CF ) 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 2K words EPROM and80 bytes static RAM. Four comparator inputs with external Vref (not for 18 pin package) are also provided. 2. Features Fully CMOS static design 8-bit data bus On chip EPROM size : 2 K words Internal RAM size : 80 bytes (72 general purpose registers, 8 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 6.0 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes Power-on Reset (POR),only available while PED is Disable 4 Channel comparator Power edge-detector Reset Sleep Mode for power saving 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler 4 types of oscillator can be selected by programming option: RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator XTAL－Standard crystal oscillator HFXT－High frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 μs, 20 ms, 40 ms, 80 ms On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O(for 18 pins package),14 I/O(for 20 pins package),16 I/O(for 22/24 pins package) pins with their own independent direction control 3. Applications The application areas of this MDT10P23 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2007/8 Ver. 1.6 MDT10P23(CF ) 4. Pin Assignment ※ A1：20PINS, A2：22PINS, A3：24PINS, A5 :18 PINS ※ P－PDIP,S－SOP, K－SKINNY A1P,A1S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 A3S PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC 1 PA7 2 PA5 3 PA2/CIC2 4 PA3/CIC3 5 RTCC 6 /MCLR 7 Vss 8 PB0 9 PB1 10 PB2 11 PB3 12 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A2K A5P,A5S PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 1 2 3 4 5 6 7 8 PB1 9 PB2 10 PB3 11 22 21 20 19 18 17 16 15 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 14 PB6 13 PB5 12 PB4 PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 18 17 16 15 14 13 12 PB2 8 PB3 9 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 11 PB5 10 PB4 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2007/8 Ver. 1.6 MDT10P23(CF ) 5. Block Diagram S ta ck Two Le ve ls P ort P B0~P B7 8 bits RAM 72X8 EP RO M 1KX14 (MDT10P 23) P ort B 10 bits 14 bits 10 bits P rogra m Counte rs O S C2 OS C1 Ins truction Re gis te r S pe cia l Re gis te r D0~D 7 MCLR Os cilla tor Circuit Ins truction De code r P ort P A0~P A7 (22,24 pins P A0~P A5 (20 pins ) P A0~P A3 (18 pins ) P ort A 8 bits Control Circuit CMR0~CMR5 Da ta 8-bit P owe r on Re s e t P owe r Down Re s e t Working Re gis te r S ta tus Re gis te r ALU 8-bit Tim e r/Counte r Com pa ra t or m ode Re gis te r WDT/OS T Tim e r P re s ca le RTCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2007/8 Ver. 1.6 MDT10P23(CF ) 6. Pin Function Description Pin Name I/O Function Description PA0~PA7 I/O PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground NC Unused ,do not connect 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07 Control register for comparator 08~0F Internal RAM, General Purpose Register 10~1F Internal RAM, Memory bank 0 30~3F Internal RAM, Memory bank 1 50~5F Internal RAM, Memory bank 2 70~7F Internal RAM, memory bank 3 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2007/8 Ver. 1.6 MDT10P23(CF ) (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit 5 page ROM Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 7 —— General purpose bit This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2007/8 Ver. 1.6 MDT10P23(CF ) (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only “1” Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) Bit 0 : R7 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 1 0: Define PA1 as TTL input 1: Define PA1 as comparator input 2 0: Define PA2 as TTL input 1: Define PA2 as comparator input 3 0: Define PA3 as TTL input 1: Define PA3 as comparator input 5:4 Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to inpu 7:6 Register bits This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2007/8 Ver. 1.6 MDT10P23(CF ) 9) TMR (Time Mode Register) Bit Symbol Function Prescaler Value 2—0 PS2—0 3 PSC 4 TCE 5 TCS RTCC rate WDT rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1 : 16 1:8 1 0 0 1 : 32 1 : 16 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin (10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (11) EPROM Option by writer programming : A. FIRST WORD Oscillator Type Oscillator Start-up Time Oscillator 150 μs LFXT Oscillator 20 ms XTAL Oscillator 40 ms HFXT Oscillator 80 ms RC Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2007/8 Ver. 1.6 MDT10P23(CF ) Power Edge Detect Security bit PED Disable Security Disable PED Enable Security Enable (B) Program Memory Address Description 000- 3FF Program memory The starting address of the power on, external reset or WDT 3FF 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR Reset WDT Reset CPIO A －－ 1111 1111 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 1111 1111 TMR －－ --11 1111 --11 1111 --11 1111 IAR 00h － － － RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PC 02h 1111 1111 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu 000# #uuu MSR 04h 100x xxxx 100u uuuu 1uuu uuuu PORT A 05h xxxx xxxx uuuuuuuu uuuu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu CMR 07h 0000 0000 uuuu uuuu uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) U u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2007/8 Ver. 1.6 MDT10P23(CF ) 9. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr NOP No operation None CLRWT Clear Watchdog timer 0→WT SLEEP Sleep mode 0→WT, stop OSC TF, PF TMODE Load W to TMODE register W→TMODE None RET Return Stack→PC None Control I/O port register W→CPIO 010001 1rrrrrrr STWR Store W to register W→R 011000 trrrrrrr LDR Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3)↔R(4~7)] →t None 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr R + 1→t None 011011 trrrrrrr INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→t) C, HC, Z 011101 trrrrrrr DECR R ﹣1→t Z 011110 trrrrrrr R ﹣1→t None 010010 trrrrrrr DECRSZ R, Decrement register, skip if t zero ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr R ♁ W→t Z i ♁ W→W Z 011111 trrrrrrr XORWR R, Exclu. OR W and register t XORWI i Exclu. OR W and immediate COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R(n) →R(n-1), C →R(7), R(0)→C C Operating Status 110110 iiiiiiii Instruction Code CPIO R R R, t R, t Decrement register AND W and immediate R, t Rotate right register Mnemonic Operands Function TF, PF None r None This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2007/8 Ver. 1.6 MDT10P23(CF ) 010101 trrrrrrr RLR R, t Rotate left register 010000 1xxxxxxx CLRW Clear working register R Clear register R(n)→r(n+1), C→R(0), R(7)→C C 0→W Z 0→R Z 010001 0rrrrrrr CLRR 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 100nnn nnnnnnnn LCALL n Long CALL subroutine None 101nnn nnnnnnnn 110000 nnnnnnnn LJUMP n Long JUMP to address n→PC, PC+1→ Stack n→PC CALL n Call subroutine 110001 iiiiiiii RTWI i 11001n nnnnnnnn JUMP n Return, place immediate to W JUMP to address None n→PC, PC+1→ Stack Stack→PC,i→W None n→PC None None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : 0 1 R : C : HC : Z : / : x : i : n : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 10. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Vdd Operating voltage VIL Input Low Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V Min Typ Max Unit 2.3 6.0 V -0.6 -0.6 1.0 1.0 V V This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2007/8 Ver. 1.6 MDT10P23(CF ) Sym Description Condition VIH Input high Voltage PA, PB RTCC, /MCLR Vdd=5V Vdd=5V IIL Vdd=5V Input leakage current VOL Output Low Voltage PA, PB VOH Output High Voltage PA, PB Islp Sleep current (WDT disable) Islp Sleep current (WDT enable) Min Typ 2.0 3.3 Max Unit Vdd Vdd V V +/-1 µA Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA 0.5 0.1 V V Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd＝2.3 ~ 6.0 V 3.8 4.5 V V Vdd＝2.3 V Vdd＝3.0 V Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 1 3 6 11 17 Vpr Power Edge-detector Reset Voltage 0.1 1.0 μA μA μA μA μA μA 1.1 1.3 V Twdt The basic WDT time-out cycle Vdd＝2.3 V Vdd＝3.0 V time Vdd＝4.0 V Vdd＝5.0 V Vdd＝6.0 V 25.2 22.4 20.4 18.8 18.0 mS mS mS mS mS TFLT /MCLR filter Vdd＝5.0 V 600 nS Icc Comparator Supply current (one comparator) Vdd=5.0v 15 μA Vref Input reference voltage Vdd=2.5v ~6.0v --- Comparator Response time V-=Vdd/4, V+=V- ± 0.2v V-=Vdd/2, V+=V- ± 0.2v V-=Vdd3/4, V+=V- ± 0.2v V-=VDD-0.8,V+=V± 0.2v Vdd=5.0v , V- = Vref V+ = (PA0~PA3) Vdd-0.8 v 8 8 8 8 V μS μS μS μS This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2007/8 Ver. 1.6 MDT10P23(CF ) 11. Operating Current Temperature＝25 ℃, the typical value as followings : 11.1 OSC Type＝RC; WDT=Enable; @Vdd＝5.0 V PED=Disable Cext. (F) 3P 20P 100P 300P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 11.24 M 1.3 mA 10.0 K 5.95 M 660 µA 47.0 K 1.40M 245 μA 100.0 K 658 K 175 μA 300.0 K 225 K 145 μA 470.0 K 142 K 125μA 4.7 K 5.45 M 625 µA 10.0 K 2.74 M 380 μA 47.0 K 623 K 175 μA 100.0 K 293 K 145 μA 300.0 K 100 K 130 μA 470.0 K 65 K 125 μA 4.7 K 1.76 M 300 μA 10.0 K 886 K 215 μA 47.0 K 196 K 150 μA 100.0 K 92 K 137 μA 300.0 K 31 K 132 μA 470.0 K 20 K 125 μA 4.7 K 686 K 195 μA 10.0 K 336 K 160 μA 47.0 K 75 K 135 μA 100.0 K 35 K 130 μA 300.0 K 12 K 126 μA 470.0 K 7K 125 μA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2007/8 Ver. 1.6 MDT10P23(CF ) 11.2 OSC Type＝LF (OSC1&OSC2 External Cap about 10P); WDT－Disable ﹔ PED=Disable Voltage/Frequency 32 K (EXT=100p) 455 K (Ext50p) 1M Sleep 40μA ＜1.0 μA 60μA 72μA ＜1.0 μA 35.0μA 90μA 125μA ＜1.0 μA 5.0 V 73.0μA 150μA 190μA ＜1.0 μA 6.0 V 133μA 220μA 265μA ＜1.0 μA 2.3 V 7.0μA 3.0 V 15.0μA 4.0 V [email protected] μA 11.3 OSC Type＝XT (OSC1&OSC2 External Cap about 10P); Voltage/Frequency WDT－Enable ;PED=Disable 1M 4M 10 M Sleep 2.1 V 50μA 120μA 290μA ＜1.0 μA 3.0 V 110μA 240μA 500μA 3 μA 4.0 V 220μA 410μA 650μA 6 μA 5.0 V 380μA 600μA 1.3mA 11 μA 6.0 V 650μA 860μA 1.7mA 17 μA 11.4 OSC Type＝HF (OSC1&OSC2 External Cap about 10P); WDT－Enable ﹔ PED=Disable Voltage/Frequency 4M 10 M 20 M Sleep 2.1 V 150μA 320μA X 3.0 V 295μA 555μA 935μA 3 μA 4.0 V 515μA 915μA 1.5mA 6 μA 5.0 V 810μA 1.5mA 2.4mA 11 μA 6.0 V 1.4mA 2.0mA 3.3mA 17 μA ＜1.0 μA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2007/8 Ver. 1.6 MDT10P23(CF ) 11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd＝5.0 V (PED: Enable) Vpr≦1.6~1.8 V Vpr ﹕Vdd (Power Supply) PS. If PED_Enable then Internal Power_on_reset will be off 12. Port A Equivalent Circuit PA0-PA3 Q D I/O Control C K I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G QB Input Resistor Data Bus 0 TTL input level QB Rea d D Data I/P Latch G S + 1 VREF comparator level Compartor Control This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2007/8 Ver. 1.6 MDT10P23(CF ) PA4 Q D I/O Control I/O Control Latch C K Q B Port I/O Pin D Data O/P Latch Write Q B G Input Resistor Data Bus Data I/P Latch Rea d comparator enable D QB TTL Input Level G 3 3/4 VDD 1/2 VDD 1/4 VDD 2 Vref 1 S0 S1 0 CMR_4 CMR_5 PA5-PA7 Q D I/O Control C K I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Data Bus Q B D QB Rea d Data I/P Latch Input Resistor TTL Input Level G This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 2007/8 Ver. 1.6 MDT10P23(CF ) Port B Equivalent Circuit D I/O Control C K Q I/O Control Latch Q B Port I/O Pin D Data O/P Latch Write G Data Bus Q B D QB Rea d Data I/P Latch Input Resistor TTL Input Level G This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 2007/8 Ver. 1.6 MDT10P23(CF ) 13. MCLRB and RTCC Input Equivalent Circuit R≒1K MCLRB Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 17 2007/8 Ver. 1.6 MDT10P23(CF ) 14. External Capacitor Selection For Crystal Oscillator @ Vdd＝5.0 V Osc. Type Resonator Freq. Capacity Range 20 MHz 10 pF ~ 50 pF 10 MHz 20 pF ~ 50 pF 4 MHz 10 pF ~ 30 pF 10 MHz 10 pF ~ 50 pF 4 MHz 10 pF ~ 50 pF 1 MHz 20 pF ~50 pF 1 MHz 20 pF ~ 30 pF 455 K 20 pF ~30 pF 32 K 20 pF ~30 pF HF XT LF MDT10P23 OSC1 C1 OSC2 C2 To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 18 2007/8 Ver. 1.6