MDT10P10 MDT10P10 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speeds and smaller size with the low power and high noise immunity. On chip memory system includes 1.0 K words of ROM, and 32 bytes of static RAM. 2. Features The followings are some of the features on the hardware and software : u u u u Fully CMOS static design 8-bit data bus On chip ROM size :1 K words Internal RAM size : 32 bytes (25 general purpose registers, 7 special registers) u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 5.5 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instructions u Addressing modes include direct, indirect and relative addressing modes u Power-on Reset u Power edge-detector Reset u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option (Internal Capacitor about 10p ): RC－Low cost RC oscillator LFXT－Low frequency crystal oscillator XTAL－Standard crystal oscillator HFXT－High frequency crystal oscillator u 4 oscillator start-up time can be selected by programming option: 150 µs, 20 ms, 40 ms, 80 ms u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u 12 I/O pins with their own independent direction control 3. Applications The application areas of this MDT10P10 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 1 2004/1 VER 1.2 MDT10P10 4. Pin Assignment PA2 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 5. Pin Function Description Pin Name I/O Function Description PA0~PA3 I/O Port A, TTL input level PB0~PB7 I/O Port B, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC1 I Oscillator Input OSC2 O Oscillator Output Vdd Power supply Vss Ground 6. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07~1F Internal RAM, General Purpose Register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 2 2004/1 VER 1.2 MDT10P10 (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b5 (ROM 1K) LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit 5 page 0 Page select bit : 0 : 000H --- 1FFH 1 : 200H --- 3FFH 6—7 —— General purpose bit (5) MSR (Memory Select Register) : R4 (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 3 2004/1 VER 1.2 MDT10P10 (8) TMR (Time Mode Register) Bit Symbol Function Prescaler Value 2—0 PS2—0 3 PSC 4 TCE 5 TCS RTCC rate WDT rate 1:1 1:2 0 0 0 1:2 1:4 0 0 1 1:4 1:8 0 1 0 1:8 1 : 16 0 1 1 1 : 16 1 : 32 1 0 0 1 : 32 1 : 64 1 0 1 1 : 64 1 : 128 1 1 0 1 : 128 1 : 256 1 1 1 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin (9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (10) EPROM Option by writer programming : Oscillator Type Oscillator Start-up Time RC 150 µs,20ms,40ms,80ms Oscillator HFXT Oscillator 20 ms,40ms,80ms XTAL Oscillator 20ms,40 ms,80ms LFXT Oscillator 40 ms,80 ms Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 4 2004/1 VER 1.2 MDT10P10 Power Edge Detect Security bit PED Disable Security Disable PED Enable Security Enable The default EPROM security is disable. Once the IC was set to enable, it can not to set to enable again. (B) Program Memory Address 000-3FF 3FF Description Program memory for MDT10P10 The starting address of the power on, external reset or WDT time-out reset for MDT10P10 7. Reset Condition for all Registers Register Address Power-On Reset /MCLR or WDT Reset CPIO A －－ 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 TMR －－ - - 11 1111 - - 11 1111 IAR 00h xxxx xxxx uuuu uuuu RTCC 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu MSR 04h 111x xxxx 111u uuuu PORT A 05h - - - - xxxx - - - - uuuu PORT B 06h xxxx xxxx uuuu uuuu Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) u u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 5 2004/1 VER 1.2 MDT10P10 8. Instruction Set Instruction Code Mnemonic Operands Function Operating Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode TF, PF 010000 00000011 TMODE Load W to TMODE register 0→WT, stop OSC W→TMODE 010000 00000100 RET Return Stack→PC Control I/O port register W→CPIO R None None 010000 00000rrr CPIO 010001 1rrrrrrr STWR R Store W to register W→R 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔ R(4~7)]→t None 011001 trrrrrrr INCR R, t R + 1→t Z 011010 trrrrrrr R + 1→t None 011011 trrrrrrr INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrrrr R ﹣1→t None 010010 trrrrrrr DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z 110110 iiiiiiii XORWI i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR R, t Rotate right register R(n) →R(n-1), C→R(7), R(0)→C C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C→R(0), R(7)→C C 010000 1xxxxxxx CLRW Clear working register 0→W Z I i i Increment register Exclu. OR W and immediate r None None This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 6 2004/1 VER 1.2 MDT10P10 Mnemonic Operands Instruction Code R Function Operating Clear register Status 010001 0rrrrrrr CLRR 0→R 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine n→PC, PC+1→Stack None 1010nn nnnnnnnn LJUMP n Long JUMP to address n→PC None 110000 nnnnnnnn CALL n Call subroutine n→PC, PC+1→Stack None 110001 iiiiiiii RTIW i Return, place immediate to W Stack→PC, i→W None 11001n nnnnnnnn JUMP n JUMP to address n→PC None Bit set Z Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t : : R C HC Z / x i n : : : : : : : : Bit position Target 0: Working register 1 : General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 9. Electrical Characteristics (A) Operating Voltage & Frequency Vdd ﹕2.3V ~ 5.5 V Frequency﹕0 Hz ~ 20 MHz This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 7 2004/1 VER 1.2 MDT10P10 (B) Input Voltage @ Vdd＝5.0 V, Temperature＝25 ℃ Vil Port Min. Max. PA, PB Vss 1.0 V RTCC, /MCLR Vss 1.0V PA, PB 2.0 V Vdd Vih RTCC, /MCLR 3.2 V Vdd ＊Threshold Voltage : Port A, Port B Vth＝1.45V RTCC Vil＝1.2 V, Vih＝3.0 V (Schmitt Trigger) /MCLR Vil＝1.6 V, Vih＝3.0 V (Schmitt Trigger) (C) Output Voltage﹕ @ Vdd＝5.0 V, Temperature＝25 ℃, the typical value as followings : PA, PB Port Ioh＝－20.0 mA Voh＝3.3 V Iol＝20.0 mA Vol＝0.44 V Ioh＝－5.0 mA Voh＝4.2 V Iol＝5.0 mA Vol＝0.12 V (D) Leakage Current @ Vdd＝5.0 V, Temperature＝25 ℃, the typical value as followings : Iil － 0.1µA (Max.) Iih ＋ 0.1µA (Max.) (E) Sleep Current @WDT－Disable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V Idd＜1.0 µA Vdd＝3.0 V Idd＜1.0 µA Vdd＝4.0 V Idd＜1.0 µA Vdd＝5.0 V Idd＜1.0 µA Vdd＝5.5V Idd＜45µA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 8 2004/1 VER 1.2 MDT10P10 @WDT－Enable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V Idd＜1.5 µA Vdd＝3.0 V Idd＝3.3 µA Vdd＝4.0 V Idd＝8.0 µA Vdd＝5.0 V Idd＝16.0 µA Vdd＝6.3 V Idd＝29.0 µA (F) Operating Current Temperature＝25 ℃, the typical value as followings : (i) OSC Type＝RC ( Internal capacitor 10p ) ; WDT－Enable; @ Vdd＝5.0 V Cext. (F) 0P 3P 20P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 10.0 M 940 µA 10.0 K 5.6 M 540 µA 47.0 K 1.3 M 200 µA 100.0 K 630 K 150 µA 300.0 K 210 K 120 µA 470.0 K 130 K 115 µA 4.7 K 9.0 M 820 µA 10.0 K 4.8 M 470 µA 47.0 K 1.1 M 190 µA 100.0 K 530 K 150 µA 300.0 K 180 K 120 µA 470.0 K 110 K 115 µA 4.7 K 5.4 M 530 µA 10.0 K 2.7 M 320 µA 47.0 K 620 K 160 µA 100.0 K 290 K 135 µA 300.0 K 100 K 120 µA 470.0 K 63 K 115 µA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 9 2004/1 VER 1.2 MDT10P10 Cext. (F) 100P 300P (ii) Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 2.0 M 265 µA 10.0 K 1.0 M 180 µA 47.0 K 220 K 120 µA 100.0 K 105 K 110 µA 300.0 K 36 K 105 µA 470.0 K 22 K 104 µA 4.7 K 915 K 170 µA 10.0 K 450 K 135 µA 47.0 K 99 K 106 µA 100.0 K 46 K 102 µA 300.0 K 15 K 99 µA 470.0 K 9.5 K 98 µA OSC Type＝LF (Internal C=10 p); WDT－Disable Voltage/Frequency 32 K 455 K 1M Sleep 27 µA ＜1.0 µA 33 µA 44 µA ＜1.0 µA 44 µA 70 µA 80 µA ＜1.0 µA 5.0 V 84 µA 130 µA 121 µA ＜1.0 µA 5.5 V 110 µA 155 µA 140 µA ＜45 µA 6.3 V 125 µA 165 µA 200 µA ＜120 µA 10 M Sleep 2.3 V 3.3 µA 3.0 V 11 µA 4.0 V @2.4V 19 µA @2.4V (iii) OSC Type＝XT (Internal C=10 p); WDT－Enable Voltage/Frequency 1M 4M 2.3 V 35 µA 100 µA 220 µA 1.5 µA 3.0 V 65 µA 160 µA 370 µA 3.3 µA 4.0 V 130 µA 290 µA 590 µA 8.0 µA 5.0 V 220 µA 440 µA 860 µA 16 µA 6.3 V 400 µA 640 µA 1.2 mA 29 µA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 10 2004/1 VER 1.2 MDT10P10 (iv) OSC Type＝HF (Internal C=10 p); WDT－Enable Voltage/Frequency 4M 10 M 20 M Sleep X 1.5 µA 2.3 V 110 µA 265 µA 3.0 V 175 µA 400 µA 4.0 V 340 µA 630 µA 1.2 mA 8.0 µA 5.0 V 520 µA 950 µA 1.7 mA 16 µA 6.3 V 770 µA 1.3 mA 2.4 mA 29 µA 750 µA 3.3 µA (G) The basic WDT time-out cycle time @ Vdd=5.0v ,Temperature＝25 ℃, the typical value as followings : Voltage (V) Basic WDT time-out cycle time (ms) 2.3 28.0 3.0 24.0 4.0 21.0 5.0 19.0 6.3 17.0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 11 2004/1 VER 1.2 MDT10P10 (H) Reset & Watchdog Timer Timing /MCLR, WATCHDOG timer and internal POR timing Vdd /MCLR Internal POR Tost OST Time-out Internal Reset WDT reset Tmclr I/O pin Tost Twdt Tio Symbol Description Tio Min Typ Max Unit 15 20 24 ms 100 ns Tost Oscillator start up time Tio I/O floating from /MCLR low Tmclr /MCLR pulse width 500 Twdt Watchdog timer time-out period (No postscaler) 15 ns 20 24 ms (I) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd＝5.0 V Vpr≦1.8~2.0 V Vpr ﹕Vdd (Power Supply) This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 12 2004/1 VER 1.2 MDT10P10 (J) MCLRB Filter：@ Vdd=5.0v Wm ＞1.0us Wm : Filter pulse width (low) in /MCLR pin. 10. Port A and Port B Equivalent Circuit Working Register D Data I/P QB I/O Control Latch I/O Control CK Q Port I/O Pin D Data O/P Latch Write CK Q Data Bus D QB Read Data I/P Latch Input Resistor TTL Input Level CK This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 13 2004/1 VER 1.2 MDT10P10 11. MCLRB and RTCC Input Equivalent Circuit R ≒ 1 K MCLRB Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 14 2004/1 VER 1.2 MDT10P10 12. Block Diagram Stack Two Levels EPROM 1024× 14 (MDT10P10) RAM 25×8 Port PA0~PA3 4 bits Port A 9 or10 bits 14 bits 9 or 10 bits Program Counters Instruction Register Special Register D0~D7 OSC1 OSC2 MCLR Port B Oscillator Circuit Instruction Decoder Port PB0~PB7 8 bits Control Circuit Data 8-bit Power on Reset Power Down Reset Working Register Status Register ALU 8-bit Timer/Counter WDT/OST Timer Prescale RTCC This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 15 2004/1 VER 1.2 MDT10P10 13. Internal Capacitor Selection For Crystal Oscillator @ Vdd＝2.3 V~5.5 V , C1=C2=10P To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range can be recommended for reference, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw P. 16 2004/1 VER 1.2