28C64A 64K (8K x 8) CMOS EEPROM 30 NC 32 Vcc 31 WE 2 RDY/BSY 1 NU 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 20 19 18 17 16 15 21 I/O6 14 Vcc WE NC A8 A6 5 A9 A5 6 A11 A4 7 A3 8 OE A10 A2 9 A1 10 CE A0 11 I/O7 NC 12 I/O6 I/O0 13 I/O5 I/O4 I/O3 PLCC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 • Pin 1 indicator on PLCC on top of package OE A11 A9 A8 NC WE Vcc 1 2 3 4 5 6 7 RDY/BSY A12 A7 A6 A5 A4 A3 8 9 10 11 12 13 14 OE A11 A9 A8 NC WE VCC RDY/BSY A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 28 27 26 25 24 23 22 A10 CE I/07 I/06 I/05 I/04 I/03 21 20 19 18 17 16 15 Vss I/02 I/01 I/00 A0 A1 A2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 VSOP The Microchip Technology Inc. 28C64A is a CMOS 64K nonvolatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a “byte write”, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications •1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP DESCRIPTION RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS DIP/SOIC • Fast Read Access Time—150 ns • CMOS Technology for Low Power Dissipation - 30 mA Active - 100 µA Standby • Fast Byte Write Time—200 µs or 1 ms • Data Retention >200 years • High Endurance - Minimum 100,000 Erase/Write Cycles • Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches • Data Polling • Ready/Busy • Chip Clear Operation • Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit • Electronic Signature for Device Identification • 5-Volt-Only Operation • Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin Thin Small Outline Package (TSOP) 8x20mm - 28-pin Very Small Outline Package (VSOP) 8x13.4mm • Available for Extended Temperature Ranges: - Commercial: 0˚C to +70˚C 4 A7 3 A12 PACKAGE TYPES I/O1 I/O2 Vss NU I/O3 I/O4 I/O5 FEATURES A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 BLOCK DIAGRAM I/O0 VSS VCC Data Protection Circuitry Chip Enable/ Output Enable Control Logic CE OE WE Rdy/ Busy I/O7 Auto Erase/Write Timing Data Poll Input/Output Buffers Program Voltage Generation A0 L a t c h e s Y Decoder Y Gating X Decoder 16K bit Cell Matrix A12 1996 Microchip Technology Inc. DS11109H-page 1 This document was created with FrameMaker 4 0 4 28C64A 1.0 ELECTRICAL CHARACTERISTICS 1.1 MAXIMUM RATINGS* TABLE 1-1: PIN FUNCTION TABLE Name Function VCC and input voltages w.r.t. VSS ....... -0.6V to + 6.25V A0 - A12 Voltage on OE w.r.t. VSS ..................... -0.6V to +13.5V CE Chip Enable OE Output Enable WE Write Enable Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V Output Voltage w.r.t. VSS ................ -0.6V to VCC+0.6V Storage temperature .......................... -65˚C to +125˚C Ambient temp. with power applied ....... -50˚C to +95˚C *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: Address Inputs I/O0 - I/O7 Data Inputs/Outputs RDY/Busy Ready/Busy VCC +5V Power Supply VSS Ground NC No Connect; No Internal Connection NU Not Used; No External Connection is Allowed READ/WRITE OPERATION DC CHARACTERISTIC VCC = +5V ±10% Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Status Symbol Min Max Units Input Voltages Logic ‘1’ Logic ‘0’ VIH VIL 2.0 -0.1 Vcc+1 0.8 V V Input Leakage — ILI -10 10 µA VIN = -0.1V to Vcc +1 Input Capacitance — CIN — 10 pF VIN = 0V; Tamb = 25˚C; f = 1 MHz (Note 2) Logic ‘1’ Logic ‘0’ VOH VOL 2.4 0.45 V V IOH = -400 µA IOL = 2.1 mA Output Leakage — ILO -10 10 µA VOUT = -0.1V to Vcc +0.1V Output Capacitance — COUT — 12 pF VIN = 0V; Tamb = 25˚C; f = 1 MHz (Note 2) TTL input ICC — 30 mA f = 5 MHz (Note 1) VCC = 5.5V — 2 3 100 mA mA µA CE = VIH (0˚C to +70˚C) CE = VIH (-40˚C to +85˚C) CE = VCC-0.3 to Vcc +1 Output Voltages Power Supply Current, Active Power Supply Current, Standby ICC(S)TTL TTL input TTL input ICC(S)TTL CMOS input ICC(S)CMOS Conditions Note 1: AC power supply current above 5MHz: 2mA/MHz. 2: Not 100% tested. DS11109H-page 2 1996 Microchip Technology Inc. 28C64A TABLE 1-3: READ OPERATION AC CHARACTERISTICS AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C 28C64A-15 Parameter 28C64A-20 28C64A-25 Symbol Min Max Min Max Min Max Units Conditions Address to Output Delay tACC — 150 — 200 — 250 ns OE = CE = VIL CE to Output Delay tCE — 150 — 200 — 250 ns OE = VIL OE to Output Delay tOE — 70 — 80 — 100 ns CE = VIL CE or OE High to Output Float tOFF 0 50 0 55 0 70 ns (Note 1) Output Hold from Address, CE or OE, whichever occurs first. tOH 0 — 0 — 0 — ns (Note 1) Endurance — 1M — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block Mode (Note 2) Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. FIGURE 1-1: READ WAVEFORMS VIH Address Address Valid VIL VIH CE VIL t CE(2) VIH OE VIL VOH Data t OE(2) High Z t OFF(1,3) t OH Valid Output High Z VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested 1996 Microchip Technology Inc. DS11109H-page 3 28C64A TABLE 1-4: BYTE WRITE AC CHARACTERISTICS AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Symbol Min Max Units Remarks Address Set-Up Time tAS 10 — ns Address Hold Time tAH 50 — ns Data Set-Up Time tDS 50 — ns Data Hold Time tDH 10 — ns Write Pulse Width tWPL 100 — ns Write Pulse High Time tWPH 50 — ns OE Hold Time tOEH 10 — ns OE Set-Up Time tOES 10 — ns Data Valid Time tDV — 1000 ns Time to Device Busy tDB 2 50 ns Write Cycle Time (28C64A) tWC — 1 ms 0.5 ms typical Write Cycle Time (28C64AF) tWC — 200 µs 100 µs typical Note 1 Note 2 Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first. FIGURE 1-2: PROGRAMMING WAVEFORMS VIH Address VIL VIH t AS t AH t WPL CE, WE VIL t DV Data In t DS t DH VIH VIL t OES VIH OE VIL t OEH VOH Rdy/Busy Busy VOL DS11109H-page 4 t WC Ready t DB 1996 Microchip Technology Inc. 28C64A FIGURE 1-3: DATA POLLING WAVEFORMS VIH Last Written Address Valid Address Valid Address VIL t ACC VIH CE t CE VIL t WPH VIH t WPL WE VIL t OE VIH OE VIL t DV VIH Data In Valid Data VIL I/O7 Out True Data Out t WC FIGURE 1-4: CHIP CLEAR WAVEFORMS VIH CE VIL VH OE VIH tS tH tW VIH WE tW = 10ms tS = tH = 1µs VH = 12.0V ±0.5V VIL TABLE 1-5: SUPPLEMENTARY CONTROL CE OE WE A9 VCC Chip Clear VIL VIH VIL X VCC Extra Row Read VIL VIL VIH A9 = VH VCC Data Out Extra Row Write * VIH * A9 = VH VCC Data In Mode Note: VH = 12.0V±0.5V. 1996 Microchip Technology Inc. I/OI *Pulsed per programming waveforms. DS11109H-page 5 28C64A 2.0 DEVICE OPERATION 2.4 The Microchip Technology Inc. 28C64A has four basic modes of operation—read, standby, write inhibit, and byte write—as outlined in the following table. CE OE WE I/O Rdy/Busy (1) Read L L H DOUT H Standby H X X High Z H Write Inhibit H X X High Z H Write Inhibit X L X High Z H Write Inhibit X X H High Z H Byte Write L H L DIN L Operation Mode Byte Clear Automatic Before Each “Write” Note 1: Open drain output. 2: X = Any TTL level. 2.1 Read Mode The 28C64A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the output tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE. 2.2 Standby Mode Write Mode The 28C64A has a write cycle similar to that of a Static RAM. The write cycle is completely self-timed and initiated by a low going pulse on the WE pin. On the falling edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched. The Ready/Busy pin goes to a logic low level indicating that the 28C64A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. When Ready/Busy goes back to a high, the 28C64A has completed writing and is ready to accept another cycle. 2.5 Data Polling The 28C64A features Data polling to signal the completion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 are indeterminable). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. 2.6 Electronic Signature for Device Identification An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9 to 12V ±0.5V and using address locations 1FEO to 1FFF, the additional bytes can be written to or read from in the same manner as the regular memory array. 2.7 Chip Clear All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data, except for the extra row. The 28C64A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input. 2.3 Data Protection In order to ensure data integrity, especially during critical power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal VCC detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when VCC is less than the VCC detect circuit trip. Second, there is a WE filtering circuit that prevents WE pulses of less than 10 ns duration from initiating a write cycle. Third, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC). DS11109H-page 6 1996 Microchip Technology Inc. 28C64A 28C64A Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 28C64A F T – 15 I /P Package: Temperature Range: Access Time: = = = = = Plastic Leaded Chip Carrier (PLCC) Plastic DIP (600 mil) Plastic Small Outline IC (600 mil) Thin Small Outline Package (TSOP) 8x20mm Very Small Outline Package (VSOP) 8x13.4mm Blank = 0°C to +70°C I = -40°C to +85°C 15 20 25 150 ns 200 ns 250 ns Shipping: Blank T Option: Blank = twc = 1ms F = twc = 200 µs Device: 1996 Microchip Technology Inc. L P SO TS VS 28C64A Tube Tape and Reel “L” and “SO” 8K x 8 CMOS EEPROM DS11109H-page 7 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972 991-7177 Fax: 972 991-8588 Dayton Microchip Technology Inc. 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Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 1628 850303 Fax: 44 1628 850178 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleone Pas Taurus 1 Viale Colleoni 1 20041 Agrate Brianza Milan Italy Tel: 39 39 6899939 Fax: 39 39 689 9883 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 9/3/96 All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS11109H-page 8 1996 Microchip Technology Inc.