ML12061 Crystal Oscillator Legacy Device: Motorola MC12061 The ML12061 is for use with an external crystal to form a crystal controlled oscillator. In addition to the fundamental series mode crystal, two bypass capacitors are required (plus usual power supply pin bypass capacitors). Translators are provided internally for MECL and TTL outputs. • • • • Frequency Range = 2.0 to 20 MHz Operating Temperature Range = 0 to + 70°C Single Supply Operation: +5.0 Vdc or –5.2 V DC Three Outputs Available: 1.Complementary Sine Wave (600 mVpp typ) 2.Complementary MECL 3.Single Ended TTL 16 1 P DIP 16 = EP PLASTIC PACKAGE CASE 648 Figure 1. Block Diagram VCC Bias Bypass 0.1 µF AGC Filter 0.1 µF Sine Wave Output – 7 1 VCC Voltage Reg. 4 3 + 2 – 14 16 VCC Sine to MECL AGC 6 5 P DIP 16 + 15 Ampl./ AGC Crystal Osc. CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE MECL Output 8 VEE 13 12 11 VCC MECL to TTL Translator 9 10 MC112061P ML12061EP Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. TTL Output VEE Crystal Note: 0.1 µF power supply pin bypass capacitors not shown. Page 1 of 9 www.lansdale.com Issue A ML12061 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS Test Limits Symbol Pin Under Test Min Max Min Typ Max Min Max Unit ICC 1 – – 13 16 19 – – mAdc 1 11 16 – – – – – – 18 – 13 23 3.0 16 28 4.0 19 – – – – – – IinH 14 15 – – – – – – – – 250 250 – – – – µAdc IinL 14 15 – – – – – – – – 1.0 1.0 – – – – µAdc ∆V 4 to 7 2 to 3 – – – – 40 –200 – 0 325 +200 – – – – mAdc Vout 2 3 – – – – – – 3.5 3.5 – – – – – – Vdc VOH1 (Note 1) 12 13 4.0 4.0 4.16 4.16 4.04 4.04 – – 4.19 4.19 4.1 4.1 4.28 4.28 Vdc VOH2 10 2.4 – 2.4 – – 2.4 – VOL1 (Note 1) 12 13 2.98 2.98 3.43 3.43 3.0 3.0 – – 3.44 3.44 3.02 3.02 3.47 3.47 VOL2 10 10 – – 0.5 0.5 – – – – 0.5 0.5 – – 0.5 0.5 Logic ‘1’ Threshold Voltage VOHA 12 13 3.98 3.98 – – 4.02 4.02 – – – – 4.08 4.08 – – Vdc Logic ‘0’ Threshold Voltage VOLA 12 13 – – 3.45 3.45 – – – – 3.46 3.46 – – 3.49 3.49 Vdc Output Short Circuit Current IOS 10 20 60 20 – 60 20 60 mAdc Characteristic Power Supply Drain Current Input Current Differential Offset Voltage Output Voltage Level Logic ‘1’ Output Voltage Logic ‘0’ Output Voltage NOTE: Page 2 of 9 0°C +25°C +75°C Vdc 1. Devices will meet standard MECL logic levels using VEE = –5.2 Vdc and VCC = 0. www.lansdale.com Issue A ML12061 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature VIHmax VILmin VIHAmin VILAmax VIHT VCCL 0°C 4.16 3.19 3.86 3.51 4.0 4.75 +25°C 4.19 3.21 3.90 3.52 4.0 4.75 +75°C 4.28 3.23 3.96 3.55 4.0 4.75 Symbol Pin Under Test VIHmax VILmin VIHAmin VILAmax VIHT VCCL Gnd ICC 1 – – – – – – 8 1 11 16 – 14 – – 15 – – – – – – – – – – – – – 8 8,9 8 IinH 14 15 14 15 15 14 – – – – – – – – 8 8 IinL 14 15 15 14 – – – – – – – – – – 8,14 8,15 ∆V 4 to 7 2 to 3 – – – – – – – – 5,6 4 – – 8 – Vout 2 3 – – – – – – – – 4 4 – – 8 8 VOH1 (Note 1) 12 13 14 15 15 14 – – – – – – – – 8 8 VOH2 10 15 14 – – – 11,16 8,9 VOL1 (Note 1) 12 13 15 14 14 15 – – – – – – – – 8 8 VOL2 10 10 14 14 15 15 – – – – – – 11,16 – 8,9 8,9 Logic ‘1’ Threshold Voltage VOHA 12 13 – – – – 14 15 15 14 – – – – 8 8 Logic ‘0’ Threshold Voltage VOLA 12 13 – – – – 15 14 14 15 – – – – 8 8 Output Short Circuit Current IOS 10 15 14 – – – 11,16 8,9,10 Characteristic Power Supply Drain Current Input Current Differential Offset Voltage Output Voltage Level Logic ‘1’ Output Voltage Logic ‘0’ Output Voltage NOTE: Page 3 of 9 TEST VOLTAGE APPLIED TO PINS LISTED BELOW 1. Devices will meet standard MECL logic levels using VEE = –5.2 Vdc and VCC = 0. www.lansdale.com Issue A ML12061 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature mA VCC VCCH IOL IOH IIL 0°C 5.0 5.25 16 –0.4 –2.5 +25°C 5.0 5.25 16 –0.4 –2.5 +75°C 5.0 5.25 16 –0.4 –2.5 Symbol Pin Under Test VCC VCCH IOL IOH IIL Gnd ICC 1 1 – – – – 8 1 11 16 1 11,16 16 – – – – – – – – – – – – 8 8,9 8 IinH 14 15 16 16 – – – – – – – – 8 8 IinL 14 15 16 16 – – – – – – – – 8,14 8,15 ∆V 4 to 7 2 to 3 1 – – – – – – – – – 8 – Vout 2 3 1 1 – – – – – – – – 8 8 VOH1 (Note 1) 12 13 16 16 – – – – – – 12 13 8 8 VOH2 10 – – – 10 – 8,9 VOL1 (Note 1) 12 13 16 16 – – – – – – 12 13 8 8 VOL2 10 10 – – – 11,16 10 10 – – – – 8,9 8,9 Logic ‘1’ Threshold Voltage VOHA 12 13 16 16 – – – – – – 12 13 8 8 Logic ‘0’ Threshold Voltage VOLA 12 13 16 16 – – – – – – 12 13 8 8 Output Short Circuit Current IOS 10 – – – – – 8,9,10 Characteristic Power Supply Drain Current Input Current Differential Offset Voltage Output Voltage Level Logic ‘1’ Output Voltage Logic ‘0’ Output Voltage NOTE: Page 4 of 9 TEST VOLTAGE APPLIED TO PINS LISTED BELOW 1. Devices will meet standard MECL logic levels using VEE = –5.2 Vdc and VCC = 0. www.lansdale.com Issue A ML12061 LANSDALE Semiconductor, Inc. Figure 6. AC Characteristics – MECL and TTL Outputs Input (Pin 15) 20% +200 mV t– t+ 80% 50% VCC = + 2.0 Vdc 0.1 µF –200 mV t– – t+ + 16 15 11 13 450 12 450 10 1.2 k 50% TTL Output (Pin 10) MECL Output (Pin 13) MECL Output (Pin 12) 80% 50% 20% t+– 80% Pulse Generator (EH 137 or Equiv) PRF = 2.0 MHz t + = t – = 2.0 ± 0.2 ns t– – t++ 14 t– t+ t– + 8 50% 20% t– 0.1 µF t+ All input and output cables to the scope are equal lengths of 50 Ω coaxial cable. Unused outputs are connected to a 50 Ω ± 1% resistor to ground. 400 9 MMD6150 or Equiv CT C T = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance. + 2.0 Vdc MMD7000 or Equiv VEE = – 3.0 Vdc – 3.0 Vdc TEST VOLTAGES/WAVEFORMS APPLIED TO PINS LISTED BELOW: Test Limits Pin 0°C + 25°C + 75°C Under Test Min Max Min Typ Max Min Max Unit Pulse In Pulse Out + 2.0 Vdc – 3.0 Vdc Gnd Characteristic Symbol Propagation Delay t15 + 10 + t15 – 10 – t15 + 12 – t15 – 12 + t15 + 13 + t15 – 13 – 10 10 12 12 13 13 — — — — — — 22 19 5.2 5.0 4.8 5.0 — — — — — — 17 12 4.3 3.7 4.0 4.0 25 18 5.5 5.2 5.0 5.0 — — — — — — 27 18 5.8 5.2 5.2 5.1 ns 15 10 10 12 12 13 13 11,16 8,9 14 Rise Time t12 + t13 + 12 13 — — 4.0 4.0 — — 3.0 3.0 4.0 4.0 — — 4.4 4.4 ns ns 15 15 12 13 11,16 11,16 8,9 8,9 14 14 Fall Time t12 – t13 – 12 13 — — 4.0 4.0 — — 3.0 3.0 4.0 4.0 — — 4.0 4.0 ns ns 15 15 12 13 11,16 11,16 8,9 8,9 14 14 Characteristic TEST VOLTAGE APPLIED TO PINS LISTED BELOW Pin Under Test Min Typ Unit + 2.0 Vdc – 3.0 Vdc 2 3 650 650 750 750 mVp-p 1 8,9 + 25°C Sine Wave Amplitude Figure 7. AC Test Circuit – Sine Wave Output All output cables to the scope are equal lengths of 50 Ω coaxial cable. All unused cables must be terminated with a 50 Ω ± 1% resistor to ground. VCC = + 2.0 Vdc 450 Ω resistor and the scope termination impedance constitute a 10:1 attenuator probe. Crystal — Reeves Hoffman Series Mode, Series Resistance Minimum at Fundamental f = 10 MHz RE = 5 Ω *RS = 15 kΩ is inserted only for test purposes. When used with the above specified crystal, it guarantees oscillation with any crystal which has an equivalent series resistance 155 Ω 0.1 µF 0.1 µF 4 1 6 5 *RS Rp 8 3 450 2 450 9 VEE = – 3.0 Vdc 0.1 µF Crystal Rp: will improve start up problems value: 200–500 Ω Page 5 of 9 0.1 µF www.lansdale.com Issue A ML12061 LANSDALE Semiconductor, Inc. Frequency Stability Output frequency of different oscillator circuits (of a given device type number) will vary somewhat when used with a given test setup. However, the variation should be within approximately ±0.001% from unit to unit. Frequency variations with temperature (independent of the crystal, which is held at 25°C) are small — about –0.08ppm/°C for ML12061 operating at 8.0 MHz. that the higher harmonic levels (greater than the fifth) are increased when the MECL translator is being driven. Typically, the MECL outputs (pins 12 and 13) will drive up to five gates and the TTL output (pin10) will drive up to ten gates. Noise Characteristics Noise level evaluation of the sine wave outputs operation at or 9.0 MHz, indicates the following characteristics: 1. Noise floor (200 kHz from oscillator center frequency) is approximately –122 dB when referenced to a 1.0 Hz bandwidth. Noise floor is not sensitive to load conditions and/or translator operation. 2. Close-in noise (100 Hz from oscillator center frequency) is approximately –88 dB when referenced to a 1.0 Hz bandwidth. Figure 8. Frequency Variation Due to Temperature +10 f, FREQUENCY SHIFT (ppm) The ML12061 consists of three basic sections: an oscillator with AGC and two translators. Buffered complementary sine wave outputs are available from the oscillator section. The translators convert these sine wave outputs to levels compatible with MECL and/or TTL. Series mode crystals should be used with the oscillator. If it is necessary or desirable to adjust the crystal frequency, a reactive element can be inserted in series with the crystal — an inductor to lower the frequency or a capacitor to raise it. When such an adjustment is necessary, it is recommended that the crystal be specified slightly lower in frequency and a series trimmer capacitor be added to bring the oscillator back on frequency. As the oscillator frequency is changed from the natural resonance of the crystal, more and more dependence is placed on the external reactance, and temperature drift of the trimming components then affects overall oscillator performance. The ML12061 is designed to operate from a single supply — either +5.0 Vdc or –5.2 Vdc. Although each translator has separate VCC and VEE supply pins, the circuit is NOT designed to operate from both voltage levels at the same time. The separate VEE pin from the TTL translator helps minimize transient disturbance. If neither translator is being used, all unused pins (9 thru 16) should be connected to VEE (pin 8). With the translators not powered, supply current drain is typically reduced from 42 mA to 23 mA for the ML12061. VCC = +5.0 Vdc Tcrystal = 25°C 0 ML12061 –10 –20 ML12061 –30 –55 Signal Characteristics The sine wave outputs at either pin 2 or pin 3 will typically range from 800 mVp-p (no load) to 500 mVp-p (120 ohm AC load). Approximately 500 mVp-p can be provided across 50 ohms by slightly increasing the DC current in the output buffer by the addition of an external resistor (680 ohms) from pin 2 or 3 to ground, as shown in Figure 9. Frequency drift is typically less than 0.0003% when going from a high-impedance load (1 megohm, 15pF) to the 50 ohm load of Figure 9. The DC voltage level at pin 2 or 3 is nominally 3.5 Vdc with VCC = +5.0 Vdc. Harmonic distortion content in the sine wave outputs is crystal as well as circuit dependent. The largest harmonic (third) will usually be at least 15 dB down from the fundamental. The harmonic content is approximately load independent except Page 6 of 9 www.lansdale.com –25 0 25 50 75 TA, AMBIENT TEMPERATURE (°) 100 125 Figure 9. Driving Low Impedance Loads +5.0 V 0.1 µF 0.1 µF 0.1 µF 7 1 4 0.1 µF 2 or 3 6 5 8 680 50 * See text under signal characteristics. Issue A ML12061 LANSDALE Semiconductor, Inc. Figure 10. MECL Translator Load Capability Figure 11. TTL Translator Load Capability VCC = +5.0 V VCC = +5.0 V +5.0 V 0.1 µF 16 0.1 µF 11 13 Sine to MECL MECL to TTL Translator 12 15 pF 8 270 10 15 pF 1.5 k 8.2 k 9 All diodes MBD101 or Equiv Figure 12. Noise Measurement Test Circuit +5.0 V 0.1 µF 0.1 µF ANALYZER SETTING 0.1 µF 7 1 4 2 or 3 6 Page 7 of 9 5 8 0.1 µF Measurement Sweep Bandwidth Video Filter Noise Floor Close-In Noise 50 kHz/div 20 kHz/div 10 kHz 10 Hz 10 Hz 10 Hz To HP8552B/53B Spectrum Analyzer or Equiv 750 www.lansdale.com Issue A 1k Page 8 of 9 9.32k R1 R2 www.lansdale.com 6 Crystal 5 R2 8 9.32k VEE 410 205 410 1.5k 1.5k Sine Wave Output 2 3 + – 16 58 2 2.98k VCC 1.4k 241 15+ 130 241 680 14– 20 MECL Output 20 54 0 12 13 500 1.2k VCC 9 750 11 VEE 10 100 TTL Output 2 kΩ MECL to TTL Translator 400 Ω R3 (2 Places) R3 R3 R1 AGC Filter 4 Sine to MECL Translator 200 Ω R2 (2 Places) VCC 1 Amplifier / AGC ML12061 4 10 Bias 7 Oscillator RESISTOR R1 (2 Places) 260 Voltage Regulator ML12061 LANSDALE Semiconductor, Inc. Figure 13. Circuit Schematic Issue A ML12061 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS P DIP 16 = EP PLASTIC PACKAGE (ML12061EP) CASE 648–08 ISSUE R –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 9 of 9 www.lansdale.com Issue A