MM54HC640/MM74HC640 Inverting Octal TRI-STATEÉ Transceiver MM54HC643/MM74HC643 True-Inverting Octal TRI-STATE Transceiver General Description These TRI-STATE bi-directional buffers utilize advanced silicon-gate CMOS technology, and are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power consumption and high noise immunity usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Each device has an active low enable G and a direction control input, DIR. When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The MM54HC640/ MM74HC640 transfers inverted data from one bus to other and the MM54HC643/MM74HC643 transfers inverted data from the A bus to the B bus and true data from the B bus to the A bus. These devices can drive up to 15 LS-TTL Loads, and all inputs are protected from damage due to static discharge by diodes to VCC and ground. Features Y Y Y Y Y Typical propagation delay: 13 ns Wide power supply range: 2 – 6V Low quiescent current: 80 mA maximum (74 HC) TRI-STATE outputs for connection to bus oriented systems High output drive: 6 mA (min) Connection Diagrams Dual-In-Line Package Dual-In-Line Package TL/F/5344 – 2 TL/F/5344 – 1 Top View Top View Order Number MM54HC640 or MM74HC640 Order Number MM54HC643 or MM74HC643 Truth Table Control Inputs Operation G DIR 640 643 L L B data to A bus B data to A bus L H A data to B bus A data to B bus H X Isolation Isolation H e high level, L e low level, X e irrelevant TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/5344 RRD-B30M105/Printed in U. S. A. MM54HC640/MM74HC640 Inverting Octal TRI-STATE Transceiver MM54HC643/MM74HC643 True-Inverting Octal TRI-STATE Transceiver January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage DIR and G pins (VIN) DC Output Voltage (VIN, VOUT) Clamp Diode Current (ICD) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V Operating Temp. Range (TA) MM74HC MM54HC b 0.5 to VCC a 0.5V g 20 mA Min 2 Max 6 Units V 0 VCC V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise/Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V g 35 mA g 70 mA b 65§ C to a 150§ C 600 mW 500 mW 260§ C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC 54HC TA eb40 to 85§ C TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VCC or GND VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Input Leakage Current (G and DIR) 6.0V g 0.1 g 1.0 g 1.0 mA IOZ Maximum TRI-STATE Output VOUT e VCC or GND 6.0V Leakage Current Enable G e VIH g 0.5 g 5.0 g 10 mA ICC Maximum Quiescent Supply Current 8.0 80 160 mA VIN e VCC or GND IOUT e 0 mA 6.0V Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, tr e tf e 6 ns Symbol Parameter Conditions Guaranteed Limit Typ Units tPHL, tPLH Maximum Propagation Delay CL e 45 pF 13 17 ns tPZH, tPZL Maximum Output Enable Time RL e 1 kX CL e 45 pF 33 42 ns tPHZ, tPLZ Maximum Output Disable Time RL e 1 kX CL e 5 pF 32 42 ns AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C VCC Typ tPHL, tPLH tPZH, Maximum Propagation Delay Maximum Output Enable tPZL 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits CL e 50 pF CL e 150 pF 2.0V 2.0V 29 38 72 96 88 116 96 128 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 14 18 18 24 22 29 24 32 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 14 18 18 24 22 29 24 32 ns ns CL e 50 pF CL e 150 pF 2.0V 2.0V 70 80 184 216 224 260 240 284 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 35 41 46 54 56 65 60 71 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 31 36 41 47 50 57 54 62 ns ns RL e 1 kX tPHZ, tPLZ Maximum Output Disable Time RL e 1 kX CL e 50 pF 2.0V 4.5V 6.0V 47 33 31 172 43 41 208 52 50 224 56 54 ns ns ns tTHL, tTLH Output Rise and Fall Time CL e 50 pF 2.0V 4.5V 6.0V 20 6 5 60 12 10 75 15 13 90 18 15 ns ns ns CPD Power Dissipation Capacitance (Note 5) G e VIL G e VIH CIN Maximum Input Capacitance 5 10 10 10 pF CIN/OUT Maximum Input/Output Capacitance, A or B 15 20 20 20 pF 120 12 pF pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Logic Diagrams ’HC640 ’HC643 TL/F/5344 – 5 TL/F/5344 – 6 4 5 MM54HC640/MM74HC640 Inverting Octal TRI-STATE Transceiver MM54HC643/MM74HC643 True-Inverting Octal TRI-STATE Transceiver Physical Dimensions inches (millimeters) Order Number MM54HC640J, MM54HC643J, MM74HC640J or MM74HC643J See NS Package J20A LIFE SUPPORT POLICY Order Number MM74HC640N or MM74HC643N See NS Package N20A NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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