NSC MM58242V

MM58242 High Voltage Display Driver
General Description
Features
The MM58242 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel devices. It is available both in 28-pin molded dual-in-line packages or as dice. The MM58242 is particularly suited for driving high voltage (60V max) vacuum fluorescent (VF) displays (e.g., a 20-digit alphanumeric or dot matrix display).
Y
Applications
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards
Y
Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade
Block Diagram
TL/F/7924 – 1
FIGURE 1
COPSTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/7924
RRD-B30M105/Printed in U. S. A.
MM58242 High Voltage Display Driver
March 1991
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VDD)
VSS e 0V
Voltage at Any Input Pin
Display Voltage (VDIS)
Temperature Range
Min
VDD a 0.3V to VSS b0.3V
VDD to VDD b62.5V
62.5V
b 65§ C to a 150§ C
Voltage at Any Display Pin
VDD a lVDISl
Storage Temperature
Power Dissipation at a 25§ C
Molded DIP Package, Board Mount
Molded DIP Package, Socket Mount
Junction Temperature
Max
Units
V
V
§C
4.5
5.5
b 55
b 25
b 40
a 85
2.03W*
1.83W**
130§ C
Lead Temperature (Soldering, 10 sec.)
260§ C
*Molded DIP Package, Board Mount, iJA e 52§ C/W,
Derate 19.2 mW/§ C above a 25§ C.
**Molded DIP Package, Socket Mount, iJA e 58§ C/W,
Derate 17.2 mW/§ C above a 25§ C.
DC Electrical Characteristics
TA e b40§ C to a 85§ C, VDD e 5V g 0.5V, VSS e 0V unless otherwise specified
Symbol
IDD
IDIS
Parameter
Power Supply Currents
Conditions
Min
VIL
VIH
Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
Logic ‘0’
Logic ‘1’
(Note 1)
VOL
VOH
VOH
Data Output Logic Levels
Logic ‘0’
Logic ‘1’
Logic ‘1’
IOUT e 400 mA
IOUT e b10 mA
IOUT e b500 mA
VDDb0.5
2.8
VIN e 0V or VDD
b 10
IIN
Input Currents
DATA IN, CLOCK
ENABLE, BLANK
CIN
Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK
ROFF
Display Output Impedances
Output Off (Figure 3a)
RON
Output On (Figure 3b)
VDOL
Display Output Low Voltage
Note 1: 74LSTTL VOH e 2.7V
@
Typ
VIN e VSS or VDD, VSS e 0V, VDIS Disconnected
VDD e 5.5V, VSS e 0V, VDIS e 55V
All Outputs Low
Units
150
10
mA
mA
0.8
V
V
0.4
V
V
V
10
mA
15
pF
400
550
650
4.0
3.7
3.4
kX
kX
kX
kX
kX
kX
VDIS a 4
V
2.4
VDD e 5.5V, VSS e 0V
VDIS e b25V
VDIS e b40V
VDIS e b55V
VDIS e b25V
VDIS e 40V
VDIS e b55V
VDD e 5.5V, IOUT e Open Circuit,
b 55V s VDIS s b 25V
IOUT e b 400 mA, TTL VOH e 2.4V
Max
@
IOUT e b 400 mA.
2
60
70
80
3.0
2.6
2.3
VDIS
AC Electrical Characteristics TA e b40§ C to a 85§ C, VDD e 5V g 0.5V
Parameter
Conditions
Clock Input
Frequency, fC
High Time, tH
Low Time, tL
Min
Typ
Max
Units
800
300
300
kHz
ns
ns
100
100
ns
ns
100
100
ns
ns
(Notes 3 and 4)
Data Input
Set-Up Time, tDS
Hold Time, tDH
Enable Input
Set-Up Time, tES
Hold Time, tEH
(Note 2)
Data Output
CLOCK Low to Data Out
Time, tCDO
CL e 50 pF
500
ns
Note 2: For timimg purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC input waveform specification for test purposes: tr s 20 ns, tf s 20 ns, f e 800 kHz, 50% g 10% duty cycle.
Note 4: Clock input rise and fall times must not exceed 5 ms.
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
TL/F/7924 – 8
Top View
Order Number MM58242V
See NS Package Number V28A
TL/F/7924 – 2
Top View
FIGURE 2
Order Number MM58242N
See NS Package Number N28B
3
Functional Description
To clear (reset) the display driver at ‘‘power on’’ or any time,
the following flushing routine may be used. With the enable
signal high, clock in 20 zeroes. Drive the enable signal low
and the display will be blank. It is recommended to clear the
driver at power on.
In Figure 5 , the ENABLE signal acts as an envelope, and
only while this signal is at a logic ‘1’ does the circuit accept
CLOCK input signals. Data is transferred and shifted in the
internal shift register on the rising clock edge, i.e., ‘0’ – ‘1’
transition. When the ENABLE signal goes low, the contents
of the shift registers are latched, and the display will show
new data. During data transfer, the display will show old
data. DATA OUT is also provided on the MM58242 being
output on the falling edge. At any time, the display may be
blanked under processor control, using the BLANKING
CONTROL input.
This product is specifically designed to drive multiplexed or
non-multiplexed high voltage alphanumeric or dot matrix
vacuum fluorescent (VF) displays. Character generation is
done externally in the microprocessor, with a serial data
path to the display driver. The MM58242 uses three signals,
DATA IN, CLOCK and ENABLE, where ENABLE acts as an
external load signal. Display blanking can be achieved by
means of the BLANKING CONTROL input, and a logic ‘1’
will turn off all sections of the display. A block diagram of
the MM58242 is shown in Figure 1 .
Figure 2 shows the pinout of the MM58242 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of data
to be loaded into the shift register following ENABLE high).
A logic ‘1’ at the input will turn on the corresponding display
digit/segment/dot output.
A significant reduction in discrete board components can be
achieved by use of the MM58242, because external pulldown resistors are not required. Due to the nature of the
output stage, both its on and off impedance values vary as a
function of the display voltage applied, However, Figures 3a
and 3b show that this output impedance will remain constant for a fixed value of display voltage.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58242 is used to provide the
grid drive for a 40-digit 2 line 5 c 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
provided by another member of the high voltage display
driver family, namely the MM58248, which does not require
an externally generated load signal.
Figure 4 demonstrates the critical timing requirements between CLOCK and DATA IN for the MM58242.
TL/F/7924 – 3
FIGURE 3a. Output Impedance Off
TL/F/7924 – 4
FIGURE 3b. Output Impedance On
4
Timing Diagrams
TL/F/7924 – 5
For the purposes of AC measurement, VIH e 2.4V, VIL e 0.8V.
FIGURE 4. Clock and Data Timings
TL/F/7924 – 6
FIGURE 5. MM58242 Timings (Data Format)
Typical Application
TL/F/7924 – 7
FIGURE 6. Microprocessor-Controlled Word Processor
5
MM58242 High Voltage Display Driver
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number MM58242N
NS Package Number N28B
LIFE SUPPORT POLICY
Plastic Chip Carrier (V)
Order Number MM58242V
NS Package Number V28A
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