MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
8051 Embedded CRT Monitor Controller
MASK Version
FEATURES
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8051 core.
384-bytes internal RAM.
16K-bytes program Mask ROM.
14-channels 10V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
28 bi-direction I/O pin,12 dedicated pin,12 shared with DAC,4 shared with DDC/IIC interface.
5-output pin shared with H/V sync output and self test output pins.
SYNC processor for composite separation, polarity and frequency check, and polarity adjustment.
Built-in monitor self-test pattern generator.
Built-in low power reset circuit.
One slave mode IIC interface and one master mode IIC interface.
IIC interface for DDC1/DDC2B and EEPROM; only one EEPROM needed to store DDC1/DDC2B and
display mode information.
Dual 4-bit ADC or 4 channel 6-bit ADC.
Watchdog timer with programmable interval.
40-pin PDIP and 44-pin PLCC package.
GENERAL DESCRIPTION
The MTV112A micro-controller is an 8051 CPU core embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 384-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface,
24Cxx series EEPROM interface, A/D converter and a 16K-bytes internal program Mask ROM.
BLOCK DIAGRAM
STOUT
P0.0-7
P1.0-7
RD
WR
X1
X2
8051
CORE
P2.0-3
INT
1
RST
P0.0-7
RD
HSYNC
XFR
H / VSYNC
CONTROL
WR
VSYNC
HBLANK
VBLANK
WATCH-DOG
TIMER
14 CHANNEL
PWM DAC
RST
DA0-9
DA10-13
P3.0-P3.2
P3.4 P2.4-7
ADC
HSCL
HSDA
AD0
AD1
ISCL
DDC 1/2 B & FIFO
INTERFACE
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV112A Revision 1.9 05/18/2001
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MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
1.0 PIN CONNECTION
P1.0
P1.0
VDD
P1.1/HALFV
DA0/P5.0
VDD
P1.1/HALFV
DA0/P5.0
P1.2/HALFH
DA1/P5.1
P1.2/HALFH
DA1/P5.1
P1.3/HCLAMP
DA2/P5.2
P1.3/HCLAMP
DA2/P5.2
P1.4/AD2
DA3/P5.3
P1.4/AD2
DA3/P5.3
P1.5/AD3
DA4/P5.4
P1.5/AD3
DA4/P5.4
P1.6/AD0
DA5/P5.5
P1.6/AD0
DA5/P5.5
P1.7/AD1
DA6/P5.6
P1.7/AD1
DA6/P5.6
RST
DA7/P5.7
RST
DA7/P5.7
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
MTV112A
ISDA/P3.2/INT0
DA8
HSCL/P3.0/Rxd
DA9
HSDA/P3.1/Txd
DA8
STOUT/P4.2
ISDA/P3.2/INT0
HALFH/P4.3
STOUT/P4.2
MTV112A
DA9
HSYNC
DA10/P2.7
HSYNC
ISCL/P3.4/T0
DA11/P2.6
ISCL/P3.4/T0
DA10/P2.7
VSYNC
DA12/P2.5
VSYNC
DA11/P2.6
HBLANK/P4.1
DA13/P2.4
HCLAMP/P4.4
DA12/P2.5
VBLANK/P4.0
P2.3
HBLANK/P4.1
DA13/P2.4
X2
P2.2
VBLANK/P4.0
P2.3
X1
P2.1
X2
P2.2
P2.0/INT0
X1
P2.1
VSS
DA2/P5.2
DA3/P5.3
NC
41
40
VDD
1
42
P1.0
2
DA1/P5.1
P1.1/HALFV
3
DA0/P5.0
P1.2/HALFH
4
43
P1.3/HCLAMP
5
44
P1.4/AD2
6
VSS
P2.0/INT0
NC
7
39
DA4/P5.4
P1.5/AD3
8
38
DA5/P5.5
P1.6/AD0
9
37
DA6/P5.6
P1.7/AD1
10
36
DA7/P5.7
35
DA8
34
DA9
RESET
11
HSCL/P3.0/Rxd
12
HSDA/P3.1/Txd
13
33
STOUT/P4.2
ISDA/P3.2/INT0
14
32
DA10/P2.7
HSYNC
15
31
DA11/P2.6
ISCL/P3.4/T0
16
30
DA12/P2.5
VSYNC
17
29
NC
18
19
20
21
22
23
24
25
26
27
28
NC
HBLANK/P4.1
VBLANK/P4.0
X2
X1
VSS
P2.0/INT0
P2.1
P2.2
P2.3
DA13/P2.4
MTV112A
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MTV112A
(Rev 1.9)
MYSON
TECHNOLOGY
2.0 PIN DESCRIPTIONS
Name
P1.0
P1.1/HALFV
P1.2/HALFH
P1.3/HCLAMP
P1.4/AD2
P1.5/AD3
P1.6/AD0
P1.7/AD1
RST
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
ISDA/P3.2/INT0
HSYNC
ISCL/P3.4/T0
VSYNC
HCLAMP/P4.4
HBLANK/P4.1
VBLANK/P4.0
X2
X1
VSS
P2.0/INT0
P2.1
P2.2
P2.3
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7
STOUT/P4.2
HALFH/P4.3
DA9
DA8
DA7/P5.7
DA6/P5.6
DA5/P5.5
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
VDD
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
-
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin#
42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
38
39
41
42
43
44
1
Description
General purpose I/O
General purpose I/O / Vsync half frequency output.
General purpose I/O / Hsync half frequency output.
General purpose I/O / Hsync clamp pulse output.
General purpose I/O / ADC input.
General purpose I/O / ADC input.
General purpose I/O / ADC input
General purpose I/O / ADC input
Active high reset
IIC clock / General purpose I/O / Rxd
IIC data / General purpose I/O / Txd
IIC data / General purpose I/O / INT0
Horizontal SYNC or Composite SYNC
IIC clock / General purpose I/O / T0
Vertical SYNC
Hsync clamp pulse output / General purpose output
Horizontal blank / General purpose output
Vertical blank / General purpose output
Oscillator output
Oscillator input
Ground
General purpose I/O / INT0
General purpose I/O
General purpose I/O
General purpose I/O
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
Self-test video output / General purpose output
Hsync half frequency output / General purpose output
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
PWM DAC output / General purpose I/O (open-drain)
Positive power supply
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TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTION
1. 8051 CPU Core
MTV112A includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV112A.
1.2 Port 0, port 3.3, and ports 3.5 ~ 3.7 are not general-purpose I/O ports. They are dedicated to monitor
control or DAC pins.
1.3 INT1 and T1 input pins are not provided.
1.4 Ports 2.4 ~ 2.7 are shared with DAC pins; ports 3.0 ~ 3.2, and port3.4 are shared with monitor control
pins.
In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051.
The Txd/Rxd (P3.0/P3.1) pins are shared with DDC interface. INT0/T0 pins are shared with IIC interface. An
extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature maintains an external
interrupt source when IIC interface is enabled.
Note: All registers listed in this document reside in the external RAM area (XFR). For the internal
RAM memory map please refer to the 8051 spec.
Reg name
addr
PADMOD 30h (w)
PADMOD 31h (w)
PADMOD 37h (w)
SINT0 = 1
=0
IICF
=1
=0
DDCE = 1
=0
IICE
=1
=0
DA13E = 1
=0
DA12E = 1
=0
DA11E = 1
=0
DA10E = 1
=0
P57E = 1
=0
P56E = 1
=0
P55E = 1
=0
P54E = 1
=0
P53E = 1
=0
P52E = 1
=0
bit7
SINT0
P57E
-
bit6
IICF
P56E
-
bit5
DDCE
P55E
-
bit4
IICE
P54E
-
bit3
DA13E
P53E
-
bit2
DA12E
P52E
-
bit1
DA11E
P51E
-
bit0
DA10E
P50E
MORE
→ INT0 source is pin #21.
→ INT0 source is pin #12.
→ Selects 400kHz master IIC speed.
→ Selects 100kHz master IIC speed.
→ Pin #10 is HSCL; pin #11 is HSDA.
→ Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.
→ Pin #12 is ISDA; pin #14 is ISCL.
→ Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.
→ Pin #25 is DA13.
→ Pin #25 is P2.4.
→ Pin #26 is DA12.
→ Pin #26 is P2.5.
→ Pin #27 is DA11.
→ Pin #27 is P2.6.
→ Pin #28 is DA10.
→ Pin #28 is P2.7.
→ Pin #32 is P5.7.
→ Pin #32 is DA7.
→ Pin #33 is P5.6.
→ Pin #33 is DA6.
→ Pin #34 is P5.5.
→ Pin #34 is DA5.
→ Pin #35 is P5.4.
→ Pin #35 is DA4.
→ Pin #36 is P5.3.
→ Pin #36 is DA3.
→ Pin #37 is P5.2.
→ Pin #37 is DA2.
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MTV112A
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TECHNOLOGY
→ Pin #38 is P5.1.
→ Pin #38 is DA1.
→ Pin #39 is P5.0.
→ Pin #39 is DA0.
→ Bits P57E,P56E,P55E,P54E,P53E,P52E,P51E,P50E,DACK,EHALFV,
EHALFH,ENCLP,ADCMOD can be programmed,and master IIC speed is
controlled by (MCLK1,MCLK0) bits.
=0
→ above bits internal keep “0” by MTV112A, and master IIC speed is controlled by
IICF bit.
* SINT0 should be 0 in this case.
P51E
=1
=0
P50E = 1
=0
MORE = 1
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
SFR is a group of registers that is the same as standard 8051.
2.2 Internal RAM
There is a 384 bytes RAM in MTV112A. The first portion of the RAM area contains 256 bytes, accessible by
setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.
2.3 External Special Function Registers (XFR)
XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for
monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access
these registers.
FFH
80H
7FH
Accessible by indirect
addressing only.
The value of PSW.1 =
both 0 and 1.
(Using MOV A, @Ri
instruction)
SFR
Accessible by direct
addressing.
Accessible by direct
and indirect
addressing.
Accessible by direct
and indirect
addressing.
PSW.1=0
PSW.1 =1
FFH
XFR
00H
Accessible by indirect
external RAM
addressing.
(Using MOVX A, @Ri
Instruction.)
00H
3. PWM DAC
Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM clk
is X’tal or 2 * X’tal, selected by DACK. And the frequency of these DAC outputs is (PWM clk frequency)/253
or (PWM clk frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register
generates stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's
content is FFH. Writing 00H to the DAC register generates stable low output.
reg name
DA0
DA1
DA2
DA3
addr
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
bit7
DA0b7
DA1b7
DA2b7
DA3b7
bit6
DA0b6
DA1b6
DA2b6
DA3b6
bit5
DA0b5
DA1b5
DA2b5
DA3b5
bit4
DA0b4
DA1b4
DA2b4
DA3b4
bit3
DA0b3
DA1b3
DA2b3
DA3b3
bit2
DA0b2
DA1b2
DA2b2
DA3b2
bit1
DA0b1
DA1b1
DA2b1
DA3b1
bit0
DA0b0
DA1b0
DA2b0
DA3b0
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MTV112A
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DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
WDT
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
80h
DA4b7
DA5b7
DA6b7
DA7b7
DA8b7
DA9b7
DA10b7
DA11b7
DA12b7
DA13b7
WEN
DA0 (r/w) :
DA1 (r/w) :
DA2 (r/w) :
DA3 (r/w) :
DA4 (r/w) :
DA5 (r/w) :
DA6 (r/w) :
DA7 (r/w) :
DA8 (r/w) :
DA9 (r/w) :
DA10 (r/w) :
DA11 (r/w) :
DA12 (r/w) :
DA13 (r/w) :
WDT (w) :
DIV253
DACK
DA4b6
DA5b6
DA6b6
DA7b6
DA8b6
DA9b6
DA10b6
DA11b6
DA12b6
DA13b6
WCLR
DA4b5
DA5b5
DA6b5
DA7b5
DA8b5
DA9b5
DA10b5
DA11b5
DA12b5
DA13b5
DA4b4
DA5b4
DA6b4
DA7b4
DA8b4
DA9b4
DA10b4
DA11b4
DA12b4
DA13b4
CLRDDC DIV253
DA4b3
DA5b3
DA6b3
DA7b3
DA8b3
DA9b3
DA10b3
DA11b3
DA12b3
DA13b3
DACK
DA4b2
DA5b2
DA6b2
DA7b2
DA8b2
DA9b2
DA10b2
DA11b2
DA12b2
DA13b2
WDT2
DA4b1
DA5b1
DA6b1
DA7b1
DA8b1
DA9b1
DA10b1
DA11b1
DA12b1
DA13b1
WDT1
DA4b0
DA5b0
DA6b0
DA7b0
DA8b0
DA9b0
DA10b0
DA11b0
DA12b0
DA13b0
WDT0
The output pulse width control for DA0.
The output pulse width control for DA1.
The output pulse width control for DA2.
The output pulse width control for DA3.
The output pulse width control for DA4.
The output pulse width control for DA5.
The output pulse width control for DA6.
The output pulse width control for DA7.
The output pulse width control for DA8.
The output pulse width control for DA9.
The output pulse width control for DA10.
The output pulse width control for DA11.
The output pulse width control for DA12.
The output pulse width control for DA13.
Watchdog timer & special control bit.
=1
→ The PWM DAC outputs frequency is (PWM clk frequency)/253.
=0
→ The PWM DAC output frequency is Xtal frequency/256.
=1
→ The PWM clk frequency is 2 x (X’tal frequency).
=0
→ The PWM clk frequency is (X’tal frequency).
*1. All D/A converters are centered with value 80h after power-on.
4. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation, SYNC input
presence check, frequency counting, and polarity detection and control, as well as the protection of VBLANK
output while VSYNC speeds up to a high DDC communication clock rate. The present and frequency
function block treat any pulse less than one OSC period as noise.
4.1 Composite SYNC Separation
MTV112A continuously monitors the input HSYNC. If the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and the user can select the extracted "CVSYNC" for the source of polarity check,
frequency count and VBLANK. The CVSYNC will have a 10-16 us delay compared to the original signal. The
delay depends on the OSC frequency and composite mix method.
4.2 H/V Frequency Counter
MTV112A can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 15-bit
Hcounter counts the time of the 64xHSYNC period, but only 11 upper bits are loaded into the
HCNTH/HCNTL latch. The 11-bit output value is {2/H-Freq} / {1/OSC-Freq}, updated once per
VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC
is not present. The 14-bit Vcounter counts the time between 2 VSYNC pulses, but only 9 upper bits are
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loaded into the VCNTH/VCNTL latch. The 9-bit output value is {1/V-Freq} / {512/OSC-Freq}, updated every
VSYNC/CVSYNC period. An extra overflow bit indicates the condition of the H/V counter overflow. The
VFchg/HFchg interrupt is active when VCNT/HCNT value changes or overflows. Tables 4.2.1 and 4.2.2
shows the HCNT/VCNT value under the operations of 8MHz and 12MHz.
4.2.1 H-Freq Table
H-Freq(KHZ)
1
2
3
4
5
6
7
8
9
10
11
12
13
30
31.5
33.5
35.5
36.8
38
40
48
50
57
60
64
100
Output Value (11 bits)
8MHz OSC (hex / dec)
12MHz OSC (hex / dec)
215h / 533
320h / 800
1FBh / 507
2F9h / 761
1DDh /477
2CCh / 716
1C2h / 450
2A4h / 676
1B2h / 434
28Ch / 652
1A5h / 421
277h / 631
190h / 400
258h / 600
14Dh / 333
1F4h / 500
140h / 320
1E0h / 480
118h / 280
1A5h / 421
10Ah / 266
190h / 400
0FAh / 250
177h / 375
0A0h / 160
0F0h / 240
*1. The H-Freq output (HF10 - HF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.2.2 V-Freq Table
V-Freq(Hz)
1
2
3
4
5
6
7
8
9
10
11
12
56.25
59.94
60
60.32
60.53
66.67
70.069
70.08
72
72.378
72.7
87
Output Value (9 bits)
8MHz OSC (hex / dec)
12MHz OSC (hex / dec)
115h / 277
1A0h / 416
104h / 260
187h / 391
104h / 260
186h / 390
103h / 259
184h / 388
102h / 258
183h / 387
0EAh / 234
15Fh / 351
0DEh / 222
14Eh / 334
0DEh / 222
14Eh / 334
0D9h /217
145h / 325
0D7h / 215
143h / 323
0D6h / 214
142h / 322
0B3h / 179
10Dh / 269
*1. The V-Freq output (VF8 - VF0) is valid.
*2. The tolerance deviation is + 1 LSB.
4.3 H/V Presence Check
The Hpresent function checks the input HSYNC pulse. The Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse. The Vpre flag
is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. A control bit "PREFS" selects the
time base for these functions. The HPRchg interrupt is set when the Hpre value changes. The VPRchg
interrupt is set when the Vpre/CVpre value changes. However, the CVpre flag interrupt may be disabled
when S/W disables the composite function.
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4.4 H/V Polarity Detection
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
4.5 Output HBLANK/VBLANK Control and Polarity Adjustment
The HBLANK is the mux output of HSYNC and self-test horizontal pattern. The VBLANK is the mux output of
VSYNC, CVSYNC and the self-test vertical pattern. The mux selection and output polarity are S/W
controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz or 133Hz depends on
8MHz/12MHz OSC selection. The HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
4.6 Self-Test Pattern Generator
This generator can generate 4 display patterns for testing purposes: positive cross-hatch, negative crosshatch, full white, and full black (shown in the following figure). It was originally designed to support the
monitor manufacturer in performing a burn-in test, or to offer the end-user a reference to check the monitor.
The generator's output STOUT shares the output pin with P4.2.
Display Region
Positive Cross-Hatch
Negative Cross-Hatch
Full White
Full Black
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D
Hor.
C
E
B
A
R
Vert.
Q
S
P
O
MTV112A Self-Test Pattern Timing (8MHz)
Hor. Total Time
Hor. Acitve Time
Hor. F. P.
SYNC Pulse Width
Hor. B. P.
Hor. Total Time
Hor. Active Time
Hor. F. P.
SYNC Pulse Width
Hor. B. P.
63.5KHz, 60Hz
Absolute time
H dots
Us(A)=15.75
1280
Us(D)=12.05
979.3
Us(E)=0.2
16.25
Us(B)=1.5
122
Us(C)=2
162.54
V lines
Us(O)=16.6635
Us(R)=15.6555
Us(S)=0.063
Us(P)=0.063
Us(Q)=0.882
31.7KHz, 60Hz
Absolute time
H dots
Us(A)=31.5
640
Us(D)=24.05
488.6
Us(E)=0.45
9
Us(B)=3
61
Us(C)=4
81.27
V lines
Us(O)=16.6635
Us(R)=15.6555
Us(S)=0.063
Us(P)=0.063
Us(Q)=0.882
1024
962
3.87
3.87
54.2
480
451
1.82
1.82
25.4
* 8 x 8 blocks of cross-hatch pattern in display region.
4.7 VSYNC Interrupt
MTV112A checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC1 flag
is set each time MTV112A detects a VSYNC pulse.
4.8 H/V SYNC Processor Register
reg name
PSTUS
HCNTH
HCNTL
VCNTH
VCNTL
PCTR0
PCTR2
PCTR3
P4OUT
addr
40h (r)
41h (r)
42h (r)
43h (r)
44h (r)
40h (w)
42h (w)
43h (w)
44h (w)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
CVpre
X
Hpol
Vpol
Hpre
Vpre
Hoff
Hovf
X
X
X
X
HF10
HF9
HF7
HF6
HF5
HF4
HF3
HF2
HF1
Vovf
X
X
X
X
X
X
VF7
VF6
VF5
VF4
VF3
VF2
VF1
C1
C0
HVsel STOsel PREFS HALFV
HBpl
STbsh
X
X
X
Selft
Rt1
Rt0
ENCLP CLPEG CLPPO CLPW2 CLPW1 CLPW0 EHALFV
X
X
X
P44
P43
P42
P41
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
STF
EHALFH
P40
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P5OUT 45h (r/w)
P57
P56
P55
P54
PCTR6 46h (w)
X
X
X
X
INTFLG 50h (r/w) HPRchg VPRchg HPLchg VPLchg
INTEN
60h (w) EHPR
EVPR
EHPL
EVPL
INTFLG 51h(r/w)
X
X
X
X
INTEN
61h(w)
X
X
X
X
Digital Filter
P53
X
HFchg
EHF
X
X
P52
X
VFchg
EVF
X
X
Present
Check
Vpre
Frequency
Count
Vfreq
Polarity
Check
Vpol
P51
CLPsel
FIFOI
EFIFO
X
X
P50
HALFHsel
MI
EMI
VSYNC
EVSI
VBpl
VSYNC
High
Frequency
Mask
Vself
VBLANK
CVSYNC
Present
Check
Polarity Check &
Sync Seperator
Hpol
Hself
CVpre
HBpl
HBLANK
HSYNC
Present Check &
Frequency Count
Digital Filter
Hpre
Hfreq
H/V SYNC Processor Block Diagram
PSTUS (r) :
The status of polarity, presence and static level for HSYNC and VSYNC.
CVpre = 1
→ The extracted CVSYNC is present.
=0
→ The extracted CVSYNC is not present.
Hpol
=1
→ HSYNC input is positive polarity.
=0
→ HSYNC input is negative polarity.
Vpol
=1
→ VSYNC (CVSYNC) is positive polarity.
=0
→ VSYNC (CVSYNC) is negative polarity.
Hpre = 1
→ HSYNC input is present.
=0
→ HSYNC input is not present.
Vpre
=1
→ VSYNC input is present.
=0
→ VSYNC input is not present.
Hoff* = 1
→ HSYNC input's off-level is high.
=0
→ HSYNC input's off-level is low.
Voff* = 1
→ VSYNC input's off-level is high.
=0
→ VSYNC input's off-level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) :
H-Freq counter's high bits.
Hovf
=1
→ H-Freq counter overflows; this bit is cleared by H/W when condition removed.
HF10 - HF8 : 3 high bits of H-Freq counter.
HCNTL (r) :
H-Freq counter's low bits.
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VCNTH (r) :
Vovf
VF8 :
V-Freq counter's high bits.
=1
→ V-Freq counter overflows; this bit is cleared by H/W when condition removed.
High bit of V-Freq counter.
VCNTL (r) :
V-Freq counter's low bits.
PCTR0 (w) :
SYNC processor control register 0.
C1, C0 = 1,1 → Selects CVSYNC as the polarity, Freq and VBLANK source.
= 1,0 → Selects VSYNC as the polarity, Freq and VBLANK source.
= 0,0 → Disables composite function (MTV012 compatible mode).
= 0,1 → H/W auto switches to CVSYNC when CVpre=1 and VSpre=0.
HVsel = 1
→ Pin #16 is P4.1, pin #17 is P4.0.
=0
→ Pin #16 is HBLANK, pin #17 is VBLANK.
STOsel = 1
→ Pin #29 is P4.2.
=0
→ Pin #29 is STOUT.
PREFS = 0
→ Selects 8MHz OSC as H/V presence check and self-test pattern time base.
=1
→ Selects 12MHz OSC as H/V presence check and self-test pattern time base.
HALFV = 1
→ VBLANK is half frequency output of VSYNC.
HBpl = 1
→ Negative polarity HBLANK output.
=0
→ Positive polarity HBLANK output.
VBpl = 1
→ Negative polarity VBLANK output.
=0
→ Positive polarity VBLANK output.
PCTR2 (w) :
Selft
Self-test pattern generator control.
=1
→ Enables generator.
=0
→ Disables generator.
STbsh = 1
→ 63.5KHz (horizontal) output selected.
=0
→ 31.75KHz (horizontal) output selected.
Rt1, Rt0= 0,0 → Positive cross-hatch pattern output.
= 0,1 → Negative cross-hatch pattern output.
= 1,0 → Full white pattern output.
= 1,1 → Full black pattern output.
STF
=1
→ Enables STOUT output.
=0
→ Disables STOUT output.
PCTR3 (w) :
HSYNC clamp pulse control register.
ENCLP = 1
→ pin #4 is HCLAMP.
=0
→ pin #4 is P1.3.
CLPEG = 1
→ Clamp pulse follows HSYNC leading edge.
=0
→ Clamp pulse follows HSYNC trailing edge.
CLPPO= 1
→ Positive polarity clamp pulse output.
=0
→ Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] X 0.25 µs for 8MHz X’tal selection,or
[(CLPW2:CLPW0) + 1] X 0.167 µs for 12MHz X’tal selection.
EHALFV= 1
→ pin #2 is HALFV.
=0
→ pin #2 is P1.1.
EHALFV= 1
→ pin #3 is HALFH.
=0
→ pin #3 is P1.2.
P4OUT (w) :
Port 4 data output value.
P5OUT (r/w) :
Port 5 data input/output value.
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PCTR6 (w) :
Sync processor control register 6.
CLPsel = 1
→ pin HCLAMP/P4.4 is P4.4.
=0
→ pin HCLAMP/P4.4 is HCLAMP.
HALFHsel = 1 → pin HALFH/P4.3 is P4.3.
=0
→ pin HALFH/P4.3 is HALFH.
INTFLG (w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enabler bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serving the interrupt routine.
HPRchg= 1
→ No action.
=0
→ Clears HSYNC presence change flag.
VPRchg= 1
→ No action.
=0
→ Clears VSYNC presence change flag.
HPLchg= 1
→ No action.
=0
→ Clears HSYNC polarity change flag.
VPLchg = 1
→ No action.
=0
→ Clears VSYNC polarity change flag.
HFchg = 1
→ No action.
=0
→ Clears HSYNC frequency change flag.
VFchg = 1
→ No action.
=0
→ Clears VSYNC frequency change flag.
VSYNCi= 1
→ No action.
=0
→ Clears VSYNC interrupt flag.
INTFLG (r) :
Interrupt flag.
HPRchg= 1
→ Indicates an HSYNC presence change.
VPRchg= 1
→ Indicates a VSYNC presence change.
HPLchg= 1
→ Indicates a HSYNC polarity change.
VPLchg = 1
→ Indicates a VSYNC polarity change.
HFchg = 1
→ Indicates an HSYNC frequency change or counter overflow.
VFchg = 1
→ Indicates a VSYNC frequency change or counter overflow.
VSYNCi= 1
→ Indicates a VSYNC interrupt.
INTEN (w) :
EHPR
EVPR
EHPL
EVPL
EHF
EVF
EVSI
Interrupt enabler.
=1
→ Enables HSYNC presence change interrupt.
=1
→ Enables VSYNC presence change interrupt.
=1
→ Enables HSYNC polarity change interrupt.
=1
→ Enables VSYNC polarity change interrupt.
=1
→ Enables HSYNC frequency change / counter overflow interrupt.
=1
→ Enables VSYNC frequency change / counter overflow interrupt.
=1
→ Enables VSYNC interrupt.
5. DDC & IIC Interface
5.1 DDC1 Mode
MTV112A enters DDC1 mode after Reset. In this mode, VSYNC is used as a data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from 8 bytes f FIFO in MTV112A. MTV112A
fetches the data byte from FIFO, then sends it in a 9-bit packet format which includes a null bit (=1) as
packet separator. The software program should load EDID data (original stored in EEPROM) into FIFO and
take care of the FIFO depth. FIFO sets the FIFOI (FIFO low interrupt) flag when there are fewer than N
(N=2,3,4 or 5 controlled by LS1, LS0) bytes to be output to the HSDA pin. To prevent FIFO from emptying,
software needs to write EDID data to FIFO as soon as FIFOI is set. On the other hand, FIFO sets the FIFOH
flag when its capacity is full. Software should not write additional data to FIFO in such instance. The FIFOI
interrupt can be masked or enabled by an EFIFO control bit. A simple way to control FIFO is to set (LS1,
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LS0=1,0) and enable FIFOI interrupt, then software may load 4 bytes into FIFO each time a FIFOI interrupt
arises. A special control bit "LDFIFO" can reduce the software effort when EDID data is stored in EEPROM.
If LDFIFO=1, FIFO will be automatically loaded with MBUF data when software reads MBUF XFR.
5.2 DDC2B Mode
MTV112A switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV112A enters DDC2B mode, the host can access the EEPROM using IIC bus protocol as if the HSDA
and HSCL are directly bypassed to ISDA and ISCL pins. MTV112A will return to DDC1 mode if HSCL is
kept high for a 128 VSYNC clock period. However, it will lock in DDC2B mode if a valid IIC access has been
detected on HSCL/HSDA bus. The DDC2 flag reflects the current DDC status. S/W may clear it by setting
CLRDDC. Control bits M128/M256 are used to block the EEPROM write operation from the host if the
address is over 128/256.
5.3 Master Mode IIC Function Block
The master mode IIC block is connected to the ISDA and ISCL pins. Its speed can be selected to 100kHz or
400kHz by s/w set IICF control bit while MORE=0, or to 50KHz,100KHz,200KHz or 400KHz by s/w set
(MCLK1,MCLK0) bits while MORE=1. The software program can access the external EEPROM through this
interface. Since the EDID/VDIF data and display information share the common EEPROM, precaution must
be taken to avoid bus conflict. In DDC1 mode, the IIC interface is controlled by MTV112A only. In DDC2B
mode, the host may access the EEPROM directly. Software can test the HSCL condition by reading the
BUSY flag, which is set in case HSCL=0. A summary of master IIC access is illustrated as follows:
5.3.1. To Write EEPROM
1. Write the EEPROM slave address to MBUF (bit 0 = 0).
2. Set the S bit to Start.
3. After MTV112A transmits this byte, an MI interrupt will be triggered.
4. The program can write MBUF to transfer the next byte or set the P bit to Stop.
* Please see the attachments about "Master IIC Transmission Timing".
5.3.2. To Read EEPROM
1. Write the slave address to MBUF (bit 0 = 1).
2. Set the S bit to Start.
3. After MTV112A transmits this byte, a MI interrupt will be triggered.
4. Set or reset the ACK flag according to the IIC protocol.
5. Read out the useless byte to MBUF to continue the data transfer.
6. After MTV112A receives a new byte, the MI interrupt is triggered again.
7. Reading MBUF also triggers the next receiving operation, but setting the P bit before reading can
terminate the operation.
* Please see the attachments about "Master IIC Timing Receiving".
5.4 Slave Mode IIC Function Block
The slave mode IIC block can be connected to HSDA/HSCL or ISDA/ISCL pins, and selected by the SLVsel
control bit. This block can receive/transmit data using the IIC protocol. S/W may set the SLVADR register to
determine which slave address the block should respond to.
In receiving mode, the block first detects an IIC slave address match condition then issues a SLVMI interrupt.
The data received from SDA is shifted into a shift register and written to the RCBUF latch. The first byte
loaded is the word address (slave address is dropped). This block also generates an RCBI (Receive Buffer
full Interrupt) each time the RCBUF is loaded. If S/W can't read out the RCBUF in time, the next byte will not
be written to RCBUF and the slave block will return NACK to the master. This feature guarantees the data
integrity of communication. A WADR flag can tell S/W if the data in RCBUF is a word address.
In transmission mode, the block first detects an IIC slave address match condition then issues a SLVMI. In
the meantime, the data pre-stored in the TXBUF is loaded into the shift register, results in TXBUF emptying
and generates a TXBI (Transmission Buffer Interrupt). S/W should write the TXBUF a new byte for the next
transfer before the shift register empties. Failure to do this will cause data corruption. The TXBI occurs each
time the shift register receives new data from TXBUF. The SLVMI is cleared by writing the SLVSTUS
register. The RCBI is cleared by reading the RCBUF. The TXBI is cleared by writing the TXBUF.
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If the control bit ENSCL is set, the block will hold SCL low until the RCBI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
Reg name
MCTR
MSTUS
MCTR
MBUF
INTFLG
INTEN
FIFO
SLVCTR
SLVSTUS
SLVSTUS
RCBUF
TXBUF
SLVADR
addr
00h (w)
00h (r)
01h (w)
10h (r/w)
50h (r/w)
60h (w)
70h (w)
90h (w)
91h (r)
91h (w)
92h (r)
92h (w)
93h (w)
bit7
LS1
X
X
MBUF7
HPRchg
EHPR
FIFO7
ENSLV
WADR
bit6
LS0
SCLERR
X
MBUF6
VPRchg
EVPR
FIFO6
SLVsel
SLVS
RCbuf7 RCbuf6
TXbuf7 TXbuf6
SLVadr7 SLVadr6
bit5
bit4
bit3
bit2
LDFIFO M256
M128
ACK
DDC2
BERR HFREQ FIFOH
X
X
X
X
MBUF5 MBUF4 MBUF3 MBUF2
HPLchg VPLchg HFchg VFchg
EHPL
EVPL
EHF
EVF
FIFO5 FIFO4 FIFO3 FIFO2
ERCBI ESLVMI ETXBI ENSCL
RCBI
SLVMI
TXBI
RWB
Write to clear SLVMI
RCbuf5 RCbuf4 RCbuf3 RCbuf2
TXbuf5 TXbuf4 TXbuf3 TXbuf2
SLVadr5 SLVadr4 SLVadr3 SLVadr2
bit1
bit0
P
S
FIFOL
BUSY
MCLK1 MCLK0
MBUF1 MBUF0
FIFOI
MI
EFIFO
EMI
FIFO1 FIFO0
X
X
ACKIN
X
RCbuf1 RCbuf0
TXbuf1 TXbuf0
SLVadr1
X
MCTR (w) :
Master IIC interface control register.
LS1, LS0
= 11
→ FIFOL is the status in which FIFO depth < 5.
= 10
→ FIFOL is the status in which FIFO depth < 4.
= 01
→ FIFOL is the status in which FIFO depth < 3.
= 00
→ FIFOL is the status in which FIFO depth < 2.
LDFIFO
=1
→ FIFO will be written while S/W reads MBUF.
M256
=1
→ Disables host writing EEPROM when address is over 256.
M128
=1
→ Disables host writing EEPROM when address is over 128.
ACK
=1
→ In receiving mode, no acknowledgment is given by MTV112A.
=0
→ In receiving mode, ACK is returned by MTV112A.
S, P
= ↑, 0 → Start condition when Master IIC is not transferring.
= X, ↑ → Stop condition when Master IIC is not transferring.
= 1, X → Will resume transfer after a read/write MBUF operation.
= X, 0 → Forces HSCL low and occupies the IIC bus.
MCLK1 : MCLK0 : Master IIC speed select,
=0
→ 50KHz for 8MHz X’tal, 75KHz for 12MHz X’tal.
=1
→ 100KHz for 8MHz X’tal, 150KHz for 12MHz X’tal.
=2
→ 200KHz for 8MHz X’tal, 300KHz for 12MHz X’tal .
=3
→ 400KHz for 8MHz X’tal, 600KHz for 12MHz X’tal.
* MTV112A uses a 100KHz clock to sample the S/P bit; any pulse should sustain at least 20us.
* A write/read MBUF operation can be recognized only after 10us of the MI flag's rising edge.
MSTUS (r) :
Master IIC interface status register.
SCLERR
=1
→ The ISCL pin has been pulled low by other devices during the transfer,
cleared when S=0.
DDC2
=1
→ DDC2B is active.
=0
→ MTV112A remains in DDC1 mode.
BERR
=1
→ IIC bus error, no ACK received from the slave, updated each time the
slave sends ACK on the ISDA pin.
HFREQ
=1
→ MTV112A has detected a higher than 200Hz clock on the VSYNC pin.
FIFOH
=1
→ FIFO high indicated.
FIFOL
=1
→ FIFO low indicated.
BUSY
=1
→ Host drives the HSCL pin to low.
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* While writing FIFO, the FIFOH/FIFOL flag will reflect the FIFO condition after 30us.
MBUF (w) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV112A's transmission to the IIC bus.
MBUF (r) :
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV112A's receiving from the IIC bus.
INTFLG (w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enabler bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serving the interrupt routine.
FIFOI = 1
→ No action.
=0
→ Clears FIFOI flag.
MI
=1
→ No action.
=0
→ Clears Master IIC bus interrupt flag (MI).
INTFLG (r) :
Interrupt flag.
FIFOI = 1
→ Indicates the FIFO low condition; when EFIFO is set, MTV112A will be interrupted
by INT1.
MI
=1
→ Indicates when a byte is sent/received to/from the IIC bus; when EME is active,
MTV112A will be interrupted by INT1.
INTEN (w) :
Interrupt enabler.
EFIFO = 1
→ Enables FIFO interrupt.
EMI
=1
→ Enables Master IIC bus interrupt.
FIFO (w) :
Writes FIFO contents.
SLVCTR (w) : Slave IIC block control.
ENSLV
=1
→ Enables slave IIC block.
=0
→ Disables slave IIC block.
SLVsel
=1
→ Slave IIC connects to ISDA/ISCL.
=0
→ Slave IIC connects to HSDA/HSCL.
ERCBI
=1
→ Enables slave receiving buffer interrupt.
ESLVMI
=1
→ Enables slave address match interrupt.
ETXBI
=1
→ Enables slave transmission buffer interrupt.
ENSCL
=1
→ Enables slave block to hold SCL pin low.
SLVSTUS (r) : Slave IIC block
WADR
=1
SLVS
=1
RCBI
=1
SLVMI
=1
TXBI
RWB
ACKIN
=1
=1
=0
=1
status.
→ The data in SLVBUF is a word address.
→ The slave block has detected a START; cleared when STOP detected.
→ RCBUF has loaded a new data byte; reset by S/W reading RCBUF.
→ The slave block has detected the slave address match condition; cleared
by S/W writing SLVSTUS.
→ TXBUF is empty; reset by S/W writing TXBUF.
→ Current transfer is slave transmitting.
→ Current transfer is slave receiving.
→ Master responds to NACK.
SLVSTUS (w) : Clears SLVMI flag.
RCBUF (r) :
Slave IIC receives data buffer.
TXBUF (w) :
Slave IIC transmits data buffer.
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SLVADR (w) : Slave IIC address to which the slave block should respond.
6. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of the power supply is below 4.0V for a specific time, the LVR will generate a chip
resetting signal. After the power supply is above 4.0V, LVR maintains the reset state for 144 Xtal cycles to
guarantee the chip exit reset condition has a stable Xtal oscillation. The specific time of power supply in a
low level is 3us and is adjustable by an external capacitor connected to the RST pin.
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
0.25 sec x N, in which N is a number from 1 to 8, and can be programmed via register WDT (2:0). The timer
function is disabled after power-on reset. The user can activate this function by setting WEN and clear the
timer by setting WCLR.
7. A/D Converter
The MTV112 is equipped with two 4-bit or four 6-bit A/D converters. Each one can be enabled/disabled by
S/W control. The refresh rate for the ADC is OSC freq./6144(4-bit) or OSC freq./12288(6-bit). The ADC
compare the input pin voltage with the internal VDD*N/16(4-bit) or VDD*N/64(6-bit) voltage (where N = 0 -15
or N = 0 - 63). The ADC output value is N when pin voltage is greater than VDD*N/16 or VDD *N/64 and
smaller than VDD*(N+1)/16 or VDD*(N+1)/64.
Reg name
ADC
ADC
ADC
WDT
addr
bit7
A0h (w) ENADC
A0h (r) AD1b3
A0h (r)
X
80h (w) WEN
bit6
bit5
bit4
X
X
X
AD1b2 AD1b1 AD1b0
X
ADb5
ADb4
WCLR CLRDDC DIV253
bit3
X
AD0b3
ADb3
DACK
bit2
X
AD0b2
ADb2
WDT2
bit1
bit0
EADC1 EADC0
AD0b1 AD0b0
ADb1
ADb0
WDT1 WDT0
WDT (w) :
Watchdog timer control register.
WEN
=1
→ Enables watchdog timer.
WCLR
=1
→ Clears watchdog timer.
CLRDDC
=1
→ Clears DDC2 flag.
WDT2: WDT0 = 0
→ Overflow interval = 8 x 0.25 sec.
=1
→ Overflow interval = 1 x 0.25 sec.
=2
→ Overflow interval = 2 x 0.25 sec.
=3
→ Overflow interval = 3 x 0.25 sec.
=4
→ Overflow interval = 4 x 0.25 sec.
=5
→ Overflow interval = 5 x 0.25 sec.
=6
→ Overflow interval = 6 x 0.25 sec.
=7
→ Overflow interval = 7 x 0.25 sec.
ADC (w) :
ADC control.
ENADC
=1
ADCMOD
=1
EADC3
EADC2
EADC1
EADC0
=0
=1
=1
=1
=1
→ Enables ADC.
→ 4 channels 6 bits ADC are selected.
Note: Only one ADC input can be enabled at the same time.
→Dual 4 bits ADC are selected.(ADC1 and ADC0)
→ Enables ADC3 pin input.
→ Enables ADC2 pin input.
→ Enables ADC1 pin input.
→ Enables ADC0 pin input.
ADC (r) :
ADC conversion result.
AD1b3: AD1b0 4-bit ADC1 convert result.
AD0b3: AD0b0 4-bit ADC0 convert result.
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ADb5: ADb0
6-bit ADC convert result.
4.0 Test Mode Condition
In normal applications, users should avoid the MTV012 entering its test/program mode, outlined as follow:
Test Mode A: RESET=1 & DA9=0 & DA8=1 & DA7=1 &DA6=0
Test Mode B: RESET falling edge & DA9=1 & DA8=0 & DA7=1 & DA6=0
5.0 ELECTRICAL PARAMETERS
5.1 Absolute Maximum Ratings
at: Ta= 0 to 70 oC, VSS=0V
Name
Maximum Supply Voltage
Maximum Input Voltage
Maximum Output Voltage
Maximum Operating Temperature
Maximum Storage Temperature
Symbol
VDD
Vin
Vout
Topg
Range
-0.3 to +6.0
-0.3 to VDD+0.3
-0.3 to VDD+0.3
0 to +70
Unit
V
V
V
oC
Tstg
-25 to +125
oC
5.2 Allowable Operating Conditions
at: Ta= 0 to 70 oC, VSS=0V
Name
Supply Voltage
Input "H" Voltage
Input "L" Voltage
Operating Freq.
Symbol
VDD
Vih1
Vil1
Fopg
Min.
4.0
0.4 x VDD
-0.3
-
Max.
6.0
VDD +0.3
0.15 x VDD
15
Unit
V
V
V
MHz
5.3 DC Characteristics
at: Ta=0 to 70 oC, VDD=4.0V ~ 6.0V, VSS=0V
Name
Symbol
Condition
Output "H" Voltage, except openVoh1 Ioh=-50uA
drain pins: pin #s 16, 17, 29
Output "H" Voltage, pin #s 16, 17, 29
Voh2 Ioh=-1mA
Output "L" Voltage
Vol
Iol=8mA
Active
Power Supply Current
Idd
Idle
Power-Down
RST Pull-Down Resistor
Rrst VDD=5V
Pin Capacitance
Cio
Min.
4
Typ.
Max.
4
18
1.3
50
50
0.45
24
4.0
80
150
15
Unit
V
V
V
mA
mA
uA
Kohm
pF
5.4 AC Characteristics
at: Ta=0 to 70 oC, VDD=4.0V ~ 6.0V, VSS=0V
Name
Symbol
Condition
Crystal Frequency
fXtal
PWM DAC Frequency
fDA
fXtal=8MHz
PWM DAC Frequency
fDA
fXtal=12MHz
HS Input Pulse Width
tHIPW fXtal=8MHz
Min.
31.25
46.875
0.3
Typ.
8
Max.
31.62
47.43
12
Unit
MHz
KHz
KHz
uS
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VS Input Pulse Width
HS Input Pulse Width
VS Input Pulse Width
HSYNC to HBLANK Output Jitter
H+V to VBLANK Output Delay
H+V to VBLANK Output Delay
VS Pulse Width in H+V Signal
VS Pulse Width in H+V Signal
tVIPW
tHIPW
tVIPW
tHHBJ
tVVBD
tVVBD
tVCPW
tVCPW
fXtal=8MHz
fXtal=12MHz
fXtal=12MHz
3
0.2
2
US
US
US
NS
uS
uS
uS
uS
8
5
fXtal=8MHz
fXtal=12MHz
fXtal=8MHz
FXtal=12MHz
16
10
32
20
6.0 PACKAGE DIMENSION
6.1 40 pin PDIP 600 mil
52.197mm +/0.127
1.981m
m
+/-0.254
1.270mm +/0.254
0.457mm +/0.127
2.540m
m
15.494mm +/0.254
13.868mm +/0.102
1.778m
m
+/-0.127
0.254m
m
(min.)
3.81mm
+/-0.127
3.302m
m
+/-0.254
0.254m
m
+/-0.102
5o~7
0
6o +/o
16.256mm +/- 3
0.508
6.2 42 pin SDIP 600 mil
36.83mm +/-0.05
MTV 112A
1.981mm
+/-0.254
1.270mm +/-0.254
0.457mm +/-0.127
70TYP.
15.494mm +/-0.254
13.868mm +/-0.102
0.254mm
+/-0.102
1.778mm
+/-0.127
3.81mm
+/-0.127
0.254mm
(min.)
3.302mm
+/-0.254
5o~70
6o +/-3o
16.256mm +/-0.508
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6.3 44 pin PLCC Unit: inch
PIN #1 HOLE
0.045*450
0.180 MAX.
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005
0.610 +/-0.02
0.653 +/-0.003
0.500
70TYP.
0.010
0.050 TYP.
0.026~0.032 TYP.
0.070
0.070
0.653 +/-0.003
0.690 +/-0.005
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TECHNOLOGY
7.0 Ordering Information
Standard configurations:
Prefix
Part Type
MTV
112A
Package Type
N: PDIP
V: PLCC
Other Information
Part Numbers:
MTV 112A N -999
Prefix
Code Number
Part Type
Package Type
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