ETC MTV212AS32

MYSON
TECHNOLOGY
MTV212A32
(Rev. 1.2)
8051 Embedded Monitor Controller
Mask ROM Type
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
8051 core, 12MHz operating frequency.
512-byte RAM, 32K-byte program Mask-ROM.
Maximum 14 channels of 5V open-drain PWM DAC.
Maximum 31 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment
and programmable clamp pulse output.
Built-in self-test pattern generator with four free-running timings.
Built-in low power reset circuit.
Compliant with VESA DDC1/2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
3-channel 6-bit ADC.
Watchdog timer with programmable interval.
40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212A32 micro-controller is an 8051 CPU core embedded device specially tailored to Monitor
applications. It includes an 8051 CPU core, 512-byte SRAM, SYNC processor, 14 built-in PWM DACs,
VESA DDC interface, 3-channel A/D converter and a 32K-byte internal program Mask-ROM.
BLOCK DIAGRAM
P1.0-7
P2.0-2,P2.4-7
P3.0-2
8051
P3.4-5 CORE
P0.0-7
RD
WR
ALE
INT1
P0.0-7
RD
WR
ALE
INT1
XFR
AD0-2
ADC
H/VSYNC
CONTROL
RST
STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH
X1
X2
14 CHANNEL
PWM DAC
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.2
-1-
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
DEVICE SUMMARY
The MTV212A32 is one of the MTV212 family device. For other family devices information, please see the
table below:
Part Number
MTV212A16
MTV212A24
MTV212A32
MTV212A32U
MTV212A48U
MTV212A64U
USB
No
No
No
Yes
Yes
Yes
ROM
16K
24K
32K
32K
48K
64K
RAM
256
512
512
768
768
1024
Package
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
The usage of Auxiliary RAM (AUXRAM) is limited for targeted mask ROM, the allowable XBANK (35h) bank
selection is defined as the table below:
Part Number
MTV212A16
MTV212A24
RAM
256
512
MTV212A32
512
MTV212A32U
768
MTV212A48U
768
MTV212A64U
1024
Revision 1.2
Xbnk2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
-2-
Xbnk1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Xbnk0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
PIN CONNECTION
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
VSYNC
RST
VDD
NC
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
MTV212A32
44 Pin
PLCC
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.7/DA13
P2.6/DA12
P2.5/DA11
P2.4/DA10
HSCL/P3.0/Rxd
-3-
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
P1.6
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.6/DA12
P2.5/DA11
P2.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
P1.6
P1.5
DA2/P5.2
DA1/P5.1
Revision 1.2
MTV212A32
42 Pin
SDIP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P1.5
P1.4
P1.3
P1.2
P3.2/INT0
P1.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VSYNC
HSYNC
DA3/P5.3
DA4/P5.4
DA5/P5.5
DA8/HALFH
DA9/HALFV
HBLANK/P4.1
VBLANK/P4.0
DA7/HCLAMP
DA6/P5.6
P2.7/DA13
P2.6/DA12
P2.5/DA11
P2.4/DA10
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P2.0/AD0
P2.1/AD1
P1.7
28
27
26
25
24
23
22
21
20
19
18
DA2/P5.2
DA1/P5.1
DA0/P5.0
NC
NC
NC
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
MTV212A32
40 Pin
PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
41
42
43
44
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DA0/P5.0
NC
NC
NC
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
PIN DESCRIPTION
Name
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
Type
I/O
I/O
I/O
I
O
I
I/O
#
1
2
3
4
5
6
7
8
9
ISCL/P3.5/T1
I/O
10
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd
O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11
12
13
14
15
16
17
18
19
20
21
22
23
24
HSCL/P3.0/Rxd
I/O
25
P2.4/DA10
I/O
26
P2.5/DA11
I/O
27
P2.6/DA12
I/O
28
P2.7/DA13
I/O
29
DA6/P5.6
I/O
30
DA7/HCLAMP
VBLANK/P4.0
HBLANK/P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
O
O
O
O
O
I/O
31
32
33
34
35
36
DA4/P5.4
I/O
37
DA3/P5.3
I/O
38
I
I
39
40
HSYNC
VSYNC
Revision 1.2
Description
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
PWM DAC output (5V open drain) / General purpose I/O (5V open drain).
Active high reset.
Positive Power Supply.
Ground.
Oscillator output.
Oscillator input.
Master IIC data (5V open drain) / General purpose I/O (8051 standard) / T0 (8051
standard).
Master IIC clock (5V open drain) / General purpose I/O (8051 standard) / T1 (8051
standard).
Self-test video output (CMOS) / General purpose Output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / ADC Input.
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose Input / INT0.
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard).
General purpose I/O (Mask option as CMOS output or 8051 standard) / ADC Input.
General purpose I/O (Mask option as CMOS output or 8051 standard) / ADC Input.
Slave IIC data (5V open drain) / General purpose I/O (8051 standard) / Txd (8051
standard).
Slave IIC clock (5V open drain) / General purpose I/O (8051 standard) / Rxd (8051
standard).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
General purpose I/O (Mask option as CMOS output or 8051 standard) / PWM DAC
output (CMOS).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
PWM DAC output (CMOS) / Hsync clamp pulse output (CMOS).
Vertical blank (CMOS) / General purpose Output (CMOS).
Horizontal blank (CMOS) / General purpose Output (CMOS).
PWM DAC output (5V open drain) / vsync half freq. output (5V open drain).
PWM DAC output (5V open drain) / hsync half freq. output (5V open drain).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
PWM DAC output (CMOS) / General purpose I/O (Mask option as CMOS output or
open drain I/O).
Horizontal SYNC or Composite SYNC Input.
Vertical SYNC input.
-4-
2000/07/04
MYSON
TECHNOLOGY
MTV212A32
(Rev. 1.2)
PIN CONFIGURATION
A “CMOS output pin” means it can sink and drive at least 4mA current. It’s not recommended to use such pin
as input fuction.
A “5V open drain pin” means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used
as input or output function and need an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output low level, and
drive at least 4mA current for 160nS when output transit from low to high, then keep drive 100uA to maintain
the pin at high level. It can be used as input or output function. It need an external pull up resistor when drive
heavy load device.
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV212A32 includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within the
MTV212A32.
1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.
1.3 INT1 input pin is not provided, it is connected to special interrupt sources.
1.4 Port2 are shared with special function pins.
In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV212A32, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
divided into two banks, selected by XBANK register. Program can initialize Ri value and use "MOVX"
instruction to access the AUXRAM.
Revision 1.2
-5-
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
FFh
80h
7Fh
FFh
Internal RAM
SFR
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
Accessible by
direct addressing
AUXRAM
AUXRAM
Accessible by
indirect external
RAM addressing
(XBANK=0)(Using
MOVX A,@Ri
instruction)
Accessible by
indirect external
RAM addressing
(XBANK=1)(Using
MOVX A,@Ri
instruction)
80h
7Fh
Internal RAM
Accessible by
direct and indirect
addressing
XFR
Accessible by
indirect external
RAM addressing
(Using
MOVX A,@Ri
instruction
00h
00h
3. Chip Configuration
The Chip Configuration registers define the chip pins function, as well as the functional blocks' connection,
configuration and frequency.
Reg name
PADMOD
PADMOD
PADMOD
OPTION
OPTION
XBANK
addr
30h (w)
31h (w)
32h (w)
33h (w)
34h (w)
35h (r/w)
bit7
DA13E
HIICE
PWMF
bit6
DA12E
P56E
IIICE
DIV253
bit5
DA11E
P55E
HLFVE
FclkE
bit4
DA10E
P54E
HLFHE
IICpass
bit3
AD3E
P53E
HCLPE
ENSCL
bit2
AD2E
P52E
P42E
Msel
Xbnk2
bit1
bit0
AD1E
AD0E
P51E
P50E
P41E
P40E
MIICF1 MIICF0
SlvAbs1 SlvAbs0
Xbnk1
Xbnk0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)
DA13E = 1
→ pin “P2.7/DA13” is DA13.
=0
→ pin “P2.7/DA13” is P2.7.
DA12E = 1
→ pin “P2.6/DA12” is DA12.
=0
→ pin “P2.6/DA12” is P2.6.
DA11E = 1
→ pin “P2.5/DA11” is DA11.
=0
→ pin “P2.5/DA11” is P2.5.
DA10E = 1
→ pin “P2.4/DA10” is DA10.
=0
→ pin “P2.4/DA10” is P2.4.
AD3E = 1
→ no action
=0
→ no action
AD2E = 1
→ pin “P2.2/AD2” is AD2.
=0
→ pin “P2.2/AD2” is P2.2.
AD1E = 1
→ pin “P2.1/AD1” is AD1.
=0
→ pin “P2.1/AD1” is P2.1.
AD0E = 1
→ pin “P2.0/AD0” is AD0.
=0
→ pin “P2.0/AD0” is P2.0.
P56E = 1
→ pin “DA6/P5.6” is P5.6.
=0
→ pin “DA6/P5.6” is DA6.
P55E = 1
→ pin “DA5/P5.5” is P5.5.
=0
→ pin “DA5/P5.5” is DA5.
Revision 1.2
-6-
2000/07/04
MYSON
TECHNOLOGY
P54E
=1
=0
P53E = 1
=0
P52E = 1
=0
P51E = 1
=0
P50E = 1
=0
HIICE = 1
=0
IIICE = 1
=0
HLFVE = 1
=0
HLFHE = 1
=0
HCLPE = 1
=0
P42E = 1
=0
P41E = 1
=0
P40E = 1
=0
MTV212A32
(Rev. 1.2)
→ pin “DA4/P5.4” is P5.4.
→ pin “DA4/P5.4” is DA4.
→ pin “DA3/P5.3” is P5.3.
→ pin “DA3/P5.3” is DA3.
→ pin “DA2/P5.2” is P5.2.
→ pin “DA2/P5.2” is DA2.
→ pin “DA1/P5.1” is P5.1.
→ pin “DA1/P5.1” is DA1.
→ pin “DA0/P5.0” is P5.0.
→ pin “DA0/P5.0” is DA0.
→ pin “HSCL/P3.0/Rxd” is HSCL;
pin “HSDA/P3.1/Txd” is HSDA.
→ pin “HSCL/P3.0/Rxd” is P3.0/Rxd;
pin “HSDA/P3.1/Txd” is P3.1/Txd.
→ pin “ISDA/P3.4/T0” is ISDA;
pin “ISCL/P3.5/T1” is ISCL.
→ pin “ISDA/P3.4/T0” is P3.4/T0;
pin “ISCL/P3.5/T1” is P3.5/T1.
→ pin “DA9/HALFV” is VSYNC half frequency output.
→ pin “DA9/HALFV” is DA9.
→ pin “DA8/HALFH” is HSYNC half frequency output.
→ pin “DA8/HALFH” is DA8.
→ pin “DA7/HCLAMP” is HSYNC clamp pulse output.
→ pin “DA7/HCLAMP” is DA7.
→ pin “STOUT/P4.2” is P4.2.
→ pin “STOUT/P4.2” is STOUT.
→ pin “HBLANK/P4.1” is P4.1.
→ pin “HBLANK/P4.1” is HBLANK.
→ pin “VBLANK/P4.0” is P4.0.
→ pin “VBLANK/P4.0” is VBLANK.
OPTION (w) : Chip option configuration (All are "0" in Chip Reset).
PWMF = 1
→ select 94KHz PWM frequency.
=0
→ select 47KHz PWM frequency.
DIV253 = 1
→ PWM pulse width is 253 step resolution.
=0
→ PWM pulse width is 256 step resolution.
FclkE = 1
→ Double CPU clock Freq.
IICpass = 1
→ HSCL/HSDA pin bypass to ISCL/ISDA pin in DDC2 mode.
=0
→ Separate Master and Slave IIC block.
ENSCL = 1
→ Enable slave IIC block to hold HSCL pin low while MTV212A32 can't catch-up
the external master's speed.
Msel
=1
→ Master IIC block connect to HSCL/HSDA pins.
=0
→ Master IIC block connect to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 → select 400KHz Master IIC frequency.
= 1,0 → select 200KHz Master IIC frequency.
= 0,1 → select 50KHz Master IIC frequency.
= 0,0 → select 100KHz Master IIC frequency.
SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.
= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.
XBANK (r/w) : Auxiliary RAM bank switch.
Xbnk[2:0]
=0
→ Select AUXRAM bank 0.
=1
→ Select AUXRAM bank 1.
=2
→ Select AUXRAM bank 0.
=3
→ Select AUXRAM bank 1.
Revision 1.2
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MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
=4
=5
→ Select AUXRAM bank 0.
→ Select AUXRAM bank 1.
4. Extra I/O
The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.
Reg name
PORT4
PORT5
addr
38h (w)
39h (r/w)
bit7
bit6
bit5
bit4
bit3
P56
P55
P54
P53
PORT4 (w) :
Port 4 data output value.
PORT5 (r/w) :
Port 5 data input/output value.
bit2
P42
P52
bit1
P41
P51
bit0
P40
P50
5. PWM DAC
Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of
PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.
Reg name
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
addr
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
bit7
bit6
bit5
bit4
bit3
bit2
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8
Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13
bit1
bit0
DA0-13 (r/w) : The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency
function block treat any pulse shorter than one OSC period as noise.
Revision 1.2
-8-
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
Present
Check
Vpre
Polarity Check &
Freq. Count
Vfreq
Vpol
Digital Filter
Vbpl
VSYNC
XOR
CVSYNC
Vself
Present
Check
Digital Filter
Polarity Check &
Sync Seperator
Hpol
Present Check &
Freq. Count
Hpre
Hfreq
XOR
VBLANK
XOR
HBLANK
CVpre
Hbpl
Composite
Pulse Insert
XOR
HSYNC
Hself
H/V SYNC Processor Block Diagram
6.1 Composite SYNC separation/insertion
The MTV212A32 continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from
the input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV212A32 can also insert pulse to HBLANK output during composite VSYNC’s active time. The insert
pulse’s width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC.
6.2 H/V Frequency Counter
MTV212A32 can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits
Vcounter counts the time between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflow. Table 4.2.1 and table 4.2.2 shows the HCNT/VCNT value under the operations of
12MHz.
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MTV212A32
(Rev. 1.2)
6.2.1 H-Freq Table
H-Freq(KHZ)
1
2
3
4
5
6
7
8
9
10
11
12
31.5
37.5
43.3
46.9
53.7
60.0
68.7
75.0
80.0
85.9
93.8
106.3
Output Value (14 bits)
12MHz OSC (hex / dec)
0FDEh / 4062
0D54h / 3412
0B8Bh / 2955
0AA8h / 2728
094Fh / 2383
0854h / 2132
0746h / 1862
06AAh / 1706
063Fh / 1599
05D1h / 1489
0554h / 1364
04B3h / 1203
6.2.2 V-Freq Table
V-Freq(Hz)
1
2
3
4
5
6
56
60
70
72
75
85
Output value (12bits)
12MHz OSC (hex / dec)
45Ch / 1116
411h / 1041
37Ch / 892
364h / 868
341h / 833
2DFh / 735
6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is
set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when
the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. However, the
CVpre flag interrupt may be disabled when S/W disable the composite function.
6.4 H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
6.5 Output HBLANK/VBLANK Control and Polarity Adjust
The HBLANK is the mux output of HSYNC, composite Hpulse and self-test horizontal pattern. The VBLANK
is the mux output of VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity
are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz. The
HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
6.6 Self Test Pattern Generator
This generator can generate 4 display patterns for testing purpose, which are positive cross-hatch, negative
cross-hatch, full white, and full black (showed as following figure). The HBLANK output frequency of the
pattern can be chosen to 95.2KHz, 63.5KHz, 47.6KHz and 31.75KHz. The VBLANK output frequency of the
pattern is 72Hz or 60Hz. It is originally designed to support monitor manufacturer to do burn-in test, or offer
end-user a reference to check the monitor. The generator's output STOUT shares the output pin with P4.2.
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Display Region
Revision 1.2
Positive cross-hatch
Negative cross-hatch
Full white
Full black
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(Rev. 1.2)
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MTV212A32 Self-Test pattern timing
63.5KHz, 60Hz
47.6KHz, 60Hz
31.7KHz, 60Hz
time
H dots
time
H dots
time
H dots
Hor. Total time (A)
15.75us
1280
21.0us
1024
31.5us
640
Hor. Active time (D)
12.05us
979.3
16.07us
783.2
24.05us
488.6
Hor. F. P. (E)
0.2us
16.25
0.28us
12
0.45us
9
SYNC pulse width (B) 1.5us
122
2us
90
3us
61
Hor. B. P. (C)
2us
162.54
2.67us
110
4us
81.27
Vert. Total time (O)
Vert. Active time (R)
Vert. F. P. (S)
SYNC pulse width (P)
Vert. B. P. (Q)
time
16.66ms
15.65ms
0.063ms
0.063ms
0.882ms
V lines
1024
962
3.87
3.87
54.2
time
16.66ms
15.65ms
0.063ms
0.063ms
0.882ms
V lines
768
721.5
2.9
2.9
40.5
time
16.66ms
15.65ms
0.063ms
0.063ms
0.882ms
V lines
480
451
1.82
1.82
25.4
95.2KHz, 72Hz
time
H dots
10.5us
1600
8.03us
1224
0.14us
21
1.0us
152
1.33us
203
time
13.89ms
13.03ms
0.052ms
0.052ms
0.756ms
V lines
1200
1126
4.5
4.5
65
* 8 x 8 blocks of cross hatch pattern in display region.
6.7 HSYNC Clamp Pulse Output
The HCLAMP output is active by setting “HCLPE” control bit. The HCLAMP’s leading edge position, pulse
width and polarity is S/W controllable.
6.8 VSYNC Interrupt
The MTV212A32 check the VSYNC input pulse and generate an interrupt at its leading edge. The VSYNC
flag is set each time when MTV212A32 detects a VSYNC pulse. The flag is cleared by S/W writing a "0".
6.9 H/V SYNC Processor Register
Reg name
HVSTUS
HCNTH
HCNTL
VCNTH
Revision 1.2
addr
40h (r)
41h (r)
42h (r)
43h (r)
bit7
CVpre
Hovf
HF7
Vovf
bit6
HF6
bit5
Hpol
HF13
HF5
- 12 -
bit4
Vpol
HF12
HF4
bit3
Hpre
HF11
HF3
VF11
bit2
Vpre
HF10
HF2
VF10
bit1
Hoff
HF9
HF1
VF9
bit0
Voff
HF8
HF0
VF8
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VCNTL
HVCTR0
HVCTR2
HVCTR3
INTFLG
INTEN
MTV212A32
(Rev. 1.2)
44h (r)
VF7
VF6
VF5
VF4
VF3
VF2
40h (w)
C1
C0
NoHins
42h (w)
Selft
STF1
STF0
Rt1
43h (w)
CLPEG CLPPO CLPW2 CLPW1 CLPW0
48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg
VFchg
49h (w)
EHPR
EVPR
EHPL
EVPL
EHF
EVF
VF1
HBpl
Rt0
VF0
VBpl
STE
Vsync
EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1
→ The extracted CVSYNC is present.
=0
→ The extracted CVSYNC is not present.
Hpol
=1
→ HSYNC input is positive polarity.
=0
→ HSYNC input is negative polarity.
Vpol
=1
→ VSYNC (CVSYNC) is positive polarity.
=0
→ VSYNC (CVSYNC) is negative polarity.
Hpre = 1
→ HSYNC input is present.
=0
→ HSYNC input is not present.
Vpre
=1
→ VSYNC input is present.
=0
→ VSYNC input is not present.
Hoff* = 1
→ HSYNC input's off level is high.
=0
→ HSYNC input's off level is low.
Voff* = 1
→ VSYNC input's off level is high.
=0
→ VSYNC input's off level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) :
H-Freq counter's high bits.
Hovf
=1
→ H-Freq counter is overflow, this bit is clear by H/W when condition removed.
HF13 - HF8 : 6 high bits of H-Freq counter.
HCNTL (r) :
H-Freq counter's low byte.
VCNTH (r) :
V-Freq counter's high bits.
Vovf
=1
→ V-Freq counter is overflow, this bit is clear by H/W when condition removed.
VF11 - 8 :
4 high bits of V-Freq counter.
VCNTL (r) :
V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0.
C1, C0 = 1,1 → Select CVSYNC as the polarity, freq and VBLANK source.
= 1,0 → Select VSYNC as the polarity, freq and VBLANK source.
= 0,0 → Disable composite function.
= 0,1 → H/W auto switch to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1
→ HBLANK has no insert pulse in composite mode.
=0
→ HBLANK has insert pulse in composite mode.
HBpl = 1
→ negative polarity HBLANK output.
=0
→ positive polarity HBLANK output.
VBpl = 1
→ negative polarity VBLANK output.
=0
→ positive polarity VBLANK output.
HVCTR2 (w) : Self-test pattern generator control.
Selft
=1
→ enable generator.
=0
→ disable generator.
STF1,STF0
= 1,1 → 95.2KHz(horizontal)/72Hz(vertical) output selected.
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Rt1, Rt0= 0,0
= 0,1
= 1,0
= 1,1
STE
=1
=0
MTV212A32
(Rev. 1.2)
= 1,0 → 63.5KHz(horizontal)/60Hz(vertical) output selected.
= 0,1 → 47.6KHz(horizontal) /60Hz(vertical) output selected.
= 0,0 → 31.75KHz(horizontal) /60Hz(vertical) output selected.
→ positive cross-hatch pattern output.
→ negative cross-hatch pattern output.
→ full white pattern output.
→ full black pattern output.
→ enable STOUT output.
→ disable STOUT output.
HVCTR3 (w) : HSYNC clamp pulse control register.
CLPEG = 1
→ Clamp pulse follows HSYNC leading edge.
=0
→ Clamp pulse follows HSYNC trailing edge.
CLPPO = 1
→ Positive polarity clamp pulse output.
=0
→ Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] x 0.167 µs for 12MHz X’tal selection.
INTFLG (w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serve the interrupt routine.
HPRchg= 1
→ No action.
=0
→ Clear HSYNC presence change flag.
VPRchg= 1
→ No action.
=0
→ Clear VSYNC presence change flag.
HPLchg= 1
→ No action.
=0
→ Clear HSYNC polarity change flag.
VPLchg = 1
→ No action.
=0
→ Clear VSYNC polarity change flag.
HFchg = 1
→ No action.
=0
→ Clear HSYNC frequency change flag.
VFchg = 1
→ No action.
=0
→ Clear VSYNC frequency change flag.
Vsync = 1
→ No action.
=0
→ Clear VSYNC interrupt flag.
INTFLG (r) :
Interrupt flag.
HPRchg= 1
→ Indicates a HSYNC presence change.
VPRchg= 1
→ Indicates a VSYNC presence change.
HPLchg= 1
→ Indicates a HSYNC polarity change.
VPLchg = 1
→ Indicates a VSYNC polarity change.
HFchg = 1
→ Indicates a HSYNC frequency change or counter overflow.
VFchg = 1
→ Indicates a VSYNC frequency change or counter overflow.
Vsync = 1
→ Indicates a VSYNC interrupt.
INTEN (w) :
Interrupt enable.
EHPR = 1
→ Enable HSYNC presence change interrupt.
EVPR = 1
→ Enable VSYNC presence change interrupt.
EHPL = 1
→ Enable HSYNC polarity change interrupt.
EVPL = 1
→ Enable VSYNC polarity change interrupt.
EHF
=1
→ Enable HSYNC frequency change / counter overflow interrupt.
EVF
=1
→ Enable VSYNC frequency change / counter overflow interrupt.
EVsync = 1
→ Enable VSYNC interrupt.
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MTV212A32
(Rev. 1.2)
7. DDC & IIC Interface
7.1 DDC1 Mode
The MTV212A32 enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212A32. The
shift register fetch data byte from the DDC1 data buffer (DBUF) then send it in 9 bits packet formats which
includes a null bit (=1) as packet separator. The DBUF set the DbufI interrupt flag when the shift register
read out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the DbufI is set.
The DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The DbufI
interrupt can be mask or enable by EDbufI control bit.
7.2 DDC2B Mode
The MTV212A32 switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV212A32 enters DDC2B mode, S/W can set IICpass control bit to allow HOST access EEPROM directly.
Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. The other way to
perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM behavior. The
Slave A block's slave address can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W choose
5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2
LSB "xx" in XFR. This feature enables MTV212A32 to meet PC99 requirement.
The MTV212A32 will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it will
lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2
flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
7.3 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses MTV212A32 can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. If the matched address is slave A, MTV212A32 will save the matched address's 2 LSB bits to
SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then written to
RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address (slave
address is dropped). This block also generates a RCAI/RCBI (receive buffer full interrupt) every time when
the RCABUF/RCBBUF is loaded. If S/W can't read out the RCABUF/RCBBUF in time, the next byte in shift
register will not be written to RCABUF/RCBBUF and the slave block return NACK to the master. This feature
guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W that if the data in
RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is slave A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into shift register, result in TXABUF/TXBBUF empty and
generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte
for next transfer before shift register empty. Fail to do this will cause data corrupt. The TXAI/TXBI occurs
every time when shift register reads out the data from TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is
cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.4 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, select by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.
The software program can access the external IIC device through this interface. Since the EDID/VDIF data
and the display information share the common EEPROM, precaution must be taken to avoid bus conflicting
while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212A32 only. In DDC2 mode
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and IICpass flag is set, the host may access the EEPROM directly. Software can test the HSCL condition by
reading the Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the HSCL's rising
edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0, MTV212A32 will hold
HSCL low to isolate the host's access to EEPROM. A summary of master IIC access is illustrated as follows.
7.4.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212A32 transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.4.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212A32 transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV212A32 receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
* Please see the attachments about "Master IIC Receive Timing".
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
DBUF
addr
00h (r/w)
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w)
08h (r)
08h (w)
09h (w)
0Ah (w)
bit7
DDC2
WadrB
MAckIn
TXBI
ETXBI
ENSlvA
ENSlvB
bit6
bit5
bit4
WadrA
Hifreq
RCBI
bit3
bit2
MAckO
bit1
bit0
P
S
SlvAlsb1 SlvAlsb0
SlvRWB SAckIn
SLVS
Hbusy
SlvBMI
TXAI
RCAI
SlvAMI
DbufI
SlvBMI
SlvAMI
ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
DDC1 transmit data buffer
MbufI
MbufI
EMbufI
IICCTR (r/w) : IIC interface control register.
DDC2 = 1
→ MTV212A32 is in DDC2 mode, write "0" can clear it.
=0
→ MTV212A32 is in DDC1 mode.
MAckO = 1
→ In master receive mode, NACK is returned by MTV212A32.
=0
→ In master receive mode, ACK is returned by MTV212A32.
S, P
= ↑, 0 → Start condition when Master IIC is not during transfer.
= X, ↑ → Stop condition when Master IIC is not during transfer.
= 1, X → Will resume transfer after a read/write MBUF operation.
= X, 0 → Force HSCL low and occupy the master IIC bus.
* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.
IICSTUS (r) : IIC interface status register.
WadrB = 1
→ The data in RCBBUF is word address.
WadrA = 1
→ The data in RCABUF is word address.
SlvRWB = 1
→ Current transfer is slave transmit
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MTV212A32
(Rev. 1.2)
=0
→ Current transfer is slave receive
SAckIn = 1
→ The external IIC host respond NACK.
SLVS = 1
→ The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1
→ Master IIC bus error, no ACK received from the slave IIC device.
=0
→ ACK received from the slave IIC device.
Hifreq = 1
→ MTV212A32 has detected a higher than 200Hz clock on the VSYNC pin.
Hbusy = 1
→ Host drives the HSCL pin to low.
INTFLG (w) :
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
SlvBMI = 1
→ No action.
=0
→ Clear SlvBMI flag.
SlvAMI = 1
→ No action.
=0
→ Clear SlvAMI flag.
MbufI = 1
→ No action.
=0
→ Clear Master IIC bus interrupt flag (MbufI).
INTFLG (r) :
TXBI
RCBI
SlvBMI
TXAI
RCAI
SlvAMI
DbufI
MbufI
Interrupt flag.
=1
→ Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.
=1
→ Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.
=1
→ Indicates the slave IIC address B match condition.
=1
→ Indicates the TXABUF need a new data byte, clear by writing TXABUF.
=1
→ Indicates the RCABUF has received a new data byte, clear by reading RCABUF.
=1
→ Indicates the slave IIC address A match condition.
=1
→ Indicates the DDC1 data buffer need a new data byte, clear by writing DBUF.
=1
→ Indicates a byte is sent/received to/from the master IIC bus.
INTEN (w) :
Interrupt enable.
ETXBI = 1
→ Enable TXBBUF interrupt.
ERCBI = 1
→ Enable RCBBUF interrupt.
ESlvBMI = 1
→ Enable slave address B match interrupt.
ETXAI = 1
→ Enable TXABUF interrupt.
ERCAI = 1
→ Enable RCABUF interrupt.
ESlvAMI = 1
→ Enable slave address A match interrupt.
EDbufI = 1
→ Enable DDC1 data buffer interrupt.
EMbufI = 1
→ Enable Master IIC bus interrupt.
Mbuf (w) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV212A32's transmission to the IIC bus.
Mbuf (r) :
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV212A32's receiving from the IIC bus.
RCABUF (r) :
Slave IIC block A receive data buffer.
TXABUF (w) : Slave IIC block A transmit data buffer.
SLVAADR (w) : Slave IIC block A's enable and address.
ENslvA = 1
→ Enable slave IIC block A.
=0
→ Disable slave IIC block A.
bit6-0 :
Slave IIC address A to which the slave block should respond.
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RCBBUF (r) :
Slave IIC block B receive data buffer.
TXBBUF (w) : Slave IIC block B transmit data buffer.
SLVBADR (w) : Slave IIC block B's enable and address.
ENslvB = 1
→ Enable slave IIC block B.
=0
→ Disable slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 4.0V for a specific time, the LVR will generate a chip reset
signal. After the power supply is above 4.0V, LVR maintain in reset state for 144 Xtal cycle to guarantee the
chip exit reset condition with a stable X'tal oscillation.
The WatchDog Timer automatically generates a device reset when it is overflow. The interval of overflow is
0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer
function is disabled after power on reset, user can activate this function by setting WEN, and clear the timer
by set WCLR.
9. A/D converter
The MTV212A32 is equipped with three 6-bit A/D converters, S/W can select the current convert channel
by setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compare the
input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin
voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name
ADC
ADC
WDT
addr
10h (w)
10h (r)
18h (w)
bit7
ENADC
bit6
WEN
WCLR
bit5
bit4
bit3
bit2
bit1
SADC3 SADC2 SADC1
ADC convert Result
WDT2
WDT1
bit0
SADC0
WDT0
WDT (w) :
Watchdog Timer control register.
WEN
=1
→ Enable WatchDog Timer.
WCLR
=1
→ Clear WatchDog Timer.
WDT2: WDT0 = 0
→ overflow interval = 8 x 0.25 sec.
=1
→ overflow interval = 1 x 0.25 sec.
=2
→ overflow interval = 2 x 0.25 sec.
=3
→ overflow interval = 3 x 0.25 sec.
=4
→ overflow interval = 4 x 0.25 sec.
=5
→ overflow interval = 5 x 0.25 sec.
=6
→ overflow interval = 6 x 0.25 sec.
=7
→ overflow interval = 7 x 0.25 sec.
ADC (w) :
ADC control.
ENADC
=1
SADC0
=1
SADC1
=1
SADC2
=1
SADC3
=1
ADC (r) :
Revision 1.2
→ Enable ADC.
→ Select ADC0 pin input.
→ Select ADC1 pin input.
→ Select ADC2 pin input.
→ no action.
ADC convert result.
- 18 -
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
Memory Map of XFR
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
DBUF
ADC
ADC
WDT
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
PADMOD
PADMOD
PADMOD
OPTION
OPTION
XBANK
PORT4
PORT5
HVSTUS
HCNTH
HCNTL
VCNTH
VCNTL
HVCTR0
HVCTR2
HVCTR3
INTFLG
INTEN
Revision 1.2
addr
00h (r/w)
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w)
08h (r)
08h (w)
09h (w)
0Ah (w)
10h (w)
10h (r)
18h (w)
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
30h (w)
31h (w)
32h (w)
33h (w)
34h (w)
35h (r/w)
38h (w)
39h (r/w)
40h (r)
41h (r)
42h (r)
43h (r)
44h (r)
40h (w)
42h (w)
43h (w)
48h (r/w)
49h (w)
bit7
DDC2
WadrB
MAckIn
TXBI
ETXBI
ENSlvA
ENSlvB
ENADC
WEN
DA13E
HIICE
PWMF
bit6
bit4
bit3
bit2
MAckO
WadrA
Hifreq
RCBI
SlvRWB SAckIn
SLVS
Hbusy
SlvBMI
TXAI
RCAI
SlvAMI
SlvBMI
SlvAMI
ERCBI ESlvBMI ETXAI ERCAI ESlvAMI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
DDC1 transmit data buffer
SADC3 SADC2
ADC convert Result
WCLR
WDT2
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8
Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13
DA12E DA11E DA10E
AD3E
AD2E
P56E
P55E
P54E
P53E
P52E
IIICE
HLFVE HLFHE HCLPE
P42E
DIV253
FclkE IICpass ENSCL
Msel
P56
CVpre
Hovf
HF7
Vovf
VF7
C1
bit5
HF6
P55
Hpol
HF13
HF5
VF6
C0
P54
Vpol
HF12
HF4
P53
Hpre
HF11
HF3
VF11
VF3
Xbnk2
P42
P52
Vpre
HF10
HF2
VF10
VF2
VF5
VF4
NoHins
Selft
STF1
STF0
Rt1
CLPEG CLPPO CLPW2 CLPW1 CLPW0
HPRchg VPRchg HPLchg VPLchg HFchg
VFchg
EHPR
EVPR
EHPL
EVPL
EHF
EVF
- 19 -
bit1
bit0
P
S
SlvAlsb1 SlvAlsb0
DbufI
EDbufI
MbufI
MbufI
EMbufI
SADC1
SADC0
WDT1
WDT0
AD1E
AD0E
P51E
P50E
P41E
P40E
MIICF1 MIICF0
SlvAbs1 SlvAbs0
Xbnk1
Xbnk0
P41
P40
P51
P50
Hoff
Voff
HF9
HF8
HF1
HF0
VF9
VF8
VF1
VF0
HBpl
VBpl
Rt0
STE
Vsync
EVsync
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
ELECTRICAL PARAMETERS
1. Absolute Maximum Ratings
at: Ta= 0 to 70 oC, VSS=0V
Name
Maximum Supply Voltage
Maximum Input Voltage
Maximum Output Voltage
Maximum Operating Temperature
Maximum Storage Temperature
Symbol
VDD
Vin
Vout
Topg
Range
-0.3 to +6.0
-0.3 to VDD+0.3
-0.3 to VDD+0.3
0 to +70
Unit
V
V
V
oC
Tstg
-25 to +125
oC
2. Allowable Operating Conditions
at: Ta= 0 to 70 oC, VSS=0V
Name
Supply Voltage
Input "H" Voltage
Input "L" Voltage
Operating Freq.
Symbol
VDD
Vih1
Vil1
Fopg
Min.
4.5
0.4 x VDD
-0.3
-
Max.
5.5
VDD +0.3
0.2 x VDD
15
Unit
V
V
V
MHz
3. DC Characteristics
at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V
Name
Symbol
Output "H" Voltage, open drain pin
Voh1
Output "H" Voltage, 8051 I/O port pin
Voh2
Output "H" Voltage, CMOS output
Voh3
Output "L" Voltage
Vol
Power Supply Current
Idd
RST Pull-Down Resistor
Pin Capacitance
Rrst
Cio
Condition
Ioh=0uA
Ioh=-50uA
Ioh=-4mA
Iol=5mA
Active
Idle
Power-Down
VDD=5V
Min.
4
4
4
Condition
Min.
Typ.
18
1.3
50
150
Max.
0.45
24
4.0
80
250
15
Unit
V
V
V
V
mA
mA
uA
Kohm
pF
4. AC Characteristics
at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V
Name
Symbol
Crystal Frequency
fXtal
PWM DAC Frequency
fDA
HS input pulse Width
tHIPW
VS input pulse Width
tVIPW
HSYNC to Hblank output jitter
tHHBJ
H+V to Vblank output delay
tVVBD
VS pulse width in H+V signal
tVCPW
SDA to SCL set up time
tDCSU
SAD to SCL hold time
tDCH
Revision 1.2
fXtal=12MHz
fXtal=12MHz
fXtal=12MHz
Typ.
12
46.875
0.3
3
Max.
94.86
8
5
fXtal=12MHz
FXtal=12MHz
- 20 -
8
20
200
100
-
-
Unit
MHz
KHz
uS
uS
nS
uS
uS
ns
ns
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
SCL high time
SCL low time
START condition setup time
START condition hold time
STOP condition setup time
STOP condition hold time
tSCLH
tSCLL
tSU:STA
tHD:STA
tSU:STO
tHD:STO
t
500
500
500
500
500
500
-
-
ns
ns
ns
ns
ns
ns
SCKH
t
t
HD:STO
SCKL
t
SU:STA
t HD:STA
t DCSU
t DCH
tSU:STO
Data interface timing (I C)
2
Test Mode Condition
In normal application, users should avoid the MTV212A32 entering its test mode, outlined as follow:
Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0
Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & STO=1
PACKAGE DIMENSION
1. 40-pin PDIP 600 mil
52.197mm +/-0.127
1.981mm
+/-0.254
1.270mm +/-0.254
0.457mm +/-0.127
2.540mm
15.494mm +/-0.254
13.868mm +/-0.102
0.254mm
+/-0.102
1.778mm
+/-0.127
3.81mm
+/-0.127
0.254mm
(min.)
3.302mm
+/-0.254
5o~7 0
6o +/-3 o
16.256mm +/-0.508
Revision 1.2
- 21 -
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
2. 42 pin SDIP Unit: mm
Symbol
A
A1
B1
D
E1
F
eB
Dimension in mm
Min
3.937
1.78
0.914
36.78
13.945
15.19
15.24
0°
Nom
4.064
1.842
1.270
36.83
13.970
15.240
16.510
7.5°
Max
4.2
1.88
1.118
36.88
13.995
15.29
17.78
15°
15.494mm +/-0.254
13.868mm +/-0.102
0.254mm
+/-0.102
5o~70
6o +/-3o
16.256mm +/-0.508
3. 44 pin PLCC Unit:
PIN #1 HOLE
0.045*450
0.180 MAX.
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005
0.610 +/-0.02
0.653 +/-0.003
0.500
70TYP.
0.010
0.050 TYP.
0.026~0.032 TYP.
0.070
0.070
0.653 +/-0.003
0.690 +/-0.005
Revision 1.2
- 22 -
2000/07/04
MTV212A32
(Rev. 1.2)
MYSON
TECHNOLOGY
Ordering Information
Standard configurations:
Prefix
MTV
Part Numbers:
Prefix
MTV
MTV
MTV
Revision 1.2
Part Type
212A
Part Type
212A
212A
212A
Package Type
N: PDIP
S: SDIP
V: PLCC
ROM Size (K)
Package Type
N
S
V
ROM Size (K)
32
32
32
- 23 -
32
2000/07/04