NCP5604A, NCP5604B High Efficiency White LED Driver The NCP5604A and NCP5604B products are multiple output LED drivers dedicated to the display back light. The NCP5604A drives up to 4 LEDs, the NCP5604B version being dedicated to the three LED applications. The two parts share a common built−in DC/DC converter, based on a charge pump structure, including the new 1.33X mode of operation, improving the efficiency over the full input battery supply voltage span over 90%. http://onsemi.com MARKING DIAGRAM 16 1 WQFN16 (3x3) MT SUFFIX CASE 488AK Features 2.7 to 5.5 V Input Voltage Range Consistent 85% Efficiency 1.0 mA Quiescent Supply Current All Pins are Fully ESD Protected Built−in Short Circuit Protection Provides Four Independent LED Drives 200 kHz Digital Dimming Function Unloaded LED Protection Short Circuit Current Proof Tight 0.5% LED Current Matching These are Pb−Free Devices 1 NCPx 5604 ALYWG G NCPx5604 = Specific Device Code x = A or B A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) • Portable Back Light • Digital Cellular Phone Camera Photo Flash • LCD and Key Board Simultaneously Drive 16 15 14 13 C2P C2N Typical Applications C3P PIN CONNECTIONS C3N • • • • • • • • • • • ÇÇ ÇÇ Vbat 1 12 VOUT EN 2 11 C1P IREF 3 10 C1N 9 PGND 6 7 8 LED2 LED1 LED4/NC* 5 LED3 AGND 4 * Pin 5 in not connected in the NCP5604B (Top View) ORDERING INFORMATION Device *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 0 1 Package Shipping† NCP5604AMTR2G WQFN16 3000/Tape & Reel (Pb−Free) NCP5604BMTR2G WQFN16 3000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NCP5604/D NCP5604A, NCP5604B 220 nF/10 V Vbat C3 15 C2P C1N IREF 11 U1 NCP5604A 100 k GND C1P 10 C5 LED1 12 8 LED2 7 LED3 6 LED4 VOUT 5 4 AGND 9 PGND 13 1 mF/10 V 3 EN 14 220 nF/10 V R1 C2N 220 nF/10 V 2 CONTROL VBAT C2 1 C1 4.7 mF/6.3 V C3N GND C3P 16 C4 LWY87S D4 D3 LWY87S D2 LWY87S D1 LWY87S Figure 1. Typical Multiple White LED Driver http://onsemi.com 2 GND NCP5604A, NCP5604B 16 C3 C2 C1 220 nF 220 nF 220 nF 15 14 13 11 10 C5 GND 1 mF/10 V Vbat OVERVOLTAGE Q1 8 Q2 CURRENT CONTROL R1 GND 3 100 k AGND ANALOG CONTROL 4 Q3 Q4 OVERTEMPERATURE 7 6 5 9 Figure 2. NCP5604A Simplified Block Diagram http://onsemi.com 3 PGND D4 Vbat DIGITAL CONTROL D3 2 D1 EN LWY87S Vout LWY87S 12 LWY87S 4.7 mF/10 V CHARGE PUMP DC−DC CONVERTER D2 1 LWY87S C4 GND NCP5604A, NCP5604B 16 C3 C2 C1 220 nF 220 nF 220 nF 15 14 13 11 10 C5 GND 1 mF/10 V Vbat Vout OVERVOLTAGE Vbat DIGITAL CONTROL Q1 8 Q2 CURRENT CONTROL R1 GND 3 100 k AGND ANALOG CONTROL 4 Q3 7 6 NC 5 OVERTEMPERATURE 9 PGND Figure 3. NCP5604B Simplified Block Diagram (Pin 5 disconnected) http://onsemi.com 4 D3 2 D1 EN LWY87S 12 LWY87S 4.7 mF/10 V CHARGE PUMP DC−DC CONVERTER D2 1 LWY87S C4 GND NCP5604A, NCP5604B PIN FUNCTION DESCRIPTION Pin Symbol Type Description 1 VBAT INPUT, POWER Input Battery voltage to supply the analog and digital blocks. The pin must be decoupled to ground by a 1.0 mF ceramic capacitor. 2 EN INPUT, DIGITAL This pin carries the Enable function to control the DC−DC converter. It can be used to digitally dim the LED by using a PWM technique. EN = Low ³ shutdown mode, the DC−DC is disconnected from the load. EN = High ³ operating mode, the DC−DC is activated. The digital PWM dimming can operate over the 100 Hz − 200 kHz frequency, depending upon the application requirements. 3 IREF INPUT, ANALOG This pin provides the reference current, based on the internal bandgap voltage reference, to control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the LED biases. An external current source can be used to bias this pin to dim the light coming out of the LED. In no case shall the voltage at pin 3 be forced either higher or lower than the 600 mV provided by the internal reference. 4 AGND POWER This pin is the GROUND signal for the analog and digital blocks and must be connected to the system ground. 5 LED4 INPUT, POWER NCP5604A: This pin sinks to ground and monitors the current flowing into the fourth LED, intended to be used in backlight application. The current is limited to 25 mA maximum (Note 2). NCP5604B: This pin is not connected. 6 LED3 INPUT, POWER This pin sinks to ground and monitors the current flowing into the third LED, intended to be used in backlight application. The current is limited to 25 mA maximum (Note 2). 7 LED2 INPUT, POWER This pin sinks to ground and monitors the current flowing into the second LED, intended to be used in backlight application. The current is limited to 25mA maximum (Note 2). 8 LED1 INPUT, POWER This pin sinks to ground and monitors the current flowing into the first LED, intended to be used in backlight application. The current is limited to 25 mA maximum (Note 2). 9 PGND POWER This pin is the GROUND reference for the DC−DC converter and the output current control. The pin must be connected to the system ground, a ground plane being strongly recommended. 10 C1P POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N, pin 11 (Note 1). 11 C1N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P, pin 10 (Note 1). 12 VOUT OUTPUT, POWER This pin provides the output voltage supplied by the DC−DC converter. The Vout pin must be bypassed by 1.0 mF ceramic capacitor located as close as possible to the pin to properly bypass the output voltage to ground. The circuit shall not operate without such bypass capacitor properly connected to the Vout pin. The output voltage is internally clamped to 5.5 V in the event of no load situation. On the other hand, the output current is limited to 100 mA in the event of a short circuit to ground. 13 C2P POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2N, pin 14 (Note 1). 14 C2N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P, pin 13 (Note 1). 15 C3P POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C3N, pin 16 (Note 1). 16 C3N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C3P, pin 15 (Note 1). 1. Using low ESR 1.0 mF ceramic capacitor is mandatory to optimize the Charge Pump efficiency. The DC Bias effect must be taken into account when selecting the ceramic capacitor. Smallest foot print packages (size 0602 and lower) are prone to strong DC bias effect, reducing the real capacitance significantly. 2. Total DC−DC output current is limited to 100 mA. 3. The exposed flag shall be connected to ground. http://onsemi.com 5 NCP5604A, NCP5604B MAXIMUM RATINGS Symbol Value Unit Power Supply Rating VBAT 7.0 V Output Power Supply Vout 7.0 V Digital Input Voltage Digital Input Current EN −0.3 < V < VBAT 1.0 V mA ESD 2 200 kV V PD RqJA 320 125 mW °C/W Operating Ambient Temperature Range TA −40 to +85 °C Operating Junction Temperature Range TJ −40 to +125 °C Human Body Model: R = 1500 W, C = 100 pF (Note 4) Machine Model QFN16 Package Power Dissipation @ TA = +85°C (Note 5) Thermal Resistance, Junction−to−Air TJmax +150 °C Storage Temperature Range Tstg −65 to +150 °C Moisture Sensitivity Level (Note 7) MSL 1 Maximum Junction Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM): JESD22−A114. Machine Model (MM): JESD22−A115. 5. The maximum package power dissipation limit must not be exceeded. 6. Latchup current maximum rating: " 100 mA per JEDEC standard: JESD78. 7. Moisture Sensitivity Level (MSL): per IPC/JEDEC standard: J−STD−020A. http://onsemi.com 6 NCP5604A, NCP5604B POWER SUPPLY SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Pin Symbol 1 Vbat 12 Min Typ Max Unit Power Supply 2.7 − 5.5 V Iout Continuous DC Current in the Load (Note 8) @ Vf = 3.2 V, 3.3 V < Vbat < 5.5 V (Total Iout = 4*LED) 100 − − mA 12 Isch Continuous Output Short Circuit Current − 40 150 mA 12 Vout Output Voltage Compliance (OVP) 4.8 − 6.0 V 12 Tstart DC−DC Start Time (Cout = 1.0 mF) − from Vout = 0 V to full load operation, @ Vbat = nominal − 100 − ms Standby Current, @ Iout = 0 mA, EN = GND Vbat = 3.6 V Vbat = 4.2 V − − 0.3 0.4 3.0 5.0 Operating Current, @Iout = 0 mA, EN = H 2.85 V < Vbat < 5.5 V Vbat = 3.6 V − − 1.0 − − 1.5 Output LED to LED Current Matching, @ Vbat = 3.6 V, ILED = 20 mA, LED1 to LED4 are identical (Note 9) −2.0 "0.2 +2.0 Output Current Tolerance (Note 9) @ 3.2 V < Vbat < 4.2 V, ILED = 20 mA −5.0 "1.0 +5.0 0.85 1.0 1.15 MHz 1 1 5, 6, 7, 8 5, 6, 7, 8 Istdb Iop IMAT ITOL Rating mA mA % % − Fpwr Charge Pump Operating Frequency −25°C < TA < 85°C − TSD Thermal Shutdown Protection − 160 − °C − TSDH Thermal Shutdown Protection Hysteresis − 30 − °C − EPWR Efficiency (Note 9) LED1 to LED4 = 5.0 mA, Vf = 2.95 V (Total = 20 mA), Vbat = 3.2 V LED1 to LED4 = 25 mA, Vf = 3.3 V (Total = 100 mA), Vbat = 3.8 V − − 87 85 − − % 8. The total output current is evenly distributed across the external LED. 9. LED4 is not connected in the NCP5604B version. 10. The NCP5604B controls 75 mA in total in the three current mirrors, the extra 25 mA available current from the DC−DC converter being available for external purpose. http://onsemi.com 7 NCP5604A, NCP5604B ANALOG SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Pin Symbol 3 IREF 3 − Rating Min Typ Max Unit Reference Current @ Vref = 600 mV (Note 11) 1.0 − 100 mA VREF Reference Voltage (Note 12) −2% 600 +2% mV ILEDR Reference Current (IREF) to Output LED Current Ratio − 260 − − 11. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. 12. The external circuit must not force the IREF pin voltage either higher or lower than the 600 mV specified. DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Note: Digital inputs undershoot < − 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT. Pin Symbol 2 FPWM 2 2 Rating Min Typ Max Unit Input Enable PWM 0.1 − 200 kHz VIH Positive Going Input High Voltage Threshold, EN Signal 1.3 − VBAT V VIL Negative Going Input High Voltage Threshold, EN Signal 0 − 0.4 V APPLICATIONS INFORMATION DC−DC OPERATION The converter is based on a charge pump technique to generate a DC voltage capable to supply the White LED load The system regulates the current flowing into each LED by means of internal current mirrors associated with the white diodes. Consequently, the output voltage will be equal to the Vf of the LED, plus the 300 mV (typical) developed across the internal NMOS mirror. Typically, assuming a standard white LED forward biased at 10 mA, the output voltage will be 3.8 V. The third external capacitor makes possible the 1.33X extra mode of operation, with a significant efficiency improvement of the converter over the normal battery voltage span. The threshold levels have been defined to optimize this range of operating voltage, assuming a high efficiency is not relevant when the system is connected to a battery charger ( i.e. Vbat > 4.5 V). The built−in OVP circuit continuously monitor each output and stops the converter when the voltage is above 5.0 V. The converter resumes to normal operation when the voltage drops below 5.0 V (no latch−up mechanism). Consequently, the chip can operate with no load during any test procedures, but in the case of special applications, it is recommended to connect the non used LED driver either to a LED, or to the Vbat supply to minimize the internal losses (see LOAD CONNECTION paragraph). voltage is based on a temperature compensated Band Gap structure, a tight tolerance resistor will provide a very accurate load current. The resistor is calculated from the Ohm’s law (Rbias = Vref/I REF) and a more practical equation can be arranged to define the resistor value for a given output current: Rbias + (Vref * k)ńIout Rbias + (0.6 * 260)ńIout (eq. 1) Rbias + 156ńIout (eq. 2) Consequently, the resistor value will range between Rbias = 156/25 mA = 6240 W and Rbias = 156/0.5 mA = 312 kW. Obviously, the tolerance of such a resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance. VBandGap LED Return + − LOAD CURRENT CALCULATION The load current is derived from the 600 mV reference voltage provided by the internal Band Gap associated to the external resistor connected across IREF pin and Ground (see Figure 4). In any case, no voltage shall be forced at IREF pin, either downward or upward. The reference current is multiplied by the constant k = 260 to yield the output load current. Since the reference Pin 5 to 8 600mV IREF Pin 3 GND GND Note: The IREF pin must never be biased to voltage higher than 600 mV. Figure 4. Basic Reference Current Source http://onsemi.com 8 NCP5604A, NCP5604B LOAD CONNECTION The NCP5604A chip is capable of driving the four LED simultaneously, as depicted in Figure 1, but the load can be arranged to accommodate one or two LED if necessary in the application (see Figure 8). The four current mirror can be connected in parallel to drive a single powerful LED, thus yielding 100 mA current capability in a single LED. Iout drift versus Vbat 5 Iout = 28mA Iout = 80mA 4 Iout drift (%) 3 2 1 0 −1 12 −2 3.5 4.0 Vbat(V) 4.5 5.0 5.5 Figure 5. Typical IOUT Tolerance as a Function of the VBAT Supply Iref = 5 mA C5 8 GND 7 3 1 mF/6.3 V 3.0 NCP5604 −5 2.5 D1 −4 LWY87S −3 6 255C 0 2.5 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 1 mF/6.3 V LWY87S C5 GND 6 5 Iref = 100 mA 3 Iout Current Matching (%) 8 7 Figure 6. Typical LED to LED Current Matching at Low IREF Figure 8. Typical Single and Double LED Connections −405C 255C 2 The applications using three LED shall use the NCP5604B version to make profit of the highest efficiency (see Figure 9). In this case, LED4 is not connected and pin 5 is internally unconnected. 855C 1 0 2.5 D1 1 D2 12 855C LWY87S 2 NCP5604 Iout Current Matching (%) 5 −405C 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Figure 7. Typical LED to LED Current Matching at IREF Maximum http://onsemi.com 9 NCP5604A, NCP5604B VOUT 12 D1 C5 D2 D3 GND LWY87S GND GND PGND C1N The PWM frequency can be up to 200 kHz once the circuit has been properly started. On the other hand, with a 1% to 99% span, the circuit supports a large Duty Cycle to accommodate any range of dimming. The waveforms given in Figure 12 illustrate the NCP5604A behavior during the 50 kHz PWM operation. The same mechanism applies for the NCP5604B version. C5 5 mA LWY87S D6 220R R2 LWY87S D4 5 mA LWY87S LWY87S D3 D5 LWY87S D2 R1 LWY87S 1 mF/6.3 V D1 8 7 220R NCP5604 AGND Figure 11. Basic Digital PWM Dimming Control Finally, an external network can be connected across Vout and ground, but the current through such network will not be regulated by the NCP5604A chip (see Figure 10). On top of that, the total current out of the Vout pin shall be limited to 100 mA. 12 VOUT 4 9 Figure 9. Using the NCP5604B to Drive a Three LED Layout GND C1P C3N LWY87S LWY87S C3P IREF LED1 10 C2N LED2 C3P C1N C1 220 nF/10 V C2P EN LED3 5 3 11 VBAT 6.8 k PGND NC 9 2 PWM R1 4 C2 220 nF/10 V 1uF/10V 100k U1 C2P IREF NCP5604B C1P AGND 13 LED1 3 14 8 EN 15 16 2 R1 C2N C3N VBAT LED2 1 LED3 GND C3 7 CONTROL 1 6 C4 GND 4.7uF/6.3V Input PWM Signal Frequency: 100 Hz to 200 kHz 220 nF/10 V LED4 Vbat 6 5 GND Figure 10. Extra Load Connected to Vout Figure 12. PWM Modulation Span: 1% to 99% DIMMING The dimming can be achieved by two means: • Use a digital PWM signal to control the EN pin • Use an analog signal to control the reference current IREF pin. The digital PWM is straightforward, yielding a zero to 100% duty cycle, but the output current is pulsed since the system is continuously switched ON/OFF. There is no need for extra passive component, the clock being provided by an I/O port from the MCU (see Figure 11). Besides the popular PWM mode, a simple analog technique can be built with two extra components (one resistor + one NMOS), the net advantage being a continuous output current once the operating point has been stabilized (see Figure 13). The absolute output current tolerance depends upon the precision of the two external resistors, the RDS(on) of the NMOS being negligible in front of the resistor value. The example given, Figure 13 yields a 1.0 mA output current when Q1 is OFF, http://onsemi.com 10 VBAT 2 ENABLE C3P 150 k R1 6.8 k R2 C2N IREF C3N VOUT 4 VBAT C1N C1P C2P C2N EN C3P IREF V = 3.3 V C3N VOUT GND GND Figure 14. Basic Analog PWM Dimming Control http://onsemi.com 11 LED1 LED2 8 GND 7 PGND LED3 AGND LED4 9 Q1B Q1A 10 nF C1 BC846BDW 6 4 5 15 k LED1 LED2 8 Figure 13. Basic Analog Dimming Control 3 12 k LED3 GND 2 PWM 7 5 High Out 6 PGND Q1 LED4 AGND 9 ENABLE R2 C2P EN 3 1 R1 C1N 1 and 23 mA when Q1 is ON. The concept can use either a DC drive or a pulsed mode to dynamically dim the light out of the LED. A different analog approach, but more complex solution, can be derived from either a DC or a pulsed voltage associated with a current mirror built with low cost discrete devices (see Figure 14). The associated filter (R2/R3/C1) provides a continuous voltage to the current mirror, thus a digitally controlled continuous output current. Generally speaking, the PWM frequency could be either in the low end 20 Hz to 200 Hz band, or above the audio band (25 kHz and beyond) to make sure the dimming can be adjusted from zero to 100% without any audible noise. As a matter of fact, the NCP5604A has been designed to guarantee 200 kHz PWM at the ENABLE pin. The current mirror can be largely improved by using an external operational amplifier to get a very stable and temperature independent current, but such a solution could turn out to be too expensive and, generally speaking, the basic structure given, Figure 13, gives good results since the current depends mostly upon the quality of resistor R2. C1P NCP5604A, NCP5604B NCP5604A, NCP5604B Figure 15. Startup Operation Figure 17. Input Current Short Circuit Operation SHORT CIRCUIT OPERATION The circuit is designed to support a short circuit across Vout and Ground without damage. When a short occurs, the pulsed output current increases to the maximum peak value until the output voltage drops below 1 V. At this point, the pulsed current is limited to 40 mA average (typical), until the short is removed. The waveforms given in Figure 16 illustrate the functional operation. Similarly, the input current is limited 300 mA peak (typical) as depicted in Figure 17. Iout=100 mA Iout=80 mA Iout=60 mA Iout=40 mA Iout=20 mA 90 85 EFFPLED (%) 80 75 70 65 60 55 50 4.2 4.0 3.8 3.6 Vbat(V) Figure 18. Typical Efficiency Figure 16. Output Short Circuit Operation http://onsemi.com 12 3.4 3.2 NCP5604A, NCP5604B TP2 GND GND R1 GND 330 k BSS138 R2 100 nF GND TP1 VREF GND VCC GND S2 ENABLE VCC LWY87S D3 PGND 5 9 4 IREF EN 3 2 1 AGND LED4 C8 C3N 6 D1 LED3 8 7 D2 LED2 U1 NCP5604 D4 12 10 C1P C1N VOUT LED1 C3P VBAT 16 11 13 C2P C2N 15 6.8 k Q1 Q C 12 A 11 B 13 CLR 15 14 RC Q U3B MC14538B CLR 3 A B 4 5 9 10 7 Q Q 2 C GND 4.7 mF/6.3 V 1 C5 RC U3A MC14538B 6 GND GND C9 R6 VCC S1 1 U2A R3 VCC 100 k Figure 19. Demo Board Schematic Diagram http://onsemi.com 13 PWM 6 100 k VCC NL27WZ14 R4 CNT/PWM 3 U2B 1.5 k R7 VCC GND D5 Adjust PWM 4 22 nF P1 100 kA NL27WZ14 R5 − 10 k C6 10 k 100 nF 4 + GND GND 2.2 mF/6.3 V 2*1.5 V PK1 + + C7 GND 2 1 S1 POWER 3 C3 220 nF/10 V 14 GND 4.7 mF/10 V LWY87S C1 VOUT Z3 GND GROUND C2 C4 LWY87S 220 nF/10 V LWY87S 220 nF/10 V NCP5604A, NCP5604B Figure 20. Silk View Top Layer Figure 21. Demo Board Printed Circuit Layout http://onsemi.com 14 NCP5604A, NCP5604B PACKAGE DIMENSIONS WQFN16 MT SUFFIX CASE 488AK−01 ISSUE O D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM SPACING BETWEEN LEAD TIP AND FLAG. A B ÇÇÇ ÇÇÇ PIN 1 LOCATION E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 SEATING PLANE A1 C D2 16X e L 5 NOTE 5 EXPOSED PAD 8 4 9 E2 16X K 12 1 16 16X 0.10 C A B 0.05 C 13 b BOTTOM VIEW NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 15 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP5604/D