NM24C02U/NM24C03U 2K-Bit Serial EEPROM 2-Wire Bus Interface General Description Functions The NM24C02U/NM24C03U are 2K (2,048) bit serial interface CMOS EEPROMs (Electrically Erasable Programmable ReadOnly Memory). These devices fully conform to the Standard I2C™ 2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the EEPROM device). In addition, the serial interface allows a minimal pin count packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. ■ I2C™ compatible interface ■ 2,048 bits organized as 256 x 8 ■ Extended 2.7V – 5.5V operating voltage ■ 100 KHz or 400 KHz operation ■ Self timed programming cycle (6ms typical) ■ "Programming complete" indicated by ACK polling ■ NM24C03U: Memory "Upper Block" Write Protect pin Features NM24C03U incorporates a hardware "Write Protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the WP pin to VCC. This section of memory then effectively becomes a ROM (Read-Only Memory) and can no longer be programmed as long as WP pin is connected to VCC. ■ The I2C™ interface allows the smallest I/O pincount of any EEPROM interface ■ 16 byte page write mode to minimize total write time per byte ■ Typical 200µA active current (ICCA) ■ Typical 1µA standby current (ISB) for "L" devices and 0.1µA standby current for "LZ" devices Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. ■ Endurance: Up to 1,000,000 data changes ■ Data retention greater than 40 years Block Diagram VCC VSS WP H.V. GENERATION TIMING &CONTROL START STOP LOGIC SDA CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR SCL XDEC A2 A1 A0 E2PROM ARRAY WORD ADDRESS COUNTER R/W YDEC CK DATA REGISTER DIN DOUT DS800007-1 I2C™ is a registered trademark of Philips Electronics N.V. © 1998 Fairchild Semiconductor Corporation NM24C02U/NM24C03U Rev. B.1 1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface August 1999 NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Connection Diagrams Dual-in-Line Package (N), SO Package (M8), and TSSOP Package (MT8) A0 1 8 VCC A1 2 7 NC A2 3 6 SCL VSS 4 5 SDA NM24C02U DS800007-2 Top View See Package Number N08E, M08A, and MTC08 Pin Names A0,A1,A2 Device Address Inputs VSS Ground SDA Serial Data I/O SCL Serial Clock Input NC No Connection VCC Power Supply Dual-in-Line Package (N), SO Package (M8), and TSSOP Package (MT8) A0 1 A1 2 A2 3 VSS 4 NM24C03U 8 VCC 7 WP 6 SCL 5 SDA DS800007-3 Top View See Package Number N08E, M08A, and MTC08 Pin Names A0,A1,A2 Device Address Inputs VSS Ground SDA Serial Data I/O SCL Serial Clock input WP Write Protect VCC Power Supply 2 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM 24 C XX U F LZ E XX Letter Description N M8 MT8 8-pin DIP 8-pin SOIC 8-pin TSSOP Temp. Range None V E 0 to 70°C -40 to +125°C -40 to +85°C Voltage Operating Range Blank L LZ 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1µA Standby Current SCL Clock Frequency Blank F 100KHz 400KHz Ultralite CS100UL Process 02 03 2K 2K with Write Protect C W CMOS Technology Total Array Write Protect 24 IIC NM Fairchild Non-Volatile Memory Package Density Interface 3 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Ordering Information Operating Conditions Absolute Maximum Ratings Ambient Storage Temperature Ambient Operating Temperature NM24C02U/03U NM24C02UE/03UE NM24C02UV/03UV –65°C to +150°C All Input or Output Voltages with Respect to Ground 6.5V to –0.3V Lead Temperature (Soldering, 10 seconds) +300°C ESD Rating 0°C to +70°C -40°C to +85°C -40°C to +125°C Positive Power Supply NM24C02U/03U NM24C02UL/03UL NM24C02ULZ/03ULZ 2000V min. 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V Standard VCC (4.5V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Min Limits Typ (Note 1) Max Units 0.2 1.0 ICCA Active Power Supply Current fSCL = 400 KHz fSCL = 100 KHz ISB Standby Current VIN = GND or VCC 10 50 µA ILI Input Leakage Current VIN = GND to VCC 0.1 1 µA ILO Output Leakage Current VOUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V IOL = 3 mA mA Low VCC (2.7V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Min Limits Typ (Note 1) Max Units ICCA Active Power Supply Current fSCL = 400 KHz fSCL = 100 KHz 0.2 1.0 mA ISB Standby Current VIN = GND or VCC 1 0.1 10 10 1 50 µA µA µA ILI Input Leakage Current VIN = GND to VCC 0.1 1 µA VOUT = GND to VCC VCC = 2.7V - 4.5V VCC = 2.7V - 4.5V VCC = 4.5V - 5.5V ILO Output Leakage Current 1 µA VIL Input Low Voltage –0.3 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V 0.1 IOL = 3 mA Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2) Symbol Test Conditions Max Units CI/O Input/Output Capacitance (SDA) VI/O = 0V 8 pF CIN Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF Note 1: Typical values are TA = 25°C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested. 4 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Product Specifications Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels VCC x 0.5 Output Load 1 TTL Gate and CL = 100 pF Read and Write Cycle Limits (Standard and Low VCC Range) Symbol fSCL TI Parameter 100 KHz Min Max 400 KHz Min Max Units SCL Clock Frequency 100 400 KHz Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) 100 50 ns 0.9 µs tAA SCL Low to SDA Data Out Valid 0.3 tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 1.3 µs Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 0.6 µs tHD:DAT Data in Hold Time 0 0 µs tSU:DAT Data in Setup Time 250 100 ns tHD:STA tR SDA and SCL Rise Time tF SDA and SCL Fall Time tSU:STO tDH tWR (Note 3) 3.5 0.1 1 300 0.3 µs 300 ns Stop Condition Setup Time 4.7 0.6 µs Data Out Hold Time 300 50 ns Write Cycle Time - NM24C02U/03U - NM24C02U/03UL, NM24C02U/03ULZ 10 15 10 15 ms Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24C02U/03U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. 5 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface AC Conditions of Test tR tF tHIGH tLOW tLOW SCL ;; tSU:STA tHD:STA SDA tHD:DAT tSU:DAT tSU:STO IN tBUF tAA tDH SDA OUT DS800007-8 System Layout Typical System Configuration VCC VCC SDA SCL Master Transmitter/ Receiver Note: Slave Transmitter/ Receiver Slave Receiver Master Transmitter Master Transmitter/ Receiver DS800007-20 Due to open drain configuration of SDA, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ) Example of 16K of Memory on 2-Wire Bus Note: VCC The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices. The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state. It is recommended that the total line capacitance be less than 400pF VCC SDA SCL VCC VCC VCC NM24C02U/03U NM24C02U/03U A0 A1 A2 VSS A0 A1 A2 VSS To VCC or VSS VCC NM24C04U/05U A1 A2 VSS To VCC or VSS To VCC or VSS NM24C08U/09U A2 VSS To VCC or VSS DS800007-9 Device NM24C02U/03U A0 Address Pins A1 A2 ADR ADR ADR 6 NM24C02U/NM24C03U Rev. B.1 Memory Size # of Page Blocks 2048 Bits 1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Bus Timing Pin Descriptions Device address pins A0, A1, and A2 are connected to VCC or VSS to configure the EEPROM chip address. Table I shows the active pins. Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Table 1. Device A0 A1 NM24C02U/03U ADR * ADR Max # of devices on bus A2 Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire–ORed with any number of open drain or open collector outputs. Effects of Addresses ADR 23 = 8; 8*x (1x2K)** = 16K ** Number of page blocks per density WP Write Protection (NM24C03U Only) Under the Standard IIC protocol, the maximum density addressable using the three pin configuration of the IIC protocol is 16K. Any combination of densities can be used up to this limit. If tied to VCC, PROGRAM operations onto the upper half of the memory will not be executed. READ operations are possible. If tied to VSS, normal operation is enabled, READ/WRITE over the entire memory is possible. Background Information (IIC Bus) As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition. This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. Device Operation • Hardware configuring the A0, A1, and A2 pins (Device Address pins) with pull-up or pull-down to VCC or VSS. All unused pins must be grounded (tied to VSS). • Software addressing the required PAGE BLOCK within the device memory array (as sent in the Slave Address string). For devices with densities greater than 16K, a different protocol, the Extended IIC protocol, is used. Refer to NM24C32U datasheet (for example) for additional details. The NM24C02U/03U supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM24C02U/03U will be considered a slave in all applications. Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]–[DEVICE ADDRESS]–[PAGE BLOCK ADDRESS]–[BYTE ADDRESS] Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3 on next page. DEFINITIONS WORD 8 bits (byte) of data PAGE 16 sequential addresses (one byte each) that may be programmed during a 'Page Write' programming cycle PAGE BLOCK 2048 (2K) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits MASTER Any IIC device CONTROLLING the transfer of data (such as a microprocessor) SLAVE Device being controlled (EEPROMs are always considered Slaves) TRANSMITTER RECEIVER Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM24C02U/03U continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Stop Condition All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C02U/03U to place the device in the standby power mode. Write Cycle Timing Acknowledge Acknowledge is a hardware convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. Device currently SENDING data on the bus (may be either a Master or Slave). During the ninth clock cycle the receiver will pull the SDA line to LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. Device currently RECEIVING data on the bus (Master or Slave) 7 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Device Operation Inputs (A0, A1, A2) SCL SDA 8th BIT ACK WORD n tWR STOP CONDITION Note: START CONDITION DS800007-10 The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. Data Validity (Figure 2) SCL SDA DATA STABLE DATA CHANGE DS800007-11 Start and Stop Definition (Figure 3) SCL SDA START CONDITION STOP CONDITION DS800007-12 Acknowledge Response from Receiver (Figure 4) SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 8 NM24C02U/NM24C03U Rev. B.1 DS800007-13 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Write Cycle Timing (Figure 1) Refer to the following table for Slave Addresses string details: Device The NM24C02U/03U device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the NM24C02U/03U will respond with an acknowledge after the receipt of each subsequent eight bit byte. NM24C02U/03U 1 (None) A simple review: After the NM24C02U/03U recognizes the start condition, the devices interfaced to the IIC bus wait for a slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge signal and awaits further transmissions. Slave Addresses (Figure 5) 1 A The last bit of the slave address defines whether a write or read condition is requested by the master. A '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier (see Figure 5). This is fixed as 1010 for all EEPROM devices. 0 A All IIC EEPROMs use an internal protocol that defines a PAGE BLOCK size of 2K bits (for Word addressess 0000 through 1111). Therefore, address bits A0, A1, or A2 (if designated 'P') are used to access a PAGE BLOCK in conjunction with the Word address used to access any individual data byte (Word). Device Addressing 1 A Page Block Addresses A: Refers to a hardware configured Device Address pin. In the read mode the NM24C02U/03U slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. Device Type Identifier A0 A1 A2 Page Blocks Device Address 0 A2 A1 A0 R/W (LSB) NM24C02U/03U DS800007-14 9 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Write Cycle Timing (Continued) Once the stop condition is issued to indicate the end of the host’s write operation the NM24C02U/03U initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C02U/03U is still busy with the write operation no ACK will be returned. If the NM24C02U/03U has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. BYTE WRITE For a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. Upon receipt of the byte address the NM24C02U/03U responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24C02U/03U begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the NM24C02U/03U inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Write Protection (NM24C03U Only) Programming of the upper half of the memory will not take place if the WP pin of the NM24C03U is connected to VCC. The NM24C03U will accept slave and byte addresses; but if the memory accessed is write protected by the WP pin, the NM24C03U will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. PAGE WRITE The NM24C02U/03U is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. After the receipt of each byte, the NM24C02U/03U will respond with an acknowledge. After the receipt of each byte, the internal address counter increments to the next address and the next SDA data is accepted. If the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 7 for the address, acknowledge, and data transfer sequence. Byte Write (Figure 6) Bus Activity: Master S T A R T SLAVE ADDRESS WORD ADDRESS S T O P DATA SDA Line A C K Bus Activity: NM24C02U/03U A C K A C K DS800007-15 Page Write (Figure 7) Bus Activity: Master S T A R T SLAVE ADDRESS WORD ADDRESS (n) DATA n DATA n + 1 S T O P DATA n + 15 SDA Line Bus Activity: NM24C02U/03U A C K A C K A C K A C K DS800007-16 10 NM24C02U/NM24C03U Rev. B.1 A C K www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Acknowledge Polling Write Operations Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read. start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the NM24C02U/03U and then by the eight bit data. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM24C02U/03U discontinues transmission. Refer to Figure 9 for the address, acknowledge and data transfer sequence. Current Address Read Sequential Read Internally the NM24C02U/03U contains an address counter that maintains the address of the last byte accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the NM24C02U/03U issues an acknowledge and transmits the eight bit byte. The master will not acknowledge the transfer but does generate a stop condition, and therefore the NM24C02U/ 03U discontinues transmission. Refer to Figure 8 for the sequence of address, acknowledge and data transfer. Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The NM24C02U/03U continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" and the NM24C02U/03U continues to output data for each acknowledge received. Refer to Figure 10 for the address, acknowledge, and data transfer sequence. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition, slave address and then the byte address it is to read. After the byte address acknowledge, the master immediately reissues the Current Address Read (Figure 8) Bus Activity: Master S T A R T S T O P SLAVE ADDRESS SDA Line A C K Bus Activity: NM24C02U/03U DATA NO A C K DS800007-17 Random Read (Figure 9) Bus Activity: Master S T A R T SLAVE ADDRESS S T A R T WORD ADDRESS S T O P SLAVE ADDRESS SDA Line A C K Bus Activity: NM24C02U/03U A C K A C K DATA n NO A C K DS800007-18 Sequential Read (Figure 10) Bus Activity: Master A C K Slave Address S T O P A C K A C K SDA Line Bus Activity: NM24C02U/03U A C K DATA n +1 DATA n +1 DATA n + 2 DATA n + x NO A C K DS800007-19 11 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Read Operations NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Physical Dimensions inches (millimeters) unless otherwise noted 0.189 - 0.197 (4.800 - 5.004) 8 7 6 5 0.228 - 0.244 (5.791 - 6.198) 1 2 3 4 Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 0.010 - 0.020 x 45° (0.254 - 0.508) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 8° Max, Typ. All leads 0.053 - 0.069 (1.346 - 1.753) 0.004 - 0.010 (0.102 - 0.254) Seating Plane 0.04 (0.102) All lead tips 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 0.014 - 0.020 Typ. (0.356 - 0.508) 0.050 (1.270) Typ 8-Pin Molded Small Outline Package (M8) Package Number M08A 0.114 - 0.122 (2.90 - 3.10) 8 5 (4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) 0.246 - 0.256 (6.25 - 6.5) (1.78) Typ (0.42) Typ 0.123 - 0.128 (3.13 - 3.30) (0.65) Typ 1 Land pattern recommendation 4 Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. 0.0035 - 0.0079 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0098 (0.19 - 0.30) Gage plane 0°-8° DETAIL A Typ. Scale: 40X 0.020 - 0.028 (0.50 - 0.70) Seating plane 0.0075 - 0.0098 (0.19 - 0.25) Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 8-Pin Molded Thin Shrink Small Outline Package Package Number MTC08 12 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 8 0.092 DIA (2.337) 7 6 0.250 - 0.005 + Pin #1 IDENT 8 0.032 ± 0.005 (6.35 ± 0.127) Pin #1 IDENT 1 Option 1 1 0.280 MIN (7.112) 2 3 0.040 Typ. (1.016) 0.300 - 0.320 (7.62 - 8.128) 7 (0.813 ± 0.127) RAD 5 0.030 MAX (0.762) 20° ± 1° 4 Option 2 0.145 - 0.200 0.039 (0.991) (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 95° ± 5° 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM 0.125 - 0.140 (3.175 - 3.556) 0.065 (1.651) 90° ± 4° Typ 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 0.045 ± 0.015 (1.143 ± 0.381) 0.020 (0.508) Min 0.060 (1.524) 0.050 (1.270) Molded Dual-In-Line Package (N) Package Number N08E Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 13 NM24C02U/NM24C03U Rev. B.1 www.fairchildsemi.com NM24C02U/NM24C03U – 2K-Bit Serial EEPROM 2-Wire Bus Interface Physical Dimensions inches (millimeters) unless otherwise noted