NAINA NT5TU128M8GE-AC

NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Feature
CAS Latency Frequency
-3C/-3CI
-AC/-ACI
-BD
(DDR2-667-CL5)
(DDR2-800-CL5)
(DDR2-1066-CL6)
Speed Bins
Units
min
max
min
max
min
max
tCK(Avg.)
Clock Frequency
125
333
125
400
125
533
MHz
tRCD
15
-
12.5
-
11.25
-
ns
tRP
15
-
12.5
-
11.25
-
ns
tRC
60
-
57.5
-
56.25
-
ns
tRAS
45
70K
45
70K
45
70K
tCK(Avg.)@CL3
5
8
5
8
5
8
tCK(Avg.)@CL4
3.75
8
3.75
8
3.75
tCK(Avg.)@CL5
3
8
2.5
8
tCK(Avg.)@CL6
-
-
-
-
tCK(Avg.)@CL7
-
-
-

8 internal memory banks

Programmable CAS Latency:
，

司
限
6 (-BD)
81
51
44
71
：
QQ
8
ns
1.875
8
ns
8
ns
Support Industrial grade temperature -40℃~95℃
Operating t Temperature (-3CI/-ACI)
1KB page size for x4 and x8
2KB page size for x16
公
3, 4, 5 (DDR2--3C/-AC)
2.5
85
，

ns
ns
43
41
5
1.8V ± 0.1V Power Supply Voltage
ns
8
1.875
18
66

-
9
Parameter

Strong and Weak Strength Data-Output Driver
Programmable Additive Latency: 0, 1, 2, 3, 4 5

Auto-Refresh and Self-Refresh

Write Latency = Read Latency -1

Power Saving Power-Down modes

Programmable Burst Length:

7.8 µs max. Average Periodic Refresh Interval

4 and 8 Programmable Sequential / Interleave Burst

RoHS Compliance

OCD (Off-Chip Driver Impedance Adjustment)

Packages:

ODT (On-Die Termination)

60-Ball BGA for x4 / x8 components


84-Ball BGA for x16 components
4 bit prefetch architecture

Data-Strobes: Bidirectional, Differential
深
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有

1
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Description
The 1giga bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM
containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8 bank, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These
synchronous devices achieve high speed double-data-rate transfer rates of up to 800 Mb/sec/pin for general appli-
81
9
cations.
51
The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
ODT (On-Die Termination) function.
71
adjustment and (5) an
44
latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance
：
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are
QQ
latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended
85
，
DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x4/x8 organized components
43
41
5
and A 13 bit address bus for x16 component is used to convey row, column, and bank address devices.
深
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技
有
限
公
司
，
18
66
These devices operate with a single 1.8V ± 0.1V power supply and are available in BGA packages.
2
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration –
60 balls BGA Package (x4)
< TOP View>
See the balls through the package
X4
2
3
7
8
9
VDD
NC
VSS
A
VSSQ
DQS
VDDQ
NC6
VSSQ
DM
B
DQS
VSSQ
NC
VDDQ
DQ1
VDDQ
C
VDDQ
DQ0
VDDQ
NC
VSSQ
DQ3
D
DQ2
VSSQ
VDDL
VREF
VSS
E
VSSDL
CK
CKE
WE
F
RAS
BA0
BA 1
G
CAS
A10/ AP
A1
H
A3
A5
J
A7
A9
A12
NC
51
44
71
：
QQ
85
，
43
41
5
A0
A6
A4
K
A11
A8
NC
A13
L
VDD
ODT
VDD
VSS
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技
有
限
公
司
VDD
A2
18
66
VSS
NC
CS
，
BA2
CK
81
9
1
3
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration –
60 balls BGA Package (x8)
< TOP View>
See the balls through the package
8
9
A
VSSQ
DQS
VDDQ
DM/RDQS
B
DQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
C
VDDQ
DQ0
DQ4
VSSQ
DQ3
D
DQ2
VSSQ
VDDL
VREF
VSS
E
VSSDL
CK
VDD
CKE
WE
F
RAS
CK
ODT
BA0
BA 1
G
CAS
A10/ AP
A1
H
A3
A5
J
A7
A9
A12
NC
VSS
VDDQ
DQ5
CS
A2
A0
A6
A4
K
A11
A8
L
NC
A13
VDD
VSS
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技
有
限
公
司
VDD
，
BA2
51
VSSQ
44
DQ6
71
VSS
：
NU,/RDQS
QQ
VDD
81
7
85
，
3
43
41
5
2
18
66
1
9
X8
4
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Pin Configuration –
84 balls BGA Package (x16)
< TOP View>
See the balls through the package
x 16
2
3
7
8
9
VDD
NC
VSS
A
VSSQ
UDQS
VDDQ
DQ14
VSSQ
UDM
B
UDQS
VSSQ
VDDQ
DQ9
VDDQ
C
VDDQ
DQ8
DQ12
VSSQ
DQ11
D
DQ10
VSSQ
VDD
NC
VSS
E
VSSQ
DQ6
VSSQ
LDM
F
LDQS
VDDQ
DQ1
VDDQ
G
VDDQ
DQ4
VSSQ
DQ3
H
VDDL
VREF
VSS
J
CKE
WE
BA0
BA 1
51
DQ5
VSSDL
C
K
VDD
ODT
18
66
A1
M
A2
A0
A5
N
A6
A4
A7
A9
P
A11
A8
A12
NC
R
NC
NC
，
44
VSSQ
CS
公
71
：
QQ
85
，
DQ2
43
41
5
VDDQ
CAS
限
VDDQ
DQ0
L
技
有
DQ13
VDD
VSS
深
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金
合
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VDD
VDDQ
DQ7
CK
A3
DQ15
VSSQ
RAS
A10/ AP
VSS
LDQS
K
司
BA2
81
9
1
5
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Input / Output Functional Description
Symbol
Type
Function
Clock: CK and  are differential clock inputs. All address and control input signals are sampled
CK, 
on the crossing of the positive edge of CK and negative edge of . Output (read) data is
Input
referenced to the crossings of CK and  (both directions of crossing).
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device
81
9
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
51
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
Input
Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it
71
CKE
44
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
：
must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
QQ
exit, VREF must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input
85
，
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when  is registered high.  provides for external rank

43
41
5
Input
selection on systems with multiple memory ranks.
, , 
 is considered part of the command code.
Command Inputs: ,  and  (along with ) define the command being entered.
Input
18
66
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
DM, LDM, UDM
Input
，
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For
司
x8 device, the function of DM or RDQS /  is enabled by EMRS command.
Input
Precharge command is being applied. Bank address also determines if the mode register or
技
有
BA0 - BA2
限
公
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
extended mode register is to be accessed during a MRS or EMRS cycle.
圳
深
DQ
Auto Precharge or Read/Write commands to select one location out of the memory array in the
respective bank. A10 is sampled during a Precharge command to determine whether the
合
Input
市
金
A0 – A13
讯
科
Address Inputs: Provides the row address for Activate commands and the column address and
precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be
precharged, the bank is selected by BA0-BA2. The address inputs also provide the op-code during
Mode Register Set commands.A13 Row address use on x8 components only.
Input/output
Data Inputs/Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge aligned with read data, centered
with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to
DQS, ()
the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
LDQS, (),
Input/output
ended mode or paired with the optional complementary signals , ,  to provide
UDQS,()
differential pair signaling to the system during both reads and writes. An EMRS(1) control bit
enables or disables the complementary data strobe signals.
6
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Symbol
Type
Function
Read Data Strobe: For x8 components a RDQS and  pair can be enabled via EMRS(1) for
RDQS, ()
Input/output
real timing. RDQS and  is not support x16 components. RDQS and  are edge-aligned
with real data. If enable RDQS and  then DM function will be disabled.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2
SDRAM. When enabled, ODT is applied to each DQ, DQS, , RDQS, , and DM signal for
ODT
Input
81
9
x8 configuration. For x16 configuration ODT is applied to each DQ, UDQS, , LDQS, ,
Supply
DQ Power Supply:
1.8V ± 0.1V
VSSQ
Supply
DQ Ground
VDDL
Supply
DLL Power Supply:
VSSDL
Supply
DLL Ground
VDD
Supply
Power Supply:
VSS
Supply
Ground
VREF
Supply
SSTL_1.8 reference voltage
：
71
VDDQ
44
No Connect: No internal electrical connection is present.
85
，
QQ
1.8V ± 0.1V
1.8V ± 0.1V
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合
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技
有
限
公
司
，
18
66
43
41
5
NC
51
UDM and LDM signal. The ODT pin will be ignored if the EMRS (1) is programmed to disable ODT.
7
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Ordering Information
Green
Standard Grade
Speed
Package
CL-TRCD-TRP
NT5TU256M4GE – 3C
333
5-5-5
NT5TU256M4GE – AC
400
5-5-5
333
NT5TU128M8GE – BD
533
NT5TU64M16GG – 3C
333
NT5TU64M16GG – AC
NT5TU64M16GG – BD
NT5TU128M8GE – 3CI
Organization
81
5-5-5
533
6-6-6
Speed
Package
NT5TU128M8GE – ACI
Clock (Mbps)
Clock (Mbps)
333
5-5-5
400
5-5-5
333
5-5-5
400
5-5-5
60-Ball BGA
84-Ball BGA
司
，
NT5TU64M16GG – 3CI
18
66
Part Number
6-6-6
5-5-5
400
43
41
5
Industrial Grade
5-5-5
85
，
84-Ball BGA
44
400
QQ
NT5TU128M8GE – AC
5-5-5
71
60-Ball BGA
：
NT5TU128M8GE – 3C
Organization
9
Clock (Mbps)
51
Part Number
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技
有
限
公
NT5TU64M16GG – ACI
8
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Block Diagram (256Mb x 4)
Control Logic
CKE
CK
CK
CS
Command
Decode
WE
CAS
81
CK, CK
51
DLL
4
8
8192
512 (x16)
9
Column-Address
Counter/Latch
2
Mask
4
Write
FIFO
&
Drivers
，
Data
16
CK,
CK
1
1
1
1
1
1
1
1
4
4
4
4
1
4
4
4
4
COL0,1
DQS,
DQS
DM
4
2
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有
限
公
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DQS,
DQS
Input
Register
16
COL0,1
Notes:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ
and DQS signals.
DQ0-DQ3
COL0,1
43
41
5
11
18
66
3
2
DQS
Generator
Receivers
Column
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Decoder
8
MUX
4
85
，
Bank Control
Logic
4
QQ
2
I/O Gating
DM Mask Logic
4
ODT Control
Refresh Counter
A0 – A13,
BA0 – BA2
Address Register
17
16
ODT
Data
4
Drivers
16
Read Latch
14
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank
2
Memory
Array
Bank
1
Memory
Arrayx16)
(16384
Bank
0 x512
Memory
Arrayx16)
(16384
x512
Sense
Amplifier
Memoryx512
Arrayx16)
(16384
Sense Array
Amplifier
Memory
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
(16384
x16)
Sensex512
Amplifier
Sense Amplifier
44
14
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank
2
Row-Address
Bank
1
Row-Address
Bank
0 Latch &
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
16384
Latch
&
Decoder
Latch
&
Decoder
Decoder
71
17
14
：
Row-Address MUX
Mode
Registers
9
RAS
9
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Block Diagram (128Mb x 8)
Control Logic
CKE
CK
CK
CS
Command
Decode
WE
CAS
81
51
DLL
8
32
Bank Control
Logic
256 (x32)
10
Column-Address
Counter/Latch
2
4
，
CK,
CK
2
2
2
2
2
2
2
2
8
8
8
8
2
8
8
8
8
COL0,1
DQS,
DQS
RDQS , 
DM
8
2
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技
有
限
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Data
32
COL0,1
Notes:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ
and DQS signals.
Input
Register
Mask
Write
FIFO
&
Drivers
DQ0 – DQ7
DQS,
DQS
COL0,1
32
43
41
5
8
18
66
3
2
DQS
Generator
Receivers
Column
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Decoder
8
8
85
，
2
I/O Gating
DM Mask Logic
8
ODT Control
Refresh Counter
A0 – A13,
BA0 – BA2
Address Register
17
MUX
QQ
8192
8
Drivers
32
8
ODT
Data
8
Read Latch
14
CK, CK
44
14
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank
2
Memory
Array
Bank
1
Memory
Arrayx16)
(16384
Bank
0 x512
Memory
Arrayx16)
(16384
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x512
x16)
Sense Array
Amplifier
Memory
(16384
x16)
Sensex512
Amplifier
(16384
x32)
Sensex256
Amplifier
Sense Amplifier
71
17
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank
2
Row-Address
Bank
1
Row-Address
Bank
0 Latch &
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
16384
Latch
&
Decoder
Latch
&
Decoder
Decoder
：
Row-Address MUX
Mode
Registers
14
9
RAS
10
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Block Diagram (64Mb x 16)
Control Logic
CKE
CK
CK
CS
Command
Decode
WE
CAS
81
51
DLL
16
64
Bank Control
Logic
256 (x64)
2
8
，
CK,
CK
UDQS, 
LDQS, 
2
2
2
2
2
2
LDQS,
LDQS
2
2
2
16
16
16
16
16
16
16
16
COL0,1
UDQS,
UDQS
UDM,
LDM
16
4
深
圳
市
金
合
讯
科
技
有
限
公
司
Notes:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ
and DQS signals.
Data
64
COL0,1
DQ0 –
DQ15
Input
Register
Mask
Write
FIFO
&
Drivers
4
DQS
Generator
COL0,1
64
43
41
5
8
Column-Address
Counter/Latch
18
66
10
16
Receivers
Column
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Column
Decoder
Decoder
8
3
16
85
，
3
I/O Gating
DM Mask Logic
MUX
ODT Control
Refresh Counter
A0 – A12,
BA0 – BA2
Address Register
16
16
QQ
16384
ODT
Data
16
Drivers
64
8
Read Latch
13
CK, CK
44
13
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank
2
Memory
Array
Bank
1
Memory
Arrayx16)
(16384
Bank
0 x512
Memory
Arrayx16)
(16384
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
Memory
Array
(16384
x512
x16)
Sense Amplifier
Memory
Array
(16384
x16)
Sensex512
Amplifier
(8192
x 256
x 64)
Sense
Amplifier
Sense Amplifier
71
16
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank
2
Row-Address
Bank
1
Row-Address
Bank
0 Latch &
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
Latch
&
Decoder
Row-Address
8192
Latch
&
Decoder
Latch
&
Decoder
Decoder
：
Row-Address MUX
Mode
Registers
13
9
RAS
11
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Functional Description
The 1Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. The
1Gb DDR SDRAM is internally configured as a octal-bank DRAM.
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for
the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command,
9
which is followed by a Read or Write command. The address bits registered coincident with the activate command are
81
used to select the bank and row to be accesses (BA0, BA1, & BA2 select the banks, A0-A13 select the row for x4 and x8
51
components, A0-A12 select the row for x16 components). The address bits registered coincident with the Read or Write
44
command are used to select the starting column location for the burst access and to determine if the Auto-Precharge
：
71
command is to be issued.
QQ
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
85
，
covering device initialization, register definition, command description and device operation.
43
41
5
Power-up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
18
66
specified may result in undefined operation.
The following sequence is required for POWER UP and Initialization.
，
1. Either one of the following sequence is required for Power-up.
司
While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be unde-
限
公
fined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and
技
有
during the VDD voltage ramp up, IVDD-VDDQI≦0.3 volts. Once the ramping of the supply voltages is complete (when
VDDQ crosses VDDQ min), the supply voltage specifications in Re-commanded DC operating conditions table.
讯
科
- VDD, VDDL, and VDDQ are driven from a signal power converter output, AND
- VTT is limited to 0.95V max, AND
合
- Vref tracks VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.
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- VDDQ>=VREF must be met at all times.
While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be
深
圳
undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up.
During the ramping of the supply voltages, VDD≧VDDL≧VDDQ must be maintained and is applicable to both AC and
DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the
ramping of the supply voltages is complete, the supply voltage specifications provided in Re-commanded DC operating
conditions table.
- Apply VDD/VDDL before or at the same time as VDDQ.
- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin.
- Apply VDDQ before or at the same time as VTT.
12
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must
be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to
VDDQ.)
- Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.
- VDDQ ≧ VREF must be met at all time.
- Apply VTT.
81
9
2. Start clock (CK, ) and maintain stable condition.
51
3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and
44
maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or
：
71
Deselect & take CKE HIGH.
QQ
4. Waiting minimum of 400ns then issue pre-charge all command. NOP or Deselect applied during 400ns period.
85
，
5. Issue an EMRS command to EMR (2). (Provide LOW to BA0 and BA2, and HIGH to BA1).
43
41
5
6. Issue an EMRS command to EMR (3). (Provide LOW to BA2 and HIGH to BA0 and BA1).
7. Issue EMRS to enable DLL. (Provide Low to A0, HIGH to BA0 and LOW to BA1-BA2 and A13-A15. And
18
66
A9=A8=A7=LOW must be used when issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (Provide HIGH to A8 and LOW to BA0-BA2, and A13-A15.)
司
，
9. Issue a precharge all command.
公
10. Issue 2 more auto-refresh commands.
限
11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without
技
有
resetting the DLL.)
讯
科
12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration
is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit
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金
合
OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 DRAM is now ready for normal operation.
圳
* To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
深
Example
CK, CK
CKE
ODT "low"
NOP
Command
tMRD
tRP
400 ns
PRE
ALL
CMD
EMRS
Extended Mode
Register Set
with DLL enable
tMRD
tRP
PRE
ALL
MRS
Mode Register Set
with DLL reset
1st Auto
refresh
min. 200 cycles to
lock the DLL
tMRD
tRFC
tRFC
2nd Auto
refresh
MRS
Follow OCD
flowchart
EMRS
EMRS
Follow OCD
flowchart
13
REV 1.0
Dec / 2009
CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Register Definition
Programming the Mode Registration and Extended Mode Registers
For application flexibility, burst length, burst type,  latency, DLL reset function, write recovery time (tWR) are user
defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable
function, additive  latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip
driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register
81
9
Set (EMRS) command. Contents of the Mode Register (MR) and Extended Mode Registers (EMR (#)) can be altered by
51
re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables,
44
all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect
71
array contents, which mean re-initialization including those can be executed any time after power-up without affecting
QQ
：
array contents.
85
，
Mode Registration Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls  latency,
43
41
5
burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM
useful for various applications. The default value of the mode register is not defined, therefore the mode register must be
18
66
written after power-up for proper operation. The mode register is written by asserting low on , , , , BA0 and
BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all banks precharged (idle)
，
mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (t MRD) is
司
required to complete the write operation to the mode register. The mode register contents can be changed using the
公
same command and clock cycle requirements during normal operation as long as all banks are in the precharged state.
限
The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options
技
有
of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and  latency is defined by A4 ~ A6. A7 is
used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for
深
圳
市
金
合
讯
科
write recovery time (WR) definition for Auto-Precharge mode.
14
REV 1.0
Dec / 2009
CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
MRS Mode Register Operation Table (Address Input for Mode Set)
Address Field
BA2* BA1 BA0 A13* A 12 A11 A10 A9
A7 A6
A5
A4
A3
A2
A1
A0
9
A8
BA 1 BA0 MRS mode
0
0
MR
0
1
EMR(1)
1
0
EMR (2)
1
1
EMR(3)
Fast exit (use tXARD)
1
Slow exit (use tXARDS)
18
66
0
43
41
5
Active power down
exit time
Write recovery for autoprecharge
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
1
1
7
1
8
限
技
有
讯
科
市
金
DDR2-1066
DDR2-800
1
DDR2-667
1
0
6
司
0
公
0
，
WR (cycles)
合
A11 A10 A9
圳
0
NO
1
YES
深
DLL Reset
1
0
4
1
1
8
Burst Type
Burst Type
0
Sequential
1
Interleave
/ CAS Latency
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Mode
A7
Mode
0
Normal
1
TEST
DLL Reset
A8
BL
A3
85
，
QQ
：
71
0
Active power down exit time
A12
A0
44
0
A1
51
A2
81
Burst Length
MRS mode
* BA2 and A13 are reserved for future use and must be set to
"0" when programming MR.
15
REV 1.0
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CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Extended Mode Register Set -EMRS (1) Programming
Address Field
BA2* BA1 BA0 A13 * A12 A11 A10 A9
A8
A7 A6
A5
A4
A3
A2
A1
A0
0
1
EMR(1)
1
0
EMR(2)
1
1
EMR(3)
QQ
0
Output buffer enabled
1
Output buffer disabled
85
，
Qoff *5
43
41
5
A12
A11 RDQS Enable*6
18
66
RDQS
DQS
1
Enable
0
Enable
1
Disable
司
A10
A5
限
公
Disable
，
DQS
0
1
Reduced strength
Rtt
A6
A2
Rtt (Nominal)
0
0
ODT Disabled
0
1
75 ohm
1
0
150 ohm
1
1
50 ohm *2
Additive Latency
Additive
A4 A3
Latency
OCD Program
0
0
1
1
A7 OCD Calibration Program
0
1
0
2
0
1
1
3
Drive(1)
0
0
4
Drive(0)
0
1
5
1
1
0
6
1
1
1
Reserved
0
0
OCD Calibration mode
exit; maintain setting
合
0
讯
科
技
有
0
0
1
1
0
1
0
0
1
1
1
市
金
圳
Full strength
0
0
深
0
0
A8
1
Disable
0
A9
1
1
D.I.C
Output Driver
A1
Impedance Control
Qoff
0
Enable
44
MR
0
71
0
：
0
DLL
Enable
51
BA1 BA0 MRS mode
A0
9
MRS mode
81
DLL
Adjust mode *3
OCD Calibration default*4
* BA2 and A13 are reserved for future use and must be set to 0 when programming the EMR(1).
*2 Mandatory for DDR2-1066
*3 When Adjust mode is issued, AL from previously set value must be applied.
*4 After setting to default, OCD calibration mode needs to be exited by settin gA9-A7 to 000.
*5 Output disabled – DQs, DQSs, DQSs, RDQS, RDQS. This feature is used in conjunction with DIMM IDD
measurements when IDDQ is not desired to be included.
*6 If RDQS is enabled, the DM function is disabled. RDQS is active for reads and do not care for writes.
16
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Extended Mode Register Set –EMRS (1)
The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive
latency, ODT,  disable, OCD program, RQDS enable. The default value of the extended mode register EMRS(1) is
not defined, therefore the extended mode register must be written after power-up for proper operation. The extended
mode register is written by asserting low on , , , , BA1 and high on BA0, while controlling the state of the
address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended
81
9
mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the
51
EMRS (1). Mode register contents can be changed using the same command and clock cycle requirements during normal
44
operation as long as all banks are in precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half
71
strength output driver. A3-A5 determines the additive latency, A7-A9 are used for OCD control, A10 is used for 
QQ
：
disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.
85
，
Single-ended and Differential Data Strobe Signals
43
41
5
The following table lists all possible combinations for DQS, , RDQS,  which can be programmed by A10 & A11
address bits in EMRS(1). RDQS and  are available in x8 components only. If RDQS is enabled in x8 components,
the DM function is disabled. RDQS is active for reads and don‟t care for writes.
A11
A10
(RDQS Enable)
( Enable)
0 (Disable)
0 (Enable)
DM
0 (Disable)
1 (Disable)
1 (Enable)
0 (Enable)
1 (Enable)
1 (Disable)
DQS

Signaling
Hi-Z
DQS

differential DQS signals
Hi-Z
DQS
Hi-Z
single-ended DQS signals
RDQS

DQS

differential DQS signals
RDQS
Hi-Z
DQS
Hi-Z
single-ended DQS signals
司
限
DM

，
RDQS/DM
讯
科
技
有
18
66
Strobe Function Matrix
公
EMRS (1)
DLL Enable/Disable
合
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning
市
金
to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh
operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset,
圳
200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be
深
synchronized with the external clock. Less clock cycles may result in a violation of the t AC or tDQSCK
parameters.
Output Disable (Qoff)
Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS (1) is
set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to
measure IDD currents during Read operations, without including the output buffer current and external load currents.
17
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
EMRS (2) Extended Mode Register Set Programming
BA2 BA1 BA0 A12 A11 A10
0*
A6
A5
A4
A3
A2
A1
0*
Address Field
Extended Mode
Register
PASR***
9
SRF
A0
MRS mode
A7
0
0
MRS
0
Disable
0
1
EMRS(1)
1
Enable** (85C Tcase 95C)
1
0
EMRS(2)
1
1
EMRS(3):
Reserved
81
BA1 BA0
A7
High Temperature Self-Refresh Rate Enable
51
0
1
A8
QQ
：
71
44
0*
A9
A2
A1
A0
0
0
0
Full array
0
0
1
Half Array (BA[2:0]=000, 001, 010, &011)
0
1
0
Quarter Array (BA[2:0]=000&001)
0
1
1
1/8th array (BA[2:0] = 000)
1
0
0
3 / 4 array (BA[2:0]=010,011,100,101,110, &111)
1
0
1
Half array (BA[2:0]=100, 101, 110, & 111)
1
1
0
Quarter array (BA[2:0]=110&111)
1
1
1
1/8th array (BA[2:0]=111)
司
，
18
66
43
41
5
85
，
Partial Array Self Refresh
讯
科
技
有
限
公
* The rest bits in EMRS(2) is reserved for future use and all bits in EMRS (2) except A0-A2,A7,BA0, and
BA1 must be programmed to 0 when setting EMRS(2) during initialization.
** DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0].
*** Optional. If PASR(Partial Array Self Refresh ) is enabled, data located in areas of the array beyond the
spec. location will be lost if self refresh is entered .
合
Extended Mode Register Set EMRS (2)
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The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is
not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1,
圳
while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already
深
high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be
satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using
the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.
EMRS(3) Extended Mode Register Set Programming
All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode
register during initialization.
18
REV 1.0
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© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every
calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued.
MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully
9
controlled depending on system environment.
51
81
MRS should be set before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
Start
71
44
EMRS: OCD calibration mode exit
EMRS: Drive(0)
DQ & DQS Low; DQS High
ALL OK
85
，
ALL OK
QQ
：
EMRS: Drive (1)
DQ & DQS High; DQSLow
Test
Test
EMRS: OCD calibration mode exit
18
66
EMRS: OCD calibration mode exit
EMRS :
EMRS :
Enter Adjust Mode
司
BL =4 code input to all DQs
Inc, Dec, or NOP
限
公
Inc, Dec, or NOP
，
Enter Adjus t Mode
BL=4 cod e inpu t to all DQs
Need Calibration
43
41
5
Need Calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
深
圳
市
金
合
讯
科
技
有
EMRS: OCD calibration mode exit
19
REV 1.0
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CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS (1) mode. In drive mode all outputs are driven out by
DDR2 SDRAM and drive of RDQS is dependent on EMRS (1) bit enabling RDQS operation. In Drive (1) mode, all DQ, DQS
(and RDQS) signals are driven high and all  (and ) signals are driven low. In Drive (0) mode, all DQ, DQS (and
RDQS) signals are driven low and all  (and ) signals are driven high. In adjust mode, BL = 4 of operation code
data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18
81
9
Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are
51
specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS (1) and if half
44
strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD
71
default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,
：
subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as ‟000‟ in order to
QQ
maintain the default or calibrated value.
43
41
5
85
，
Off- Chip-Driver program
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive(1) DQ, DQS, (RDQS) high and  low
0
1
0
Drive(0) DQ, DQS, (RDQS) low and  high
1
0
0
1
1
1
，
18
66
A9
司
Adjust mode
深
圳
市
金
合
讯
科
技
有
限
公
OCD calibration default
20
REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS (1) command along with a 4 bit burst code to
DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before
activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at
bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs
9
simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength
81
setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or
51
decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust
0
0
0
NOP (no operation)
NOP (no operation)
0
0
0
1
Increase by 1 step
0
0
1
0
Decrease by 1 step
0
1
0
0
NOP
1
0
0
0
NOP
0
1
0
1
Increase by 1 step
Increase by 1 step
0
1
1
0
Decrease by 1 step
Increase by 1 step
1
0
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
NOP
NOP
Increase by 1 step
Decrease by 1 step
Reserved
限
公
Other Combinations
85
，
0
71
Pull-down driver strength
QQ
Pull-up driver strength
43
41
5
DT3
18
66
DT2
，
DT1
司
DT0
Operation
：
4 bit burst code inputs to all DQs
44
mode command is issued, AL from previously set value must be applied.
技
有
For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing
diagram. Input data pattern for adjustment, DT0 ~ DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or
深
圳
市
金
合
讯
科
interleave).
21
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
OCD Adjust Mode
OCD calibration
mode exit
OCD adjust mode
CK
CK
NOP
NOP
NOP
NOP
DQS
WL
NOP
EMRS
NOP
9
EMRS
WR
81
CMD
tDS
tDH
DT1
DT2
DT3
71
DT0
44
DQ
51
DQS
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
DM
22
REV 1.0
Dec / 2009
CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Drive Mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD
impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers
9
are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
NOP
NOP
NOP
EMRS(1)
NOP
tOIT
tOIT
DQS_in
NOP
：
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0
QQ
DQS high for Drive(1)
85
，
DQS high for Drive(0)
DQ_in
NOP
44
NOP
EMRS(1)
71
CMD
51
81
CK, CK
OCD calibration
mode exit
43
41
5
Enter Drive Mode
On-Die Termination (ODT)
18
66
ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS,
, RDQS, , and DM signal for x8 configurations via the ODT control pin. For x16 configuration ODT is applied to
，
each DQ, UDQS, , LDQS, , UDM and LDM signal via the ODT control pin. The ODT feature is designed to
公
限
resistance for any or all DRAM devices.
司
improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination
技
有
The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode.
深
圳
市
金
合
讯
科
Functional Representation of ODT
VDDQ
VDDQ
VDDQ
sw1
sw2
sw3
Rval1
Rval2
Rval3
DRAM
Input
Buffer
Input
Pin
Rval1
Rval2
Rval3
sw1
sw2
sw3
VSSQ
VSSQ
VSSQ
Switch sw1, sw2, or sw3 is enabled by the ODT pin. Selection between sw1, sw2, or sw3 is determined by “Rtt (nominal)” in EMRS.
Termination included on all DQs, DM, DQS, , RDQS, and  pins.
23
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
ODT related timings
MRS command to ODT update delay
During normal operation the value of the effective termination resistance can be changed with an EMRS command. The
update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of
EMRS
NOP
NOP
NOP
NOP
NOP
44
51
CMD
81
9
tMOD window for proper operation. The timings are shown in the following timing diagram.
tIS
QQ
CKE
tMOD, min
Old setting
Updating
New setting
43
41
5
Rtt
85
，
tMOD, max
tAOFD
：
71
CK, CK
18
66
EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)
Setting in this diagram is the Register and I/O setting, not what is measured from outside.
，
However, to prevent any impedance glitch on the channel, the following conditions must be met.
司
- tAOFD must be met before issuing the EMRS command.
公
- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.
限
Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT.
讯
科
技
有
Following timing diagram shows the proper Rtt update procedure.
NOP
NOP
市
金
CK, CK
EMRS
NOP
NOP
tIS
圳
CKE
深
NOP
合
CMD
tAOND
tMOD, max
tAOFD
Rtt
Old setting
New setting
EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)
Setting in this diagram is the Register and I/O setting, not what is measured from outside.
24
REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
ODT On/Off timings
ODT timing for active/standby mode
T-1
T-0
T-2
T-3
T-4
T-6
T-5
CK, CK
81
9
tIS
CKE
tAOND
Internal
Term Res.
71
tAOFD(2. 5 tck)
Rtt
tAON, min
QQ
tAOF, min
：
tIS
ODT
44
51
tIS
tAON, max
43
41
5
85
，
tAOF, max
T0
T1
18
66
ODT Timing for Power-down mode
T2
T4
T5
T6
司
，
CK, CK
T3
公
CKE
技
有
限
tIS
ODT
tIS
讯
科
tAOFPD,max
tAOFPD,min
Rtt
tAONPD,min
tAONPD,max
深
圳
市
金
合
DQ
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REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Bank Activate Command
The Bank Activate command is issued by holding  and  high plus  and  low at the rising edge of the clock.
The bank addresses BA0 ~ BA2 are used to select the desired bank. The row addresses A0 through A13 are used to
determine which row to activate in the selected bank for and x8 organized components. For x16 components row
addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write
9
operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write
81
command (with or without Auto-Precharge) on the following clock cycle. If an R/W command is issued to a bank that has
51
not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command
44
which is internally issued to the device. The additive latency value must be chosen to assure t RCDmin is satisfied. Additive
71
latencies of 0, 1, 2, 3, 4, 5, and 6 are supported. Once a bank has been activated it must be precharged before another
：
Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as t RAS and tRP,
QQ
respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined
85
，
(tRC). The minimum time interval between Bank Active commands, to other bank, is the Bank A to Bank B delay time (tRRD).
43
41
5
In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices,
certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the
number of sequential ACTcommands that can be issued and another for allowing more time for RAS precharge for a
18
66
Precharge All command. The rules are list as follow:
，
* 8 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window.
司
Conveting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling
公
window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further
限
activate commands may be issued in clock N+1 through N+9.
技
有
*8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+tCK,
where tRP is the value for a single bank pre-charge.
讯
科
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
圳
市
金
CK, CK
T1
T2
T3
T4
Tn
Tn+1
合
T0
深
Address
Tn+2
Tn+3
Internal RAS-CAS delay tRCDmin.
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Addr.
NOP
Bank B
Addr.
Bank A
Row Addr.
Bank A to Bank B delay tRRD.
additive latency AL=2
RAS-RAS delay tRRD.
Command
Bank A
Activate
Posted CAS
Read A
Bank B
Activate
Read A
Begins
Posted CAS
Read B
tRAS Row Active Time (Bank A)
Bank A
Precharge
NOP
Bank B
Precharge
Bank A
Activate
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
ACT
26
REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting  high,  and
 low at the clock‟s rising edge.  must also be defined at this time to determine whether the access cycle is a read
operation ( high) or a write operation ( low). The DDR2 SDRAM provides a fast column access operation. A single
Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst
cycle is restricted to specific segments of the page length.
81
9
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of
51
BL=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes
44
interrupted by a write with 4 bit burst boundary respectively, and the minimum  to  delay (tCCD) is minimum 2
：
71
clocks for read or write cycles.
85
，
QQ
Posted 
Posted  operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
43
41
5
SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the 
bank activate command (or any time during the  to  delay time, tRCD, period). The command is held for the time of
the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the 
18
66
latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0
must be written into the EMRS (1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read
，
Latency is defined as the sum of Additive Latency plus  latency (RL=AL+CL). If a user chooses to issue a Read
技
有
限
Example of posted  operation:
公
司
command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL.
Read followed by a write to the same bank:
2
0
1
Activate
Bank A
Read
Bank A
3
4
5
6
7
8
9
10
11
12
市
金
合
-1
讯
科
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
圳
CK, CK
深
CMD
DQS,
DQS
DQ
AL = 2
Write
Bank A
WL = RL -1 = 4
CL = 3
>=tRCD
RL = AL + CL = 5
Dout0 Dout1 Dout2Dout3
Din0 Din1 Din2 Din3
PostCAS1
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REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Read followed by a write to the same bank:
AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
-1
0
1
3
2
4
5
6
7
8
9
10
11
12
CK, CK
AL=0
Read
Bank A
>=tRCD
9
Write
Bank A
WL = RL – 1 = 2
CL=3
81
Activate
Bank A
CMD
RL = AL + CL = 3
DQ
Din0
Din1
Din2
Din3
PostCAS5
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
Dout0 Dout1 Dout2 Dout3
44
51
DQS,
DQS
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REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence
and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full
interleave address ordering is supported, however, sequential address ordering is nibble based for ease of
implementation. The burst type, either sequential or interleaved, is programmable and defined by the address
81
9
bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or
51
write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write
44
burst when burst length = 8 is used, see the “Burst Interruption “section of this datasheet. A Burst Stop
71
command is not supported on DDR2 SDRAM devices.
Starting Address
Sequential Addressing
(A2 A1 A0)
(decimal)
0,
1,
x 0
1
1,
2,
x 1
0
2,
3,
x 1
1
3,
0,
0
0
0
0,
1,
2, 3,
4,
5,
7
0,
1,
2, 3,
4,
5,
6,
7
0
0
1
1,
2,
18
66
6,
3, 0,
，
5,
6,
7,
4
1,
0,
3, 2,
5,
4,
7,
6
0
1
0
3,
司
0, 1,
6,
7,
4,
5
2,
3,
0, 1,
6,
7,
4,
5
0
1
1
3,
0,
1, 2,
7,
4,
5,
6
3,
2,
1, 0,
7,
6,
5,
4
1
0
4,
5,
6, 7,
0,
1,
2,
3
4,
5,
6, 7,
0,
1,
2,
3
公
限
0
技
有
8
0,
1,
2, 3
3, 0
1,
0,
3, 2
0, 1
2,
3,
0, 1
1, 2
3,
2,
1, 0
43
41
5
0
2,
2, 3
(decimal)
x 0
4
0
1
5,
6,
7, 4,
1,
2,
3,
0
5,
4,
7, 6,
1,
0,
3,
2
1
1
0
6,
7,
4, 5,
2,
3,
0,
1
6,
7,
4, 5,
2,
3,
0,
1
1
1
7,
4,
5, 6,
3,
0,
1,
2
7,
6,
5, 4,
3,
2,
1,
0
讯
科
1
1
1) Page length is a function of I/O organization
合
Note:
Interleave Addressing
85
，
Burst Length
QQ
：
Bust Length and Sequence
市
金
64Mb X 16 organization (CA0-CA9); Page Size = 2K Byte; Page Length = 1024
深
圳
128Mb X 8 organization (CA0-CA9 ); Page Size = 1K Byte; Page Length = 1024
256Mb x 4 organization (CA0-CA9, CA11); Page Size = 1K Byte; Page Length = 2048
2) Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or
DDR components
29
REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Read Command
The Burst Read command is initiated by having  and  low while holding  and  high at the rising edge of the
clock. The address inputs determine the starting column address for the burst. The delay from the start of the command
until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output
(DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is
synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with
81
9
the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus  latency (CL). The
The AL is defined by the Extended Mode Register Set (EMRS (1))
51
CL is defined by the Mode Register Set (MRS).
t CL
t CK
：
t CH
71
44
Basic Burst Read Timing
CLK, CLK
QQ
CLK
CLK
t DQSCK
85
，
t AC
DQS
DQS,
DQS
43
41
5
DQS
t RPRE
t RPST
t LZ
DQ
Dout
t DQSQmax
t QH
DO-Read
，
t QH
Dout
Dout
18
66
Dout
t DQSQmax
t HZ
司
Examples:
圳
T4
NOP
NOP
NOP
NOP
T5
T6
T7
T8
NOP
NOP
NOP
NOP
<= tDQSCK
AL = 2
CL = 3
RL = 5
Dout A0
深
DQ
T3
合
Post CAS
READ A
市
金
DQS,
DQS
讯
科
CK, CK
CMD
T2
限
T1
技
有
T0
公
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
Dout A1
Dout A2
Dout A3
BRead523
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REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
9
<= tDQSCK
51
81
DQS,
DQS
RL = 3
DQ's
Dout A1
Dout A2
Dout A3 Dout A4
Dout A5
Dout A6
Dout A7
71
Dout A0
44
CL = 3
85
，
QQ
：
BRead303
Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4
43
41
5
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around
time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.
Tn-1
T1
Tn+1
Tn
Tn+3
Tn+4
Tn+5
，
CK, CK
NOP
Posted CAS
WRITE A
司
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
公
CMD
Tn+2
18
66
T0
限
tRTW(Read to Write turn around time)
技
有
DQS,
DQS
WL = RL - 1 = 4
RL = 5
Dout A0
Dout A1
Dout A2
讯
科
DQ
Dout A3
Din A0
Din A1
Din A2
Din A3
深
圳
市
金
合
BRBW514
31
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
Post CAS
READ A
CMD
Post CAS
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
AL = 2
81
9
DQS,
DQS
RL = 5
DQ
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
44
Dout A0
51
CL = 3
71
SBR523
：
The seamless burst read operation‟s supported by enabling a read command at every clock for BL=4 operation, and every
QQ
4 clock for BL=8 operation. This operation allows regardless of same or different banks as long as the banks activated.
85
，
Burst Write Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock.
43
41
5
The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one
and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The
18
66
first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The
tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the
，
DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied
司
to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the
公
completion of the burst write to bank precharge is named “write recovery time” (WR) .
限
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the
技
有
EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which
the DDR2 SDRAM pin timing measured is mode dependent.
讯
科
Basic Burst Write Timing
合
t DQSH
t DQSL
市
金
DQS
DQS,
DQS
圳
DQS
t WPST
深
t WPRE
Din
t DS
Din
Din
Din
t DH
32
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Example:
Burst Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
NOP
NOP
NOP
<= tDQSS
NOP
Completion of
the Burst Write
DQS,
DQS
tWR
71
WL = RL-1 = 4
DQ
Precharge
9
NOP
NOP
81
NOP
51
Post CAS
WRITE A
44
CMD
BW543
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
DIN A0 DIN A1 DIN A2 DIN A3
33
REV 1.0
Dec / 2009
CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4
The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around
time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.
Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
T8
9
CK, CK
NOP
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
44
NOP
51
CMD
81
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
：
QQ
DQ
CL=3
AL=2
tWTR
WL = RL - 1 = 4
71
DQS,
DQS
DIN A0 DIN A1 DIN A2 DIN A3
85
，
RL=5
BWBR
tWTR is the write-to-read
tWTR where
43
41
5
The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 +
turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the
time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.
T1
T2
T3
T5
T6
T7
T8
Post CAS
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
限
NOP
技
有
Post CAS
WRITE A
公
司
CK, CK
CMD
T4
，
T0
18
66
Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
讯
科
DQS,
DQS
WL = RL - 1 = 4
DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3
SBR
市
金
合
DQ
The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This
深
圳
operation is allowed regardless of same or different banks as long as the banks are activated.
34
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Write Data Mask
One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the
implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a
uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit
organization is not used during read cycles. However, DM of x8 bit organization can be used as RDQS during read cycles
by EMRS (1) setting.
t DQSH
81
9
Write Data Mask Timing
44
51
t DQSL
DQS,
DQS
71
DQS
：
DQS
t WPST
Din
Din
t DS
Din
Din
43
41
5
t DH
85
，
DQ
QQ
t WPRE
18
66
DM
司
，
don't care
WRITE A
讯
科
CK, CK
CMD
T2
限
T1
T3
T4
T5
T6
T7
T9
技
有
T0
公
Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, t WR = 3, BL = 4
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
Bank A
Activate
市
金
合
<= tDQSS
DQS,
DQS
圳
WL = RL-1 = 2
tRP
DIN A0 DIN A1 DIN A2 DIN A3
深
DQ
tWR
DM
DM
35
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Interruption
Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of
8 under the following conditions:
1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or
81
2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or
9
Precharge Command is prohibited.
51
Precharge Command is prohibited.
44
3. Read burst interrupt occur exactly two clocks after the previous Read command. Any other Read burst
：
71
interrupt timings are prohibited.
QQ
4. Write burst interrupt occur exactly two clocks after the previous Write command. Any other Read burst
85
，
interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.
43
41
5
6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted.
18
66
7. Read burst interruption is allowed by a Read with Auto-Precharge command.
8. Write burst interruption is allowed by a Write with Auto-Precharge command.
，
9. All command timings are referenced to burst length set in the mode register. They are not referenced to the
司
actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in
公
the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge
深
圳
市
金
合
讯
科
技
有
the end of the actual burst end.
限
timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form
36
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Examples:
Read Burst Interrupt Timing Example: (CL = 3, AL = 0, RL = 3, BL = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CMD
NOP
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
44
51
READ A
81
9
CK, CK
DQ
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3 Dout B4
Dout B5
Dout B6
Dout B7
85
，
QQ
Dout A0
：
71
DQS,
DQS
43
41
5
RBI
T0
T1
T2
18
66
Write Burst Interrupt Timing Example: (CL = 3, AL = 0, WL = 2, BL = 8)
T3
T4
T6
T7
T8
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
限
NOP
公
CMD
司
，
CK, CK
T5
技
有
DQS,
DQS
Din A0
Din A1
Din A2
Din A3
Din B0
Din B1
合
讯
科
DQ
Din B2
Din B3
Dout B4
Din B5
Din B6
Din B7
深
圳
市
金
WBI
37
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The
Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three
address bits A10, BA0, BA1, and BA2 are used to define which bank to precharge when the command is
9
issued.
BA2
BA1
BA0
LOW
LOW
LOW
LOW
Bank 0 only
LOW
LOW
LOW
HIGH
Bank 1 only
LOW
LOW
HIGH
LOW
Bank 2 only
LOW
LOW
HIGH
HIGH
Bank 3 only
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
Don't Care
Don't Care
71
：
QQ
85
，
43
41
5
Bank 4 only
HIGH
Bank 5 only
LOW
Bank 6 only
HIGH
Bank 7 only
Don't Care
all banks
司
，
18
66
44
Bank(s)
51
Precharge
A10
81
Bank Selection for Precharge by Address Bit
公
Burst Read Operation Followed by a Precharge
限
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks.
技
有
For the earliest possible precharge, the Precharge command may be issued on the rising edge which is “Additive Latency
讯
科
(AL) + BL/2 clocks” after a Read Command, as long as the minimum t RAS timing is satisfied.
合
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates
市
金
the last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the
time from the actual read (AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2
深
圳
clocks after the Read to the Precharge command.
38
REV 1.0
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CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Examples:
Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, t RTP ≦ 2 clocks
T0
T1
T2
T3
T4
NOP
NOP
Precharge
T5
T6
T7
T8
NOP
NOP
NOP
AL + BL/2 clks
Bank A
Activate
>=tRP
44
DQS,
DQS
AL = 1
71
CL = 3
Dout A1
Dout A2
Dout A3
QQ
Dout A0
>=tRAS
：
RL = 4
DQ
NOP
81
Post CAS
READ A
51
CMD
9
CK, CK
CL = 3
85
，
>=tRC
BR-P413
43
41
5
>=tRTP
T2
T3
T5
T6
T7
T8
Post CAS
READ A
限
公
CK, CK
NOP
NOP
NOP
NOP
Precharge
NOP
NOP
NOP
技
有
CMD
T4
，
T1
司
T0
18
66
Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, t RTP ≦ 2 clocks
AL + BL/2 clks
讯
科
DQS,
DQS
AL = 1
CL = 3
RL = 4
深
圳
市
金
合
DQ
Dout A0
>=tRAS
first 4-bit prefetch
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
CL = 3
>=tRC
>=tRTP
second 4-bit prefetch
BR-P413(8)
39
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, t RTP ≦ 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
Precharge
NOP
>=tRP
9
AL + BL/2 clks
Bank A
Activate
NOP
81
DQS,
DQS
51
CL = 3
AL = 2
RL = 5
Dout A0
>=tRAS
Dout A1
Dout A2
Dout A3
44
DQ
71
CL = 3
>=tRC
>=tRTP
QQ
：
BR-P523
T1
T2
T3
T4
CK, CK
Post CAS
READ A
NOP
NOP
Precharge
A
NOP
AL + BL/2 clocks
NOP
NOP
T7
T8
Bank A
Activate
NOP
AL = 2
司
CL = 4
，
>=tRP
DQS,
DQS
公
RL = 6
DQ
T6
18
66
CMD
T5
43
41
5
T0
85
，
Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, t RTP ≦ 2 clocks
Dout A0
Dout A1
Dout A2
Dout A3
CL = 4
限
>=tRAS
>=tRTP
BR-P624
深
圳
市
金
合
讯
科
技
有
>=tRC
40
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
Precharge
T7
T8
CK, CK
CMD
NOP
READ A
NOP
AL + BL/2 clks + 1
Bank A
Activate
NOP
NOP
>=tRP
81
9
DQS,
DQS
RL = 4
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A6
Dout A7
71
>=tRAS
QQ
：
>=tRTP
first 4-bit prefetch
44
DQ
51
CL = 4
BR-P404(8)
85
，
second 4-bit prefetch
43
41
5
Burst Write followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay
18
66
must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.
This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the
，
Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does
司
not support any burst interrupt by a Precharge command. t WR is an analog timing parameter (see the AC table
限
公
in this datasheet) and is not the programmed value for tWR in the MRS.
技
有
Examples:
讯
科
Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3
市
金
CK, CK
T
2
T
3
T
4
T
5
Post CAS
WRITE A
NOP
NOP
NOP
T
6
NOP
NOP
圳
CMD
T
1
T
7
T
8
合
T
0
NOP
Precharge
A
深
Completion of
the Burst Write
DQS,
DQS
>=tWR
WL = 3
DQ
NOP
DIN
A0
DIN
A1
DIN
A2
DIN
A3
BW-P3
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REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK, CK
Post CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
Precharge
A
NOP
NOP
44
DQ
81
tWR
WL = 4
9
Completion of
the Burst Write
DQS,
DQS
51
CMD
BW-P4
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
DIN A0 DIN A1 DIN A2 DIN A3
42
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-charge
Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the 
timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the
earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued,
then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence.
9
If A10 is high when the Read or Write Command is issued, then the Auto-Precharge function is enabled. During
81
Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge
51
internally on the rising edge which is  Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is
44
also implemented for Write Commands. The precharge operation engaged by the Auto-Precharge command will not begin
71
until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge
：
operation to be partially or completely hidden during burst read cycles (dependent upon  Latency) thus improving
QQ
system performance for random data access. The RAS lockout circuit internally delays the precharge operation until the
85
，
array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write
43
41
5
command.
18
66
Burst Read with Auto-Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM
，
starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if
If tRTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will
公
delayed until tRAS(min) is satisfied.
司
tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be
限
be delayed until tRTP(min) is satisfied.
技
有
In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the
next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate
讯
科
command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL
+ 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded up to the next integer value. In any event internal
市
金
合
precharge does not start earlier than two clocks after the last 4-bit prefetch.
圳
A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously:
深
(1) The  precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.
(2) The  cycle time (tRC) from the previous bank activation has been satisfied.
43
REV 1.0
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CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Examples:
Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit)
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≦ 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
A10 ="high"
AL + BL/2
44
Auto-Precharge Begins
CL = 3
71
DQS,
DQS
tRP
：
AL = 2
RL = 5
Dout A0
Dout A1
Dout A2
Dout A3
85
，
tRAS
tRCmin.
QQ
DQ
Bank
Activate
NOP
51
Posted CAS
READ w/AP
CMD
81
9
CK, CK
43
41
5
BR-AP5231
18
66
Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit):
T1
T2
A10 ="high"
限
NOP
NOP
技
有
Posted CAS
READ w/AP
tRAS(min)
讯
科
DQS,
DQS
AL = 2
T5
NOP
NOP
T6
T7
T8
NOP
Bank
Activate
NOP
NOP
Auto-Precharge Begins
CL = 3
tRP
合
RL = 5
Dout A0
Dout A1
Dout A2
Dout A3
tRC
圳
市
金
DQ
T4
公
CK, CK
CMD
T3
司
T0
，
RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≦ 2 clocks
深
BR-AP5232
44
REV 1.0
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CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Read with Auto-Precharge followed by an Activation to the Same Bank:
RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP ≦ 2 clocks
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK, CK
NOP
NOP
A10 ="high"
NOP
NOP
NOP
AL + BL/2
tRP
51
Auto-Precharge Begins
44
DQS,
DQS
AL = 1
RL = 4
Dout A1
Dout A2
Dout A3 Dout A4
Dout A5
Dout A6
Dout A7
：
Dout A0
71
CL = 3
DQ
Bank
Activate
NOP
9
NOP
81
Posted CAS
READ w/AP
CMD
85
，
QQ
>= tRTP
BR-AP413(8)2
43
41
5
second 4-bit prefetch
first 4-bit prefetch
Burst Read with Auto-Precharge followed by an Activation to the Same Bank:
T1
T2
T3
T4
T5
T6
T7
T8
，
T0
18
66
RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks
Posted CAS
READ w/AP
NOP
A10 ="high"
讯
科
AL = 1
NOP
NOP
NOP
Bank
Activate
NOP
Auto-Precharge Begins
CL = 3
RL = 4
Dout A0
tRTP
Dout A1
Dout A2
Dout A3
tRP
BR-AP4133
first 4-bit prefetch
深
圳
市
金
合
DQ
NOP
AL + tRTP + tRP
技
有
DQS,
DQS
NOP
限
CMD
公
司
CK, CK
45
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM
automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR),
programmed
in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of
the write burst may be reactivated if the following two conditions are satisfied.
(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.
Examples:
T2
T3
T4
T5
T6
T7
：
T1
QQ
T0
71
44
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4
51
81
9
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
WRITE
w/AP
CMD
NOP
NOP
NOP
NOP
NOP
NOP
43
41
5
A10 ="high"
85
，
CK, CK
Completion of the Burst Write
DQS,
DQS
18
66
DQ
Auto-Precharge Begins
WR
WL = RL-1 = 2
Bank A
Activate
NOP
tRP
tDAL
DIN A0 DIN A1 DIN A2 DIN A3
司
，
tRCmin.
>=tRASmin.
限
公
BW-AP223
T
3
T
4
T
5
合
CK, CK
CMD
NOP
NOP
NOP
市
金
Posted CAS
WRITE w/AP
A10 ="high"
深
圳
DQS,
DQS
T
6
T
7
T
8
T
9
T12
讯
科
T
0
技
有
Burst Write with Auto-Precharge (tWR + tRP Limit) : WL = 4, tDAL = 6 (tWR = 3, tRP = 3), BL = 4
DQ
NOP
NOP
NOP
NOP
Bank A
Activate
Completion of the Burst Write
Auto-Precharge Begins
tWR
WL = RL-1 = 4
DIN
A0
DIN
A1
DIN
A2
tRP
tDAL
DIN
A3
>=tRC
>=tRAS
BW-AP423
46
REV 1.0
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CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Precharge & auto precharge clarification
From
Minimum Delay between "From
To Command
Command
tCK
1,2
Precharge All
AL + BL/2 + max(RTP,2) - 2
tCK
1,2
Precharge ( to same Bank as Read wAP) AL + BL/2 + max(RTP,2) - 2
tCK
1,2
Precharge Al
AL + BL/2 + max(RTP,2) - 2
tCK
Precharge (to same Bank as Write)
WL + BL/2 + tWR
Precharge Al
WL + BL/2 + tWR
tCK
2
tCK
2
1
tCK
2
1
tCK
2
1
tCK
2
85
，
Precharge Al
Note:
18
66
1) RTP [cycles] = RU {tRTP(ns)/tCK(ns)}, where RI stands for round up.
43
41
5
Precharge
Precharge All
81
2
1
Precharge Al
51
tCK
WL + BL/2 + WR
Precharge (to same bank as Precharge)
Precharge
2
2
：
Precharge Al
tCK
1,2
tCK
Precharge (to same bank as Write w/AP) WL + BL/2 + WR
Write w/AP
9
AL + BL/2 + max(RTP,2) - 2
44
Write
Note
Precharge (to same Bank as Read)
71
Read w/AP
Units
QQ
Read
command" to "to command"
2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge
，
all, issued to that bank. The precharge period is satisfied after tRP or tRPa depending on the latest precharge command issued to that
深
圳
市
金
合
讯
科
技
有
限
公
司
bank.
47
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Refresh
SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an
explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows
into the rolling 64 ms interval defined the average refresh interval t REFI, which is a guideline to controlles for distributed
refresh timing. For example, a 1Gbit DDR2 SDRAM has 8392 rows resulting in a tREFI of 7.8 µs.
9
Auto-Refresh Command
81
Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued
51
each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the
44
address bits ”Don‟t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an
71
average periodic interval of tREFI (maximum).
：
When ,  and  are held low and  high at the rising edge of the clock, the chip enters the Auto-Refresh mode.
QQ
All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (t RP) before the Auto-Refresh
85
，
Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the
external address bus is required once this cycle has started.
43
41
5
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the
Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or
18
66
equal to the Auto-Refresh cycle time (tRFC).
，
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval
司
is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the
T1
CK, CK
"high"
Precharge
T3
NOP
> = t RFC
> = t RFC
> = t RP
NOP
AUTO
REFRESH
NOP
AUTO
REFRESH
圳
CMD
市
金
合
CKE
T2
讯
科
T0
技
有
限
公
maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI.
NOP
NOP
ANY
深
AR
48
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Self-Refresh Command
The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the
Self-Refresh mode, the DDR2 SDRAM retains data without external clocking.
The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is
9
defined by having , ,  and  held low with  high at the rising edge of the clock. ODT must be turned off
81
before issuing Self Refresh command, by either driving ODT pin low or using EMRS (1) command. Once the command is
51
registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered
44
Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during
71
Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one
：
clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit
QQ
Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the t XSNR or tXSRD must
85
，
be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit
period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge
43
41
5
during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be
T1
T2
T4
T3
CK/CK
Tm
公
司
tRP*
T5
tis
tis
限
CKE
tis
tAOFD
市
金
合
CMD
Tr
>=tXSRD
>= tXSNR
技
有
讯
科
ODT
Tn
，
T0
18
66
turned off tAOFD before entering Self-Refresh Mode and can be turned on again when the t XSRD timing is satisfied.
Self Refresh
Entry
NOP
CK/CK may
be halted
Non-Read
Command
Read
Command
CK/CK must
be stable
深
圳
* Device must be in theing "All banks idle" state to enter Self Refresh mode.
* ODT must be turned off prior to entering Self Refresh mode.
* tXSRD (>=200 tCK) has to be satisfied for a Read or as Read with Auto-Precharge commend.
* tXSNR has to be satisfied for any command execept Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns.
* The minium CKE low time is defined by the tCKEmin. timming paramester.
* Since CKE is an SSTL input, VREF must maintained during Self-Refresh.
49
REV 1.0
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CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Power-Down
Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not
allowed to go low while mode register or extended mode register command time, or read or write operation is in progress.
CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is
in progress, but power-down IDD specification will not be applied until finishing those operations.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down
9
mode for proper read operation.
81
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down
51
occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two
44
different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to “low” this mode
71
is referred as “standard active power-down mode” and a fast power-down exit timing defined by the tXARD timing parameter
：
can be used. When A12 is set to “high” this mode is referred as a power saving “low power active power-down mode”. This
QQ
mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied.
85
，
Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled
upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active
In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2
43
41
5
power-down.
SDRAM, and all other input signals are “Don‟t Care”. Power-down duration is limited by 9 times tREFI of the device.
18
66
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A
valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high.
司
，
Power-down exit latencies are defined in the AC spec table of this data sheet.
公
Power-Down Entry
限
Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a
技
有
precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh
command or MRS / EMRS(1) command when tMRD is satisfied.
讯
科
Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until
the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge
合
command is allowed after RL + BL/2 is satisfied.
市
金
Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case
of a write command, active power-down mode entry is allowed then WL + BL/2 + tWTR is satisfied.
圳
In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command
深
has been executed, which WL + BL/2 + WR is starting from the write with Auto-Precharge command. In case the DDR2
SDRAM enters the Precharge Power-down mode.
50
REV 1.0
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CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Examples:
Active Power-Down Mode Entry and Exit after an Activate Command
T0
T1
T2
Tn
Tn+1
Tn+2
CK, CK
CMD
NOP
NOP
Valid
Command
NOP
NOP
NOP
81
9
Activate
tIS
CKE
51
tIS
Act.PD 0
T1
T2
T3
T4
T5
CK, CK
READ
READ w/AP
NOP
NOP
NOP
NOP
，
NOP
CKE
司
CMD
T6
RL + BL/2
NOP
Tn
T8
NOP
NOP
NOP
Tn+1
NOP
Tn+2
Valid
Command
tIS
tIS
CL = 3
RL = 4
tXARD or
tXARDS *)
Dout A0 Dout A1
Dout A2 Dout A3
Active
Power-Down
Entry
Active
Power-Down
Exit
Act.PD 1
深
圳
市
金
合
讯
科
DQ
技
有
AL = 1
限
公
DQS,
DQS
T7
18
66
T0
RL = 4 (AL = 1, CL =3), BL = 4
43
41
5
Active Power-Down Mode Entry and Exit after a Read Burst:
85
，
QQ
：
Active
Power-Down
Exit
Active
Power-Down
Entry
71
44
tXARD or
tXARDS *)
51
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Active Power-Down Mode Entry and Exit after a Write Burst:
T0
T1
T2
T3
T4
T5
T6
WL = 2, tWTR = 2, BL = 4
Tn
T7
Tn+1
Tn+2
CK, CK
CMD
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Valid
Command
NOP
tIS
CKE
WL + BL/2 + tWTR
tIS
tWTR
tXARD or
tXARDS *)
DIN
A3
Active
Power-Down
Exit
T3
Tn
CK, CK
Precharge
*)
NOP
NOP
NOP
NOP
tIS
CKE
，
tRP
NOP
Tn+2
Valid
Command
NOP
tIS
tXP
Precharge
Power-Down
Exit
限
公
司
Precharge
Power-Down
Entry
Tn+1
NOP
18
66
CMD
85
，
T2
43
41
5
T1
QQ
Precharge Power Down Mode Entry and Exit
T0
Act.PD 2
：
Active
Power-Down
Entry
51
DIN
A2
44
DQ
DIN
A1
71
DIN
A0
81
WL = RL - 1 = 2
9
DQS,
DQS
PrePD
深
圳
市
金
合
讯
科
技
有
*) "Precharge" may be an external command or an internal
precharge following Write with AP.
52
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No
Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No
Operation Command is registered when  is low with , , and  held high at the rising edge of the clock. A No
Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
81
9
Deselect Command
51
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when  is
44
brought high, the , , and  signals become don‟t care.
：
71
Input Clock Frequency Change
QQ
During operation the DRAM input clock frequency can be changed under the following conditions:
85
，
a) During Self-Refresh operation
43
41
5
b) DRAM is in Precharge Power-down mode and ODT is completely turned off.
The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must
be at a logic “low” state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock
18
66
frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a “high” logic
，
level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL
司
re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the
公
new clock frequency.
技
有
限
Example:
T0
T1
合
CK, CK
CMD
市
金
NOP
深
圳
CKE
讯
科
Input frequency change during Precharge Power-Down mode
T2
NOP
T3
NOP
T4
Tx
NOP
Tx+1
NOP
NOP
Ty
NOP
Ty+1
NOP
tRP
tAOFD
Ty+2
NOP
tXP
Minimum 2 clocks
required before
changing the frequency
Frequency Change
occurs here
Stable new clock
before power-down exit
Tz
Ty+3
DLL
RESET
NOP
Valid
Command
200 clocks
ODT is off during
DLL RESET
Frequ.Ch.
53
REV 1.0
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CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “low” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event
occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the
input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as described the the initialization
sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC
51
81
9
timing parametric table for tdelay specification.
QQ
：
stable clocks
71
44
Asynchronous CKE Low Event
85
，
CK, CK
43
41
5
tdelay
CKE
CKE drops low due to an
asynchronous reset event
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
Clocks can be turned off after
this point
54
REV 1.0
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CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Truth Table
Command Truth Table
CKE
Function
Previous Current
Cycle
(Extended) Mode Register
CS
RAS CAS
WE BA0-BA2 A13-A11 A10 A9 - A0
Notes
Cycle
H
H
L
L
L
L
BA
Auto-Refresh
H
H
L
L
L
H
X
X
Self-Refresh Entry
H
L
L
L
L
H
X
X
Self-Refresh Exit
L
H
H
X
X
X
X
X
Single Bank Precharge
H
H
L
L
H
L
BA
Precharge all Banks
H
H
L
L
H
L
X
Bank Activate
H
H
L
L
H
H
BA
Write
H
H
L
H
L
L
BA
Column
L
Column
1,2,3
Write with Auto-Precharge
H
H
L
H
L
L
BA
Column
H
Column
1,2,3
Read
H
H
L
H
Read with Auto-Precharge
H
H
L
H
No Operation
H
X
L
H
Device Deselect
H
X
H
Power Down Entry
H
L
OP Code
1, 2
X
X
1,7,8
X
L
X
1,2
：
H
X
1
44
71
X
QQ
85
，
51
1,8
Row Address
1,2
Column
L
Column
1,2,3
L
H
BA
Column
H
Column
1,2,3
H
H
X
X
X
X
1
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
1,4
L
H
H
H
H
X
X
X
X
X
X
X
1,4
L
H
H
H
公
，
18
66
BA
司
43
41
5
X
X
H
H
限
1
技
有
L
X
L
H
Power Down Exit
X
81
9
Set
1. All DDR2 SDRAM commands are defined by states of , , , , and CKE at the rising edge of the clock.
讯
科
2. Bank addresses (BAx) determine which bank is to be operated upon. For (E) MRS BAx selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" inspection for
合
details.
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金
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
圳
6. X means "H or L (but a defined logic level)".
深
7. Self refresh exit is asynchronous.
8. Vref must be maintained during Self Refresh operation.
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1Gb DDR2 SDRAM
Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
Command (N) 3
Previous Current
Action (N)
, , , 
Notes
3
Cycle 1
Cycle 1
(N-1)
(N)
L
L
X
Maintain Power-Down
L
H
DESELECT or NOP
Power-Down Exit
L
L
X
Maintain Self Refresh
11, 15, 16
L
H
DESELECT or NOP
44
Self Refresh Exit
4, 5, 9, 16
H
L
DESELECT or NOP
Active Power-Down Entry
H
L
DESELECT or NOP
H
L
AUTOREFRESH
H
H
：
Precharge Power-Down
QQ
Bank(s) Active
71
Self Refresh
Entry
than listed above
Self Refresh Entry
Refer to the Command Truth Table
43
41
5
Any State other
85
，
All Banks Idle
11, 13, 15
9
51
Power-Down
81
Current State 2
4, 8, 11, 13
4,8,10,11,13
4,8,10,11,13
6, 9, 11,13
7
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
18
66
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).
，
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
公
be issued only after tXSRD (200 clocks) is satisfied.
司
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may
限
6. Self Refresh mode can only be entered from the All Banks Idle state.
技
有
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
讯
科
9. Valid commands for Self Refresh Exit are NOP and DESELCT only.
合
10. Power-Down and Self Refresh cannot be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh
"Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions.
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operations are in progress. See section 2.8
11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.
圳
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
深
13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefore limited by the refresh
requirements.
14. CKE must be maintained high while the device is in OCD calibration mode.
15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However DT must be driven high or low in Power Down if
the ODT function is enabled (Bit A2 or A6 set to "1" in MRS(1)).
16. Vref must be maintained during Self Refresh operation
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1Gb DDR2 SDRAM
Operating Conditions
Absolute Maximum DC Ratings
-1.0
Notes
V
1,3
to + 2.3
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5 to + 2.3
V
1,3
VDDL
Voltage on VDDL pin relative to VSS
-0.5 to + 2.3
V
1,3
-0.5 to + 2.3
V
1
-55 to + 100
℃
1, 2
VIN, VOUT Voltage on any pin relative to VSS
TSTG
Storage Temperature
9
Voltage on VDD pin relative to VSS
Units
81
Rating
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
：
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
71
the device. This is a stress rating only and functional operation of the device at these or any other conditions
51
VDD
Parameter
44
Symbol
85
，
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
QQ
maximum rating conditions for extended periods may affect reliability.
43
41
5
3. When VDD, VDDQ, and VDDL are less than 500mV, Vref may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Parameter
Rating
18
66
Symbol
Units
0 to 85 (Standard Grade)
TOPER
Operating Temperature
1, 2
℃
1, 3
司
，
- 40 to 95 (Industrial Grade)
Notes
公
Note:
限
1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
技
有
2. The operation temperature range is the temperature where all DRAM specification will be supported. Outside of this temperature range, even if it is still within the limit of
stress condition, some deviation on portion of operation specification may be required. During operation, the DRAM case temperature must be maintained between 0℃-85 ℃
讯
科
under all other specification parameter. However, in some applications, it is desirable to operate the DRAM up to 95 ℃ case temperature. Therefore, two spec. may exist.
Supporting 0℃-85℃ with full JEDEC AC & DC spec. This is the minimum requirements for all operating temperature options.
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合
This is an optional feature and not required. Supporting 0℃-85℃ and being able to extend to 95℃ with doubling auto-refresh command in frequency to a 32ms period
(tRFI=3.9μs)
圳
Currently the period Self-Refresh interval is hard coded within the DRAM to a vendor specific value. There is a migration plan to support higher temperature Self-Refresh entry
深
via the control of EMRS (2) bit A7.
3. The operation temperature range is the temperature where all DRAM specification will be supported. Outside of this temperature range, even if it is still within the limit of
stress condition, some deviation on portion of operation specification may be required. During operation, the DRAM case temperature must be maintained between -40-95 ℃
under all other specification parameter. However, in some applications, it is desirable to operate the DRAM up to 105 degree C case temperature. Therefore, two spec. may
exist. Supporting -40℃-95℃ and being able to extend to 105℃
57
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
AC & DC Operating Conditions
DC Operating Conditions
Recommended DC Operating Conditions (SSTL_18)
Rating
Notes
1.9
V
1
1.8
1.9
V
1.7
1.8
1.9
Input Reference Voltage
0.49 * VDDQ
0.5 * VDDQ
0.51 * VDDQ
Termination Voltage
VREF - 0.04
VREF
VREF + 0.04
Max.
Supply Voltage
1.7
1.8
VDDDL
Supply Voltage for DLL
1.7
VDDQ
Supply Voltage for Output
VREF
VTT
V
71
5
1,5
V
2, 3
V
4
：
VDD
51
Typ.
9
Units
Min.
81
Parameter
44
Symbol
QQ
1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
85
，
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be
about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
43
41
5
3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to V REF and must
track variations in die dc level of VREF.
18
66
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ, and VDDL tied together.
司
Symbol
min.
nom.
max.
Units
Notes
Rtt1(eff)
60
75
90
ohms
1
Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 150 ohm Rtt2(eff)
120
150
180
ohms
1
Rtt eff. impedance value for EMRS(1)(A6,A2)=1,1; 50 ohm
Rtt3(eff)
40
50
60
ohms
1
Deviation of VM with respect to VDDQ / 2
delta VM
-6
6
%
2
公
Parameter / Condition
，
ODT DC Electrical Characteristic
讯
科
技
有
限
Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm
合
1) Measurement Definition for Rtt(eff):
市
金
Apply VIHac and VILac to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac))
圳
2) Measurement Definition for VM:
深
Measure voltage (VM) at test pin (midpoint) with no load:
delta VM =(( 2* VM / VDDQ) - 1 ) x 100%
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REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
DC & AC Logic Input Levels
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the
EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by
which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are
measured relative to the rising or falling edges of DQS crossing at VREF.
In differential mode, these timing relationships
are measured relative to the cross point of DQS and its complement, DQS. This distinction in timing methods is guaranteed
51
81
9
by design and characterization. In single ended mode, the DQS (and RDQS) signals are internally disabled and don‟t care.
44
Single-ended DC & AC Logic Input Levels
DDR2-667/800/1066
VREF + 0.125
VDDQ + 0.3
V
-0.3
VREF - 0.125
V
DC input logic high
VIL (dc)
DC input low
VIH (ac)
AC input logic high
VREF + 0.200
VDDQ+Vpeak
VIL (ac)
AC input low
VSSQ-Vpeak
VREF - 0.200
Condition
18
66
Single-ended AC Input Test Conditions
Symbol
V
V
43
41
5
VIH (dc)
：
Max.
71
Units
Min.
QQ
Parameter
85
，
Symbol
Input reference voltage
VSWING(max)
Input signal maximum peak to peak swing
SLEW
Input signal minimum slew rate
Units
Notes
0.5 * VDDQ
V
1, 2
1
V
1, 2
1
V / ns
3, 4
公
司
，
VREF
Value
限
1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh.
技
有
2. Input waveform timing is referenced to the input signal crossing through the V REF level applied to the device under test.
3. The input signal minimum slew rate is to be maintained over the range from V IL(dc)max to VIH(ac)min for rising edges and the
讯
科
range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure.
4. AC timings are referenced with input waveforms switching from V IL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
深
圳
市
金
合
VIL(ac) on the negative transitions.
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REV 1.0
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CONSUMER DRAM
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1Gb DDR2 SDRAM
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
min.
max.
Units Notes
0.5
VDDQ
V
1
VID(ac)
AC differential input voltage
VIX(ac)
AC differential cross point input voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
VOX(ac)
AC differential cross point output voltage
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
3
81
9
Notes:
51
1) VID(ac) specifices the allowable DC execution of each input of differential pair such as CK, , DQS, , LDQS, , UDQS, and
44
.
2) VIX(ac) specifices the input differential voltage lVTR-VCPl required for switching, where VTR is the true input (such as CK, DQS, LDQS, or
：
71
UDQS) level and VCP is the complementary input (such , , , or  ) level. The minimum value is equal to VIH(DC) - VIL(DC).
QQ
3) The typical value of VOX(AC) is expected to be about 0.5VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ.
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
VOX(AC) indicates the voltage at which differential signals must cross.
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REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Output Buffer Levels
Output AC Test Conditions
Symbol
VOTR
Parameter
SSTL-18 Class II
Units
Notes
0.5 * VDDQ
V
1
Output Timing Measurement Reference Level
1. The VDDQ of the device under test is referenced.
SSTL-18
Units
mA
Output Minimum Source DC Current, nominal
-13.4
IOL(dc)
Output Minimum Sink DC Current, nominal
13.4
1, 3, 4
mA
2, 3, 4
：
IOH(dc)
Notes
44
Parameter
71
Symbol
51
81
9
Output DC Current Drive
3.
280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV.
85
，
2. VDDQ = 1.7 V; VOUT =
QQ
1. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV.
The dc value of VREF applied to the receiving device is set to VTT
43
41
5
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to
ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values
18
66
are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement.
OCD Default Setting Table
Description
，
Symbol
Pull-up / Pull down mismatch
-
Output Impedance step size for OCD calibration
公
限
Output Slew Rate
Nominal
Max.
Unit
Notes
0
-
4
Ohms
6
0
-
1.5
Ohms
1,2,3
1.5
-
5
V / ns
1,4,5,7,8
技
有
SOUT
司
-
Min.
1) Absolute Specification: TOPEN; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V.
讯
科
2) Impedance measurement condition for output source dc current: VDDQ = 1.7V, VOUT = 1420 mV; (VOUT-VDDQ)/IOH must be less than 23.4 ohms for
values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280mV; VOUT / IOL
Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage.
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3)
合
must be less than 23.4 ohms for values of VOUT between 0V and 280 mV.
4) Slew rates measured from VIL(AC) to VIH(AC) with the load specified in Section 8.2.
圳
5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is
深
guaranteed by design and characterization.
6) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM
uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 ohms under nominal conditions.
7) DRAM output slew rate specification applies to 533MT/s, 667MT/s, and 800MT/s speed pin.
8) Timing skew due to DRAM output slew rate mis-match between DQS /  and associated DQ's is included in tDQSQ and tQHS specification.
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1Gb DDR2 SDRAM
Default Output V-I Characteristics
DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS (1) bits
A7~A9 = ‟111‟. The driver characteristics evaluation conditions area) Nominal Default 25℃ (Tcase), VDDQ=1.8V, typical
process. b) Minimum TOPER(max), VDDQ=1.7V, slow-slow process. c) Maximum 0℃ (Tcase), VDDQ=1.9V, fast-fast
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
44
51
81
9
process
62
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Full Strength Default Pullup Driver Characteristics
Minimum
Nomal Default low
Nomal Default high
Maximum
(23.4 Ohms)
(18 Ohms)
(18 Ohms)
(12.6 Ohms)
0.0
0.00
0.00
0.00
0.00
0.1
-4.30
-5.65
-5.90
-7.95
0.2
-8.60
-11.30
-11.80
-15.90
0.3
-12.90
-16.50
-16.80
-23.85
0.4
-16.90
-21.20
-22.10
-31.80
0.5
-20.05
-25.00
-27.60
-39.75
0.6
-22.10
-28.30
-32.40
-47.70
0.7
-23.27
-30.90
-36.90
-55.55
0.8
-24.10
-33.00
-40.90
0.9
-24.73
-34.50
-44.60
1.0
-25.23
-35.50
-47.70
-75.35
1.1
-25.65
-36.10
-50.40
-80.35
1.2
-26.02
-36.60
-52.60
-84.55
1.3
-26.35
-36.90
-54.20
-87.95
1.4
-26.65
-37.10
-55.90
-90.70
1.5
-26.93
-37.40
-57.10
-93.00
1.6
-27.20
-58.40
-95.05
1.7
-27.46
-37.70
-59.60
-97.05
1.8
-
-37.90
-60.90
-99.05
-
-
-101.05
81
51
44
71
：
-62.95
QQ
85
，
43
41
5
18
66
，
司
公
限
-
技
有
1.9
-37.60
9
Voltage (V)
-69.55
The driver characteristics evaluetion conditions are:
讯
科
Nominal Default 25℃ (Tcase) , VDDQ = 1.8 V, typical process
Minimum Toper(max.), VDDQ = 1.7V, slow-slow process
深
圳
市
金
合
Maximum 0 ℃ (Tcase). VDDQ = 1.9 V, fast-fast process
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
44
51
81
9
1Gb DDR2 SDRAM
64
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Minimum
Nomal Default low
Nomal Default high
Maximum
(23.4 Ohms)
(18 Ohms)
(18 Ohms)
(12.6 Ohms)
0.0
0.00
0.00
0.00
0.00
0.1
4.30
5.65
5.90
7.95
0.2
8.60
11.30
11.80
15.90
0.3
12.90
16.50
16.80
23.85
0.4
16.90
21.20
22.10
31.80
0.5
20.05
25.00
27.60
39.75
0.6
22.10
28.30
32.40
47.70
0.7
23.27
30.90
36.90
0.8
24.10
33.00
40.90
0.9
24.73
34.50
44.60
1.0
25.23
35.50
1.1
25.65
36.10
1.2
26.02
36.60
1.3
26.35
36.90
1.4
26.65
37.10
43
41
5
1.5
26.93
1.6
27.20
1.7
27.46
1.8
-
1.9
限
Full Strength Default Pulldown Driver Characteristics
52.60
84.55
54.20
87.95
55.90
90.70
37.40
57.10
93.00
37.60
58.40
95.05
37.70
59.60
97.05
37.90
60.90
99.05
-
-
101.05
18
66
81
51
44
71
：
69.55
85
，
QQ
62.95
75.35
，
司
公
55.55
47.70
50.40
80.35
技
有
-
9
Voltage (V)
The driver characteristics evaluetion conditions are:
讯
科
Nominal Default 25℃ (Tcase) , VDDQ = 1.8 V, typical process
Minimum Toper(max.), VDDQ = 1.7V, slow-slow process
深
圳
市
金
合
Maximum 0 ℃ (Tcase). VDDQ = 1.9 V, fast-fast process
65
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
71
44
51
81
9
1Gb DDR2 SDRAM
QQ
：
Calibrated Output Driver V-I Characteristics
85
，
DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure
outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable
43
41
5
for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high
values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact
nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real
18
66
system calibration error needs to be added to these values. It must be understood that these V-I curves are represented
here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this a
，
system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the DRAM
司
portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to
公
operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters
限
in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated
技
有
between the minimum and maximum default values at all times. If this can‟t be guaranteed by the system calibration
讯
科
procedure, re-calibration policy and uncertainty with DQ to DQ variation, it is recommend that only the default values to be
used. The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result
合
of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an
深
圳
versa.
市
金
extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice
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1Gb DDR2 SDRAM
Full Strength Calibrated Pulldown Driver Characteristics
Nominal
Nominal
Nomal Low
Nomal High
Minimum
Maximum
(18.75 Ohms) (18 ohms)
(17.25 Ohms)
(21 Ohms)
(15 Ohms)
9.5
10.7
11.5
11.8
13.3
0.3
14.3
16.0
16.6
17.4
20.0
0.4
18.7
21.0
21.6
23.0
27.0
81
0.2
9
Voltage (V)
Nominal
51
The driver characteristics evaluetion conditions are:
44
Nominal 25℃ (Tcase) , VDDQ = 1.8 V, typical process
71
Nominal Low and Nominal High 25℃ (Tcase), VDDQ = 1.8V, any process
0℃(Tcase), VDDQ = 1.9 V, any process
85
，
Full Strength Calibrated Pullup Driver Characteristics
Nominal
Nomal Low
Nominal
Minimum
(18.75 Ohms) (18 ohms)
(21 Ohms)
-9.5
-10.7
-11.4
0.3
-14.3
-16.0
-16.6
0.4
-18.7
-21.0
-21.6
-11.8
-13.3
-17.4
-20.0
-23.0
-27.0
司
Nominal 25℃ (Tcase) , VDDQ = 1.8 V, typical process
(15 Ohms)
，
The driver characteristics evaluetion conditions are:
Maximum
(17.25 Ohms)
18
66
0.2
Nominal
Nomal High
43
41
5
Voltage (V)
QQ
Nominal Maximum
：
Nominal Minimum Toper(max), VDDQ = 1.7 V, any process
限
公
Nominal Low and Nominal High 25℃(Tcase), VDDQ = 1.8V, any process
0℃ (Tcase), VDDQ = 1.9 V, any process
深
圳
市
金
合
讯
科
Nominal Maximum
技
有
Nominal Minimum Toper(max), VDDQ = 1.7 V, any process
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1Gb DDR2 SDRAM
Input/Output Capacitance
-3C/-3CI
Symbol
CCK
-AC/-ACI
-BD
Parameter
Units
Input capacitance, CK and 
min.
max.
min.
max.
min.
max.
1.0
2.0
1.0
2.0
1.0
2.0
pF
-
0.25
-
0.25
-
0.25
pF
1.0
2.0
1.0
1.75
1.0
1.75
pF
-
0.25
-
0.25
-
0.25
pF
2.5
3.5
2.5
3.5
2.5
3.5
-
0.5
-
0.5
-
Input capacitance delta, CK
CDCK
and 
81
9
Input capacitance, all other
CI
0.5
pF
pF
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
DQ, DM, DQS, 
85
，
Input/output capacitance delta,
CDIO
QQ
DQ, DM, DQS, 
：
Input/output capacitance,
CIO
71
other input-only pins
44
Input capacitance delta, all
CDI
51
input-only pins
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1Gb DDR2 SDRAM
Power & Ground Clamp V-I Characteristics
Power and Ground clamps are provided on address (A0~A13, BA0, BA1, BA2), , , , WE, CKE, and
Minimum Power
Minimum Ground
clamp (V)
Clamp Current (mA)
Clamp Current (mA)
0.0
0.0
0.0
0.1
0.0
0.0
0.2
0.0
0.0
0.3
0.0
0.0
0.4
0.0
0.0
0.5
0.0
0.0
0.6
0.0
0.0
0.7
0.0
0.0
0.8
0.1
0.1
0.9
1.0
1.0
2.5
1.1
4.7
1.2
6.8
1.3
9.1
1.4
11.0
11.0
13.5
13.5
16.0
16.0
1.7
18.2
18.2
1.8
21.0
21.0
18
66
51
44
71
：
QQ
2.5
，
限
85
，
43
41
5
1.0
4.7
6.8
9.1
深
圳
市
金
合
讯
科
技
有
1.6
公
1.5
81
9
Voltage across
司
ODT pins. The V-I characteristics for pins with clamps is shown in the following table
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1Gb DDR2 SDRAM
IDD Specifications and Measurement Conditions
IDD Specifications
X4/x8
65
70
x16
100
115
X4/x8
75
85
x16
120
130
Operating Current
Unit Notes
TBD
mA
1,2
TBD
mA
1,2
Precharge Power-Down Current
All
7
7
TBD
mA
1,2
IDD2N
Precharge Standby Current
All
30
40
TBD
mA
1,2
IDD2Q
Precharge Quiet Standby Current
All
30
35
TBD
mA
Active Power-Down
MRS(12)=0
All
25
30
TBD
mA
1,2
Standby Current
MRS(12)=1
All
8
8
TBD
mA
1,2
X4/x8
45
50
TBD
mA
1,2
x16
65
75
X4/x8
100
TBD
mA
1,2
x16
150
X4/x8
100
TBD
mA
1,2
TBD
mA
1,2
Operating Current Burst Write
Burst Auto-Refresh Current
85
，
235
160
175
200
210
All
15
15
TBD
mA
1,2
All
7
7
TBD
mA
1,2
X4/x8
210
250
TBD
mA
1,2
x16
260
330
技
有
Distributed Auto-Refresh Current
120
X4/x8
x16
IDD5D
235
限
IDD5B
150
公
x16
1,2
120
，
IDD4W
Operating Current Burst Read
司
IDD4R
Active Standby Current
43
41
5
IDD3P
IDD3N
：
IDD2P
QQ
Operating Current
-BD
81
-AC/-ACI
51
-3C/-3CI
18
66
IDD1
I/O
44
IDD0
Parameter/Condition
71
Symbol
9
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
讯
科
Self-Refresh Current for standard
IDD6
市
金
Operating Current
深
圳
IDD7
合
products
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1Gb DDR2 SDRAM
IDD Measurement Conditions
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
81
51
44
IDD3P(1)
71
IDD3P(0)
：
IDD2Q
QQ
IDD2N
85
，
IDD2P
43
41
5
IDD1
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL =
0; CKE is HIGH,  is HIGH between valid commands;Address bus inputs are SWITCHING,Data bus
inputs are SWITCHING;
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address
inputs are STABLE, Data Bus inputs are FLOATING.
Precharge Standby Current: All banks idle;  is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and
address bus inputs are SWICHTING; Data bus inputs are SWITCHING.
Precharge Quiet Standby Current:All banks idle;  is HIGH; CKE is HIGH; tCK = tCKmin.; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING.
Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address
inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "0"( Fast Power-down Exit);
Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address
inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "1"( Slow Power-down Exit);
Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH;
 is HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs
are SWITCHING.
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK
= tCKmin.; tRAS = tRASmax., tRP = tRPmin., CKE is HIGH,  is HIGH between valid commands;
Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK
= tCKmin.; tRAS = tRASmax., tRP = tRPmin.;CKE is HIGH,  is HIGH between valid commands; Address
inputs are SWITCHING; Data Bus inputs are SWITCHING.
Burst Auto-Refresh Current: tCK = tCKmin.; Refresh command every tRFC = tRFCmin interval; CKE is
HIGH,  is HIGH between valid commands; Other control and adress inputs are SWITCHING; Data bus
inputs
are SWITCHING.
Distributed
Auto-Refresh Current: tCK = tCKmin.; Refresh command every tREFI interval; CKE is HIGH,
9
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
IDD7
Operating Bank Interleave Read Current:
1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin.,
tRC = TRCmin.; tRRD = tRRDmin; tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTS.
2. Timing pattern:
公
司
，
18
66
IDD6
 is HIGH between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs
are SWITCHING.
Self-Refresh Current: CKE <= 0.2V; external clock off, CK and  at 0V; Other control and address inputs
are FLOATING; Data Bus inputs are FLOATING.
技
有
限
- DDR2 -667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
- DDR2 -800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
- DDR2 -1066 6-6-6: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D
3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT
IDD specifications are tested after the device is properly initialized.
IDD parameter are specified with ODT disabled.
Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
Definitions for IDD :
LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.);
STABLE is defined as inputs are stable at a HIGH or LOW level
FLOATING is defined as inputs are VREF = VDDQ / 2
SWITCHING is defined as:
Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control
signals, and
inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including
mask or strobes
5. Timing parameter minimum and maximum values for IDD current measurements are defined in the following table.
深
圳
市
金
合
讯
科
1.
2.
3.
4.
71
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1Gb DDR2 SDRAM
IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
-3C/-3CI
-AC/-ACI
-BD
Units
Latency
CL
5
5
6
tCK(avg)
Clock Cycle Time
tCK
3
2.5
1.875
ns
tRCD
15
12.5
11.25
ns
tRC
60
57.5
56.25
ns
7.5
7.5
7.5
10
10
10
tRASmin
45
45
45
tRASmax
70000
70000
70000
tRP
15
12.5
81
51
Active to Read or Write delay
9
Symble
Parameter
44
Active to Active / Auto-Refresh
x8
tRRD
ns
Refresh parameters
Symbol
Auto-Refresh to Active / Auto-Refresh
1Gb
Unit
All
127.5
ns
司
tRFC
(0℃≦Tcase≦85℃)
7.8
(85℃≦Tcase≦95℃)
3.9
(-40℃≦Tcase≦95℃)
7.8
Standard Grade
tREFI
Industry Grade
μs
μs
深
圳
市
金
合
讯
科
技
有
Average periodic Refresh interval
限
公
command period
ns
Component Type
，
Parameter
11.25
18
66
Precharge Command Period
43
41
5
Active to Precharge Command
QQ
ns
x16
85
，
bank B command delay
：
Active bank A to Active
71
command period
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Electrical Characteristics & AC Timing - Absolute Specification
Timing Parameter by Speed Grade
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
-3C/-3CI
Symbol
-AC/-ACI
-BD
Parameter
Units
Max.
Min.
Max.
Min.
Max.
tCK(avg) Clock cycle time, CL=x, (Average)
3000
8000
2500
8000
1875
8000
ps
tCH(avg) CK, high-level width (Average)
0.48
0.52
0.48
0.52
0.48
0.52
tCK(avg)
tCL(avg) CK, low-level width (Average)
0.48
0.52
0.48
0.52
0.48
0.52
tCK(avg)
DQS latching rising transitions to
tDQSS
-0.25
0.25
-0.25
0.2
-
tDSH
DQS falling edge hold time from CK
0.2
-
0.35
-
-
0.2
-
tCK(avg)
0.2
-
0.2
-
tCK(avg)
0.35
-
0.35
-
tCK(avg)
-
0.35
-
0.35
-
tCK(avg)
0.6
0.4
0.6
0.4
0.6
tCK(avg)
200
-
175
-
125
-
ps
275
-
250
-
200
-
ps
0.6
-
0.6
-
0.6
-
tCK(avg)
tDQSL,H DQS input low (high) pulse width
0.35
tWPST Write postamble
0.4
，
tWPRE Write preamble
Address and control input setup time
tIH
Address and control input hold time
技
有
限
公
tIS
81
tCK(avg)
0.2
18
66
DQS falling edge to CK setup time
51
0.25
司
tDSS
0.25
43
41
5
associated clock edges
85
，
edge
44
-0.25
QQ
RL-1
71
：
nCK
Write command to DQS associated clock
WL
9
Min.
Address and control input pulse width
tIPW
讯
科
(each input)
DQ and DM input setup time
differential
100
-
50
-
0
-
ps
tDH
DQ and DM input hold time
differential
175
-
125
-
75
-
ps
深
圳
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金
合
tDS
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
-3C/-3CI
Symbol
-AC/-ACI
-BD
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
0.35
-
0.35
-
0.35
-
tCK(avg)
-450
450
-400
400
-350
350
ps
-400
400
-350
350
-350
350
ps
-
tAC,max
-
tAC,max
-
tAC,max
DQ and DM input pulse width
tDIPW
tDQSCK DQS output access time from CK / 
Data-out high-impedance time from CK /
ps
71
tHZ
51
81
DQ output access time from CK / 
44
tAC
9
(each input)
tAC,min
DQS-DQ skew
-
240
(for DQS & associated DQ signals)
Min
Clock half period
(tCH(avg)
-
tCL(avg) )
-
，
Data hold skew factor
司
tQHS
Read postamble
讯
科
tRPST
公
技
有
tRPRE Read preamble
限
Data output hold time from DQS
340
tQHS
-
ps
250
ps
-
ps
Min
(tCH(avg)
tCL(avg) )
300
tHP -
ps
tHP -
tQHS
tQHS
0.9
1.1
0.9
1.1
0.9
1.1
tCK(avg)
0.4
0.6
0.4
0.6
0.4
0.6
tCK(avg)
7.5
-
7.5
-
7.5
-
ns
10
-
10
-
10
-
ns
37.5
-
35
-
35
-
ns
50
-
45
-
45
-
ns
合
Active bank B
市
金
圳
深
-
175
(1k page size)
x16
command period
tFAW
-
-
x8
Active bank A to
tRRD
(tCH(avg)
tCL(avg) )
tHP -
tQH
200
Min
18
66
tHP
-
ps
tAC,min
43
41
5
tDQSQ
tAC,max
2x
tAC,max
tAC,min
ps
QQ
2x
tAC,max
85
，
2x
tLZ(DQ) DQ low-impedance time from CK /
：
tLZ(DQS) DQS() low-impedance time from CK /  tAC,min tAC,max tAC,min tAC,max tAC,min tAC,max
(2k page size)
x8
(1k page size)
Four Activate Window
x16
(2k page size)
tCCD
 A to B command period
2
-
2
-
2
-
nCK
tWR
Write recovery time
15
-
15
-
15
-
ns
74
REV 1.0
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
-3C/-3CI
Symbol
-AC/-ACI
Units
Min.
Auto-Precharge write recovery
Max.
WR +
Min.
+ precharge time
tnRP
Min.
Max.
WR +
-
tnRP
-
nCK
tnRP
7.5
-
7.5
-
7.5
-
ns
7.5
-
7.5
-
7.5
-
ns
3
-
3
-
3
-
9
Internal Write to Read command delay
Max.
WR +
tDAL
tWTR
-BD
Parameter
10
tXSRD Exit Self-Refresh to Read command
200
-
200
2
-
2
2
-
Exit power down to any valid command
Exit active power-down mode to Read
tXARDS
7-AL
command (slow exit, lower power)
2
44
200
-
nCK
3
-
nCK
-
3
-
nCK
-
-
8-AL
-
10-AL
-
nCK
2
2
2
2
2
nCK
ODT turn-on
tAC,min tAC,max tAC,min tAC,max tAC,min tAC,max
讯
科
技
有
限
tAON
公
司
，
tAOND ODT turn-on delay
2
18
66
(other than NOP or Deselect)
-
10
43
41
5
command (other than NOP or Deselect)
tXARD
ns
10
Exit precharge power-down to any valid
tXP
tRFC +
-
71
tRFC +
-
：
tRFC +
tXSNR Exit Self-Refresh to non-Read command
nCK
QQ
CKE minimum high and low pulse width
85
，
tCKE
51
delay
81
Internal Read to Precharge command
tRTP
+ 2.575
2x
2x
2x
tCK(avg)
tCK(avg)
tAC,min
+
+2
2.5
tCK(avg)
tAC,min
+
+2
合
市
金
圳
ODT turn-off
深
tAOF
+ 0.7
tAC,min
tAONPD ODT turn-on (Power-Down mode)
tAOFD ODT turn-off delay
+ 0.7
+
tAC,max
tAC,max
+1
+1
+1
2.5
tAC,max
tAC,min
2.5
2.5
tAC,max
tAC,min
+ 0.6
ns
+2
tAC,max
2.5
ns
2.5
tAC,max
tAC,min
+ 0.6
nCK
ns
+ 0.6
75
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
-3C/-3CI
-AC/-ACI
-BD
Parameter
Units
Min.
2.5 x
+
+2
Max.
2.5 x
tCK(avg)
tAC,min
tAOFPD ODT turn-off (Power-Down mode)
Min.
2.5 x
tCK(avg)
tAC,min
Max.
tCK(avg)
tAC,min
+
+2
+
ns
+2
tAC,max
tAC,max
tAC,max
+1
+1
+1
9
Max.
81
Min.
3
-
3
-
2.5
tAXPD ODT power down exit latency
8
-
8
-
11
-
tMRD
Mode register set command cycle time
2
-
2
-
2
-
tMOD
MRS command to ODT update delay
0
12
0
12
0
12
：
ns
OCD drive mode output delay
0
12
0
12
12
ns
-
ns
tIS +
tIS +
Minimum time clocks remain ON after CKE
tDELAY
tCK(avg)
-
tCK(avg)
+ tIH
71
nCK
-
tCK(avg)
+ tIH
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
+ tIH
nCK
tIS +
43
41
5
asynchronously drops LOW
0
85
，
tOIT
nCK
44
tANPD ODT to power down entry latency
QQ
51
Symbol
76
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Reference Load for Timing Measurements
The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not
intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by
a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a
system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line
51
81
9
terminated at the tester electronics. This reference load is also used for output slew rate characterization.
71
Vtt = VDDQ / 2
：
25 Ohm
QQ
DUT
DQ
DQS
DQS
RDQS
RDQS
85
，
CK, CK
44
VDDQ
43
41
5
Timing Reference Points
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
complement (e.g. ) signal.
77
REV 1.0
Dec / 2009
CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Slew rate Measurements
Output Slew rate
With the reference load for timing measurements output slew rate for falling and rising edges is measured between VTT 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS / ) output slew rate is measured
between DQS -  = - 500 mV and DQS -  = + 500 mV. Output slew rate is guaranteed by design, but is not
81
9
necessarily tested on each device.
51
Input Slew rate - Differential signals
44
Input slew rate for differential signals (CK / , DQS / , RDQS / ) for rising edges are measured from CK - =
：
71
-250 mV to CK - = + 500 mV and from CK - CK = +250 mV to CK - CK = - 500mV for falling edges.
QQ
Input Slew rate - Single ended signals
85
，
Input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level: VREF -125
mV to VREF + 250 mV for rising edges and from VREF + 125 mV to VREF - 250 mV for falling edges. For slew rate
43
41
5
definition of the input and data setup and hold parameters see section 8.3 of this datasheet.
Input and Data Setup and Hold Time
18
66
Timing Definition for Input Setup (tIS) and Hold Time (tIH)
Address and control input setup time (t IS) is referenced from the input signal crossing at the V IH(ac) level for a rising signal
，
and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from
公
司
the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test
技
有
t
IS
t
IH
t
IS
t
IH
合
讯
科
CK
限
CK
V DDQ
市
金
V IH(ac) min
V IH(dc) min
深
圳
V REF
V IL(dc) max
V IL(ac) max
V SS
78
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Timing Definition for Data Setup (tDS) and Hold Time (tDH)
DQS
Differential Input
Waveform
DQS
Single-ended Input
Waveform
DQS
DS
t
t
DH
t
DS DH
V DDQ
71
V IH(ac) min
44
t
51
81
9
V REF
：
V IH(dc) min
85
，
QQ
V REF
V IL(dc) max
43
41
5
V IL(ac) max
V SS
18
66
1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at
the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac)
，
level to differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with
司
single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data
公
strobe crossing Vref for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data
技
有
限
strobe crossing Vref for a falling signal applied to the device under test.
2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the
讯
科
VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint
for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled
合
MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing Vref
市
金
for a rising signal and VIH(dc) to the single-ended data strobe crossing Vref for a falling signal applied to the device under
深
圳
test
79
REV 1.0
Dec / 2009
CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Slew Rate Definition for Input and Data Setup and Hold Times
Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min
and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of VIL(dc)max and the first crossing of VIL(ac)max, (fig. A) If the actual signal is always earlier
than the nominal slew rate line between shaded „dc to ac region‟, use nominal slew rate for derating value. If the actual
signal is later than the nominal slew rate line anywhere between shaded „dc to ac region‟, the slew rate of a tangent line to
81
9
the actual signal from the ac level to dc level is used for derating value.(fig.B)
51
Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max
44
and the first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the
71
last crossing of VIH(dc)min and the first crossing of Vref.(fig. A). If the actual signal is always later than the nominal slew
：
rate line between shaded „dc to Vref region‟, use nominal slew rate for derating value. If the actual signal is earlier than the
QQ
nominal slew rate line anywhere between shaded „dc to Vref region‟, the slew rate of a tangent line to the actual signal from
S
t
H
V DDQ
V IH(ac) min
V IH(dc) min
司
dc to Vref
region
限
公
V REF
V IL(dc) max
技
有
dc to Vref
region
t
，
dc to ac
region
H
43
41
5
t
S
18
66
t
85
，
the dc level to Vref level is used for derating value.(fig.B)
dc to ac
region
V SS
Delta TFS
Delta TRH
Delta TRS
Delta TFH
深
圳
市
金
合
讯
科
V IL(ac) max
80
REV 1.0
Dec / 2009
CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
t
S
t
t
H
S
t
H
V DDQ
V IH(ac) min
dc to ac
region
V IH(dc) min
9
dc to Vref
region
81
V REF
VIH(dc)min - VIL(ac)min
Setup Slew Rate =
Delta T RS
VREF - VIL(dc)max
Hold Slew Rate
=
Hold Slew Rate
=
Delta T RH
VIH(dc)min - VREF
85
，
falling signal
Se t u p
t an g e n t
S l e w= R a t e
rising signal
Se t u p
rising signal
[ V I L ( d c ) mfalling
a x signal
T FS
VI L (a c )m a x]
t a n g e n t l i n e [ V I H ( d c ) mrising
i n S l e w= R a t e
signal
D el t a TR S
VI L ( a c)m i n ]
H o l dl e S
w
falling signal
H o l dl e S
w
t an g e n t
R a t e=
li n e
D e l t a
li n e
D e l ta
t an g e n t li n e
R a t e=
D e lt a
[ R EF
T R H
-
V I rising
L ( d c)m a x ]
signal
[ V I H ( d c ) m falling
i n signal
VR EF]
TF H
深
圳
市
金
合
讯
科
技
有
限
公
司
，
Delta T FH
Delta TFH
43
41
5
Delta T FS
Delta TRS
18
66
VIL(dc)max - VIL(ac)max
Delta TRH
QQ
V SS
Delta TFS
71
：
V IL(ac) max
44
V IL(dc) max
dc to ac
region
Setup Slew Rate =
51
dc to Vref
region
81
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Input Setup (tIS) and Hold (tIH) Time DeratingTable
CK,  Differential Slew Rate
(-3C/-3CI/-AC/-ACI/-BD)
Units
94
180
124
210
154
ps
3.50
143
89
173
119
203
149
ps
3.00
133
83
163
113
193
143
ps
2.50
120
75
150
105
180
135
ps
2.00
100
45
130
75
160
105
ps
1.50
67
21
97
51
127
81
ps
1.00
0
0
30
30
60
60
ps
0.90
-5
-14
25
16
55
46
ps
0.80
-13
-31
17
-1
47
29
ps
0.70
-22
-54
8
-24
38
6
0.60
-34
-83
-4
-53
26
-23
0.50
-60
-125
-30
-95
0
-65
0.40
-100
-188
-70
-158
-40
0.30
-168
-292
-138
-262
-108
0.25
-200
-375
-170
-345
0.20
-325
-500
-295
-470
0.15
-517
-708
-487
0.10
-1000
-1125
18
66
-232
ps
-315
ps
-265
-440
ps
-457
-648
ps
-940
-1065
ps
，
-1095
ps
司
-970
ps
ps
公
技
有
-678
ps
-128
-140
81
150
51
4.00
44
D tIH
71
D tIS
：
D tIH
QQ
D tIS
85
，
D tIH
43
41
5
D tIS
9
1.0 V/ns
限
1.5 V/ns
深
圳
市
金
合
讯
科
Command/Address Slew rate (V/ns)
2.0 V/ns
82
REV 1.0
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CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Data Setup (tDS) and Hold Time (tDH) Derating Table
DQS, 
4.0 V/ns
3.0 V/ns
2.0 V/ns
Differential Slew Rate (-3C/-3CI/-AC/-ACI/-BD)
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
45
100
45
100
45
-
-
-
-
-
-
-
-
-
-
-
-
1.5
67
21
67
21
67
21
79
33
-
-
-
-
-
-
-
-
-
-
1.0
0
0
0
0
0
0
12
12
24
24
-
-
-
-
-
-
-
81
-
0.9
-
-
-5
-14
-5
-14
7
-2
19
10
31
22
-
-
-
-
51
-
-
0.8
-
-
-
-
-13
-31
-1
-19
11
-7
23
5
35
17
-
44
-
-
0.7
-
-
-
-
-
-
-10
-42
2
-30
14
-18
26
71
0.6
-
-
-
-
-
-
-
-
-10
-59
2
-47
14
0.5
-
-
-
-
-
-
-
-
-
-
-24
-89
0.4
-
-
-
-
-
-
-
-
-
-
All units in ps.
-
-6
38
6
-
-
：
26
-23
38
-11
-35
QQ
-
-
9
100
-12
-77
0
-65
12
-53
-52
-140
-40
-128
-28
-116
43
41
5
1.
2.0
85
，
DQ Slewrate (V/ns)
D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
2. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table
83
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Overshoot and Undershoot Specification
AC Overshoot / Undershoot Specification for Address and Control Pins
-AC/-ACI
-BD
Units
Maximum peak amplitude allowed for overshoot area
0.5
0.5
0.5
V
Maximum peak amplitude allowed for undershoot area
0.5
0.5
0.5
V
Maximum overshoot area above VDD
0.8
0.66
0.66
V-ns
Maximum undershoot area below VSS
0.8
0.66
0.66
V-ns
51
Maximum Amplitude
44
Overshoot Area
Volts (V)
9
-3C/-3CI
81
Parameter
：
71
VDD
85
，
QQ
VSS
Undershoot Area
18
66
Time (ns)
43
41
5
Maximum Amplitude
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
-3C/-3CI
-AC/-ACI
-BD
Units
Maximum peak amplitude allowed for overshoot area
0.5
0.5
0.5
V
Maximum peak amplitude allowed for undershoot area
0.5
0.5
0.5
V
Maximum overshoot area above VDD
0.23
0.23
0.23
V.ns
0.23
0.23
0.23
V.ns
限
公
司
，
Parameter
深
圳
市
金
合
Volts (V)
讯
科
技
有
Maximum undershoot area below VSS
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Maximum Amplitude
Undershoot Area
Time (ns)
84
REV 1.0
Dec / 2009
CONSUMER DRAM
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NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Package Dimensions
(x4/x8; 60 balls; BGA Package)
60 Ball BGA
8 .00+/-0.10
Pin A1 Index
6 .40
Min0.10
，
18
66
10.00 +/- 0.10
：
43
41
5
85
，
Dia.
Min 0.40
Max0.50
QQ
8 . 00
71
44
0.80
51
81
9
0.80
Min 0.10
0. 10 Max.
0. 40 Max.
0. 25 Min.
1. 20 Max.
技
有
限
公
司
Unit: Millimeters
深
圳
市
金
合
讯
科
Note : All dimensions are typical unless otherwise stated
85
REV 1.0
Dec / 2009
CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Package Dimensions
(X16; 84 balls; BGA Package)
84 Ball BGA
8 .00+/-0.10
Pin A1 Index
6.40
：
12.50 +/- 0.10
QQ
85
，
11. 20
71
44
51
0.80
81
9
0.80
公
司
，
18
66
43
41
5
Dia.
Min 0.40
Max0.50
Min 0.10
限
Min 0.10
0. 10 Max.
0. 40 Max.
0. 25 Min.
1. 20 Max.
Note: All dimensions are typical unless otherwise stated.
深
圳
市
金
合
讯
科
技
有
Unit: Millimeters
86
REV 1.0
Dec / 2009
CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
Revision Log
Date
Modification
0.1
11/2009
Preliminary Release
1.0
12/2009
Official Release
深
圳
市
金
合
讯
科
技
有
限
公
司
，
18
66
43
41
5
85
，
QQ
：
71
44
51
81
9
Rev
87
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
®
Nanya Technology Corporation.
9
All rights reserved.
81
Printed in Taiwan, R.O.C., 2006
51
The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both.
71
：
Other company, product and service names may be trademarks or service marks of others.
44
NANYA and NANYA logo
QQ
NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants
performance of its semiconductor products and related software to the specifications applicable at the time of sale in
85
，
accordance with NTC‟s standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems
necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
43
41
5
those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property
18
66
or environmental damage (“Critical Applications”).
，
NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE
司
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
公
APPLICATIONS.
限
Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in
技
有
such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk
讯
科
applications should be directed to NTC through a local sales office.
In order to minimize risks associated with the customer‟s applications, adequate design and operating safeguards should
合
be provided by customer to minimize the inherent or procedural hazards.NTC assumes no liability of applications
市
金
assistance, customer product design, software performance, or infringement of patents or services described herein. Nor
does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright,
圳
mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in
深
which such semiconductor products or services might be or are used.
NANYA TECHNOLOGY CORPORATION
HWA YA Technology Park, 669, FU HSING 3rd Rd., Kueishan,
Taoyuan, Taiwan, R.O.C.
The NANYA TECHNOLOGY CORPORATION
Home page can be found at http:\\www.nanya.com
88
REV 1.0
Dec / 2009
CONSUMER DRAM
© NANYA TECHNOLOGY CORP. All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.