NTE6860 Integrated Circuit NMOS – FSK Digital Modem, 600bps Description: The NTE6860 is a MOS subsystem in a 24–Lead DIP type plastic package designed to be integrated into a wide range of equipment utilizing serial data communications. The modem provides the necessary modulation, demodulation and supervisory control functions to implement a serial data communications link, over a voice grade channel, utilizing frequency shift keying (FSK) at bit rates up to 600 bps. The NTE6860 can be implemented into a wide range of data handling systems, including stand alone modems, data storage devices, remote data communication terminals and I/O interfaces for minicomputers. N–channel silicon–gate technology permits the NTE6860 to operate using a single–voltage supply and be fully TTL compatible. The modem is compatible with the NTE6860 microcomputer family, interfacing directly with the Asynchronous Communications Interface Adapter to provide low–speed data communications capability. Features: D Originate and Answer Mode D Crystal or External Reference Control D Modem Self Test D Terminal Interfaces TTL–Compatible D Full–Duplex or Half–Duplex Operation D Automatic Answer and Disconnect D Compatible Functions for 100 Series Data Sets D Compatible Functions for 1001A/B Data Couplers Absolute Maximum Ratings: Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Junction–to–Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g. either VSS or VCC). Power Considerations: The average chip–junction temperature, TJ, in °C can be obtained from: 1. TJ = TA + (PD RΘJA) Where: 5 Ambient Temperature, °C TA RΘJA 5 Package Thermal Resistance, Junction to Ambient, °C/W PD 5 PINT + PPORT PINT 5 iCC x VCC, Watts – Chip Internal Power PPORT 5 Port Power Dissipation, Watts – User Determined For most applications PPORT Ơ PINT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between PD and TJ (if PPORT is neglected) is: 2. PD = K B (TJ + 273°C) Solving equations 1 and 2 for K gives: 3. K = PD (TA + 273°C) + RΘJA PD2 Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA. DC Electrical Characteristics: (VCC = 5V ±5%, all voltages referenced to VSS = 0, TA = 0° to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input High Voltage VIH All Inputs Except Crystal 2.0 – VCC V Input Low Voltage VIL All Inputs Except Crystal VSS – 0.80 V Crystal Input Voltage Vin Crystal Input Driven from an External Reference, Input Coupling Capacitor = 200pF, Duty Cycle = 50 ±5% 1.5 – 2.0 VP–P Input Current Iin Vin = VSS All Inputs Except Rx Car, Tx Data, TD, TST, RI, SH – – –0.2 mA – – –1.6 mA – – 1.0 µA RI, SH Inputs Input Leakage Current IIL Vin = 7V, VCC = VSS, TA = +25°C Output High Voltage VOH1 All Outputs Except An Ph and Tx Car, IOH1 = –0.04mA, Load A 2.4 – VCC V Output Low Voltage VOL1 All Outputs Except An Ph and Tx Car, IOL1 = 1.6mA, Load A VSS – 0.40 V VOL2 An Ph, IOL2 = 0, Load B VSS – 0.30 V Output High Current IOH2 An Ph, VOH2 = 0.8V, Load B 0.30 – – mA Input Capacitance Cin f = 0.1Mhz, TA = +25°C – 5.0 – pF Output Capacitance Cout f = 0.1Mhz, TA = +25°C – 10 – pF Transmit Carrier Output Voltage VCO Load C 0.20 0.35 0.50 VRMS Transmit Carrier Output 2nd Harmonic V2H Load C –25 –32 – dB All Inputs Except Crystal, Operating in the Crystal Input Mode; from 10% to 90% Points, Note 2 – – 1.0 µs – – 1.0 µs Ctystal Input, Operating in External Input Reference Mode – – 30 µs – – 30 µs All Outputs Except Tx Car, From 10% to 90% Points – – 5.0 µs – – 5.0 µs – – 340 mW Input Transition Times tr tf tr tf Output Transistion Times tr tf Internal Power Dissipation PINT All Inputs at VSS and All Outputs Open, TA = 0°C Note 2. Maximum Input Transition Times are ≤ 0.1 x Pulse Width or the specified maximum of 1µs, whichever is smaller. Output Test Loads Load A: TTL Output Load for Receive Break, Digital Carrier, Mode, Clear–to–Send, and Receive Data Outputs Load B: Answer Phone Load Test Point RL = 2.67k ±1% VCC CT R1 = 2.5kΩ VI MMD6150 or Equiv Test Point Load C: Transmit Carrier Load 100k RL = 60k ±1% CT MMD7000 or Equiv 100k Simulated TTL Load – + 1.0µF CT 1k NTE778A or Equiv CT = 20pF = total parasitic capacitance, which includes probe, wiring, and load capacitance Pin Connection Diagram VSS 1 24 Rx Data Rx Brk 3 23 CTS 22 ESD An Ph 21 SH Tx Data 2 4 ELS 5 20 DTR ESS 6 19 RI TD 7 Tx Brk 8 Brk R 9 Tx Car 10 18 TST 17 Rx Car 16 ST 15 Mode FO 11 14 Rx Rate VCC 12 13 X’tal 24 13 1 12 1.300 (33.02) Max .520 (13.2) .225 (5.73) Max .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24)