NTE6850 Integrated Circuit NMOS, Asynchronous Communications Interface Adapter Description: The NTE6850 Asynchronous Communications Interface Adapter provides the data formatting and control to interface serial asynchronous data communications information to bus organized systems such as the NTE6800 Microprocessing Unit. The bus interface of the NTE6850 includes select, enable, read/write, interrupt and bus interface logic to allow data transfer over an 8–bit bidirectional data bus. The parallel data of the bus system is serially transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional configuration of the ACIA is programmed via the data bus during system initialization. A programmable control register provides variable word lengths, clock division ratios, transmit control, receive control, and interrupt control. For peripheral or modem operation, three control lines are provided. These lines allow the ACIA to interface directly with the NTE6860 0–600 bps digital modem. Features: D 8–Bit and 9–Bit Transmission D Optional Even and Odd Parity D Parity, Overrun and Framing Error Checking D Programmable Control Register D Optional ÷1, ÷16, and ÷64 Clock Modes D Up to 1.0 Mbps Transmission D False Start Bit Deletion D Peripheral/Modem Control Functions D Double Buffered D One–Stop or Two–Stop Bit Operation Absolute Maximum Ratings: Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7.0V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Thermal Resistance, Junction–to–Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g. either VSS or VCC). Electrical Characteristics: (VCC = 5V ± 5%, VSS = 0, TA = 0° to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input High Voltage VIH VSS+2.0 – VCC V Input Low Voltage VIL VSS–0.3 – VSS+0.8 V Input Leakage Current R/W, CS0, CS1, CS2, Enable, RS, RX D, RX C, CTS, DCD Iin Vin = 0 to 5.25V – 1.0 2.5 µA Hi–Z (Off–State) Input Current D0 – D7 ITSI Vin = 0.4 to 2.4V – 2.0 10.0 µA Output High Voltage D0 – D7 VOH ILoad = 205µA, Enable Pulse Width < 25µs VSS+2.4 – – V ILoad = 100µA, Enable Pulse Width < 25µs VSS+2. – – V Output High Voltage TX Data, RTS Output Low Voltage VOL ILoad = 1.6A, Enable Pulse Width < 25µs – – VSS+0.4 V Output Leakage Current (Off–State) IRQ ILOH VOH = 2.4V – 1.0 10 µA Internal Power Dissipation PINT TA = 0°C, Note 2 – 300 525 mW Internal Input Capacitance D0 – D7 Cin Vin = 0, TA = +25°C, f = 1MHz – 10.0 12.5 pF – 7.0 7.5 pF – – 10 pF – – 5 pF Internal Input Capacitance E, TX CLK, RX CLK, R/W, RS, RX Data, CS0, CS1, CS2, CTS, DCD Output Capacitance RTS, TX Data Cout Vin = 0, TA = +25°C, f = 1MHz Output Capacitance IRQ Note 2. For temperatures less than TA = 0°C, PINT maximum will increase. Serial Data Timing Characteristics: Parameter Data Clock Pulse Width, Low Data Clock Pulse Width, High Data Clock Frequency Symbol PWCL PWCH fC Test Conditions Min Typ Max Unit B16, B64 Modes 600 – 450 ns B1 Mode 900 – 650 ns B16, B64 Modes 600 – 450 ns B1 Mode 900 – 650 ns B16, B64 Modes – – 0.8 MHz B1 Mode – – 500 kHz – – 600 ns Data Clock–to–Data Delay for Transmitter tTDD Receive Data Setup Time tRDS B1 Mode 250 – – ns Receive Data Hold Time tRDH B1 Mode 250 – – ns tR – – 1.2 µs Request–to–Send Delay Time tRTS – – 560 ns Input Rise and Fall Times tr, tf – – 1.0 µs Interrupt Request Release Time or 10% of the pulse width if smaller Bus Timing Characteristics: (VL ≤ 4V, VH ≥ 2.4V, measurement points 0.8V and 2V unless otherwise specified) Parameter Symbol Min Typ Max Unit tcyc 1.0 – 10.0 µs Pulse Width, E Low PWEL 430 – 9500 ns Pulse Width, E High PWEH 450 – 9500 ns Clock Rise and Fall Time tr, tf – – 25 ns Address Hold Time tAH 10 – – ns Address Setup Time Before E tAS 80 – – ns Chip Select Setup Time Before E tCS 80 – – ns Chip Select Hold Time tCH 10 – – ns Read Data Hold Time tDHR 20 – 50 ns Write Data Hold Time tDHW 10 – – ns Output data Delay Time tDHW – – 290 ns Input Data Setup Time tDSW 165 – – ns Cycle Time Test Conditions Note 3 Note 3. The data bus output buffers are no longer sourcing or sinking current by tDHRmax (High Impedance). Pin Connection Diagram VSS Rx Data Cx Clk Tx Clk RTS Tx Data IRQ CS0 CS2 CS1 RS VDD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 24 13 1 12 CTS DCD D0 D1 D2 D3 D4 D5 D6 D7 E R/W 1.300 (33.02) Max .520 (13.2) .225 (5.73) Max .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24)