PC133/PC100 SODIMM M464S3254DTS M464S3254DTS SDRAM SODIMM 32Mx64 SDRAM SODIMM based on 16Mx16, 4Banks, 8K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung M464S3254DTS is a 32M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S3254DTS consists of eight CMOS 16M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S3254DTS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Performance range Part No. M464S3254DTS-L7C/C7C M464S3254DTS-L7A/C7A M464S3254DTS-L1H/C1H M464S3254DTS-L1L/C1L • • • • • Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,250mil), double sided component PIN NAMES PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Back Pin Front Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 51 53 55 57 59 DQ14 DQ15 VSS NC NC 52 54 56 58 60 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 Back Pin DQ46 95 DQ47 97 VSS 99 NC 101 NC 103 105 107 Voltage Key 109 CLK0 62 CKE0 111 VDD VDD 113 64 RAS 66 CAS 115 68 CKE1 117 WE 70 CS0 A12 119 72 *A13 121 CS1 74 CLK1 123 DU 76 VSS VSS 125 78 NC NC 127 80 NC NC 129 82 VDD VDD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 92 VSS VSS 141 DQ20 94 DQ52 143 Max Freq. (Speed) 133MHz@CL=2 133MHz@CL=3 100MHz @ CL=2 100MHz @ CL=3 Front Pin Back DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD Pin Name Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK1 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground SDA Serial data I/O SCL Serial clock DU Don′t use NC No connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ Data input/output Data inputs/outputs are multiplexed on the same pins. Power supply/ground Power and ground for the input buffers and the core logic. 63 VDD/VSS Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 DQM4 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U0 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U4 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 CS U6 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM6 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U1 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U5 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 ~ A12, BA0 & 1 SDRAM U0 ~ U7 RAS SDRAM U0 ~ U7 SCL CAS SDRAM U0 ~ U7 47KΩ WE SDRAM U0 ~ U7 CKE0 SDRAM U0 ~ U3 CKE1 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 CS U7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD WP SA0 SA1 SA2 SDA SDRAM U4 ~ U7 10Ω DQn Every DQ pin of SDRAM U0/U4 VDD CLK0/1 Three 0.1 uF X7R 0603 Capacitors per each SDRAM Vss To all SDRAMs U1/U5 U2/U6 U3/U7 Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 8 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input low voltage VIL -0.3 0 0.8 V 2 Output high voltage VOH 2.4 - - V IOH = -2mA Output low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A12, BA0 ~ BA1) CIN1 25 45 pF Input capacitance (RAS, CAS, WE) CIN2 25 45 pF Input capacitance (CKE0 ~ CKE1) CIN3 15 25 pF Input capacitance (CLK0 ~ CLK1) CIN4 15 21 pF Input capacitance (CS0 ~ CS1) CIN5 15 25 pF Input capacitance (DQM0 ~ DQM7) CIN6 10 12 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 13 18 pF Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P ICC2 PS ICC2N ICC2NS ICC3P ICC3 PS ICC3N ICC3NS Version Test Condition Burst length = 1 tRC ≥ tRC(min) IO = 0 mA -7C -7A -1H -1L 560 520 520 520 CKE ≤ VIL(max), tCC = 10ns 16 CKE & CLK ≤ VIL(max), tCC = ∞ 16 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 160 Unit Note mA 1 mA mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 80 CKE ≤ VIL(max), tCC = 10ns 48 CKE & CLK ≤ VIL(max), tCC = ∞ 48 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 240 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 200 mA mA ICC4 IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs 680 680 640 640 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 1000 920 880 880 mA 2 Self refresh current ICC6 CKE ≤ 0.2V Operating current (Burst mode) C 24 mA L 12 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Z0 = 50Ω Output 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -7C -7A -1H -1L Unit Note Row active to row active delay tRRD(min) 15 15 20 20 ns 1 RAS to CAS delay tRCD(min) 15 20 20 20 ns 1 Row precharge time tRP(min) 15 20 20 20 ns 1 Row active time tRAS(min) 45 45 50 50 ns 1 tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to Active delay 100 ns 1 2 CLK 2, 5 tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 CAS latency=3 2 ea 4 CAS latency=2 1 Number of valid output data 60 65 us 70 70 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter -7C Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 7.5 Max 1000 7.5 tSAC CAS latency=2 CAS latency=3 -7A tOH CAS latency=2 Min 7.5 -1H Max 1000 10 -1L Min 10 Max 1000 10 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 5.4 5.4 6 6 5.4 6 6 7 3 3 3 3 3 3 3 3 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 2 2 ns 3 Input hold time tSH 0.8 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.4 5.4 6 6 5.4 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H BA0,1 L H L H H H H X X X X L H H X V Read & column address H X L H L H X V Precharge Auto precharge enable H X L H L L X Entry H X L H H L X H X L L H L X H L Exit L H Entry H L Precharge power down mode Exit L Column address (A0 ~ A8) V L Column address (A0 ~ A8) H All banks Clock suspend or active power down L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row address H Auto precharge enable Bank selection 3 3 L Burst stop 1,2 X X Auto precharge disable Note 3 H Write & column address A12, A11 A9 ~ A0 L Bank active & row addr. Auto precharge disable A10/AP X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.66 (67.56) 2.50 (63.60) 1 59 61 0.91 (23.20) 0.13 (3.30) 143 1.25 2-φ 0.07 (1.80) 1.29 (32.80) 0.18 (4.60) 0.083 (2.10) 0.10 (2.50) 0.79 (20.00) 0.24 (6.0) 0.16 ± 0.039 (4.00 ± 0.10) (31.75) 2-R 0.078 Min (2.00 Min) Z Y 0.15 (3.70) 62 144 0.157 Min (4.00 Min) 0.125 Min (3.20 Min) 0.150 Max (3.80 Max) 0.04 ± 0.0039 (1.00 ± 0.10) 0.16 ± 0.0039 (4.00 ± 0.10) 0.06 ± 0.0039 (1.50 ± 0.1) Detail Z 0.100 Min 60 (2.540 Min) 2 0.024 ± 0.001 (0.600 ± 0.050) 0.008 ±0.006 (0.200 ±0.150) 0.03 TYP (0.80 TYP) Detail Y Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx16 SDRAM, TSOP SDRAM Part No. : K4S561632D Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS M464S3254DTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L • Organization : 32MX64 • Composition : 16MX16 *8 • Used component part # : K4S561632D-TL7C/7A/1H/1L,TC7C/7A/1H/1L • # of rows in module : 2row • # of banks in component : 4 banks • Feature : 1,250 mil height & double sided component • Refresh : 8K/64ms • Contents : Byte#. Function Supported Function described -7C 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 4 5 -7A Hex value -1H -1L -7C -7A -1H Note -1L 128bytes 80h 256bytes (2K-bit) 08h SDRAM 04h # of row address on this assembly 13 0Dh 1 # of column address on this assembly 9 09h 1 # of module Rows on this assembly 2 Row 02h 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 5.4ns 6ns 6ns 54h 54h 60h 60h 2 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General Non parity 00h 7.8us, support self refresh self 82h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 2&3 06h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & 00h redundant addressing +/- 10% voltage tolerance, 0Eh Burst Read Single bit Write precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 10ns 12ns 75h A0h A0h C0h 2 24 SDRAM access time @CAS latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 26 SDRAM access time @CAS latency of 1 - 00h 27 Minimum row precharge time (=tRP) 15ns 20ns 20ns 20ns 0Fh 14h 2 2 14h 14h 28 Minimum row active to row active delay (tRRD) 15ns 15ns 20ns 20ns 0Fh 0Fh 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 45ns 45ns 50ns 50ns 2Dh 2Dh 32h 32h 31 Module Row density 32 Command and Address signal input setup time 20h 20h 2 Row of 128MB 1.5ns 1.5ns 2ns 20h 2ns 15h 15h 33 Command and Address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 34 Data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h Rev. 0.0 Jan. 2002 PC133/PC100 SODIMM M464S3254DTS SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 Data signal input hold time SPD data revision code 63 Checksum for bytes 0 ~ 62 64 -7C -7A 0.8ns 0.8ns Superset information (maybe used in future) 62 65~71 Function Supported Function described Hex value -1H -1L -7C -7A 1ns 1ns 08h 08h - Note -1H -1L 10h 10h 21h 51h 00h Current release Intel spd 1.2B/A - 12h 79h BAh Manufacturer JEDEC ID code Samsung CEh ...... Manufacturer JEDEC ID code Samsung 00h Onyang Korea 01h 72 Manufacturing location 73 Manufacturer part # (Memory module) M 4Dh 74 Manufacturer part # (DIMM configuration) 4 34h 75 Manufacturer part # (Data bits) Blank 20h 76 ...... Manufacturer part # (Data bits) 6 36h 77 ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 3 33h 80 ...... Manufacturer part # (Module depth) 2 32h 81 Manufacturer part # (Refresh, # of banks in Comp. & inter- 5 35h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) S 53h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 7 7 1 1 37h 37h 31h 31h 89 Manufacturer part # (Minimum cycle time) C A H L 43h 41h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Year) - - 3 94 Manufacturing date (Week) - - 3 95~98 Assembly serial # 99~12 Manufacturer specific data (may be used in future) 126 System frequency for 100MHz L/C 4Ch / 43h Blank 20h S 53h D-die (5th Gen.) 44h - - 4 Undefined - 5 100MHz 64h 127 Intel Specification details Detailed 100MHz Information 128+ Unused storage locations Undefined CFh CFh CFh - CDh 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung ′s own purpose. Rev. 0.0 Jan. 2002