PHILIPS PCA8574PW

PCA8574/74A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rev. 02 — 14 May 2007
Product data sheet
1. General description
The PCA8574/74A provide general purpose remote I/O expansion for most
microcontroller families via the two-line bidirectional I2C-bus (serial clock (SCL), serial
data (SDA)).
The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The
PCA8574/74A have low current consumption and include latched outputs with 25 mA high
current drive capability for directly driving LEDs.
The PCA8574/74A also possess an interrupt line (INT) that can be connected to the
interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote
I/O can inform the microcontroller if there is incoming data on its ports without having to
communicate via the I2C-bus.
The internal Power-On Reset (POR) initializes the I/Os as inputs.
2. Features
n
n
n
n
n
n
n
n
n
n
n
400 kHz I2C-bus interface
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
8-bit remote I/O pins that default to inputs at power-up
Latched outputs with 25 mA sink capability for directly driving LEDs
Total package sink capability of 200 mA
Active LOW open-drain interrupt output
8 programmable slave addresses using 3 address pins
Readable device ID (manufacturer, device type, and revision)
Low standby current (10 µA max.)
−40 °C to +85 °C operation
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
n Packages offered: DIP16, SO16, TSSOP16, SSOP20
3. Applications
n
n
n
n
n
LED signs and displays
Servers
Industrial control
Medical equipment
PLCs
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
n Cellular telephones
n Gaming machines
n Instrumentation and test measurement
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA8574D
PCA8574D
SO16
plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
PCA8574AD
PCA8574AD
PCA8574N
PCA8574N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
PCA8574AN
PCA8574AN
PCA8574PW
PCA8574
TSSOP16
SOT403-1
PCA8574APW
PA8574A
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SSOP20
plastic shrink small outline package; 20 leads;
body width 4.4 mm
SOT266-1
PCA8574TS
PCA8574
PCA8574ATS
PCA8574A
5. Block diagram
PCA8574
PCA8574A
INT
INTERRUPT
LOGIC
LP FILTER
AD0
AD1
AD2
SCL
SDA
I2C-BUS
CONTROL
INPUT
FILTER
SHIFT
REGISTER
8 BITS
I/O
PORT
P0 to P7
write pulse
read pulse
VDD
VSS
POWER-ON
RESET
002aac677
Fig 1. Block diagram of PCA8574/74A
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
2 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
write pulse
100 µA
VDD
IOH
Itrt(pu)
D
data from Shift Register
Q
FF
P0 to P7
IOL
CI
S
power-on reset
VSS
D
Q
FF
CI
read pulse
S
to interrupt logic
data to Shift Register
002aac109
Fig 2. Simplified schematic diagram of P0 to P7
6. Pinning information
6.1 Pinning
PCA8574N
PCA8574AN
AD0
1
16 VDD
AD1
2
15 SDA
AD2
3
14 SCL
AD0
1
P0
4
13 INT
AD1
2
16 VDD
15 SDA
P1
5
12 P7
AD2
3
14 SCL
P0
4
P1
5
P2
6
11 P6
P3
7
10 P5
VSS
8
9
P2
P3
VSS
11 P6
6
10 P5
7
9
8
P4
002aac679
Fig 3. Pin configuration for DIP16
PCA8574_PCA8574A_2
Product data sheet
PCA8574D
PCA8574AD
13 INT
12 P7
P4
002aac678
Fig 4. Pin configuration for SO16
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
3 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
INT
1
20 P7
SCL
2
19 P6
18 n.c.
AD0
1
16 VDD
n.c.
3
AD1
2
15 SDA
SDA
4
AD2
3
14 SCL
VDD
5
P0
4
13 INT
AD0
6
P1
5
12 P7
AD1
7
14 P3
P2
6
11 P6
n.c.
8
13 n.c.
P3
7
10 P5
AD2
9
12 P2
VSS
8
P0 10
11 P1
PCA8574PW
PCA8574APW
9
P4
16 P4
15 VSS
002aac680
002aac941
Fig 5. Pin configuration for TSSOP16
17 P5
PCA8574TS
PCA8574ATS
Fig 6. Pin configuration for SSOP20
6.2 Pin description
Table 2.
Pin description for DIP16, SO16, TSSOP16
Symbol
Pin
Description
AD0
1
address input 0
AD1
2
address input 1
AD2
3
address input 2
P0
4
quasi-bidirectional I/O 0
P1
5
quasi-bidirectional I/O 1
P2
6
quasi-bidirectional I/O 2
P3
7
quasi-bidirectional I/O 3
VSS
8
supply ground
P4
9
quasi-bidirectional I/O 4
P5
10
quasi-bidirectional I/O 5
P6
11
quasi-bidirectional I/O 6
P7
12
quasi-bidirectional I/O 7
INT
13
interrupt output (active LOW)
SCL
14
serial clock line
SDA
15
serial data line
VDD
16
supply voltage
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
4 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
Table 3.
Pin description for SSOP20
Symbol
Pin
Description
INT
1
interrupt output (active LOW)
SCL
2
serial clock line
n.c.
3
not connected
SDA
4
serial data line
VDD
5
supply voltage
AD0
6
address input 0
AD1
7
address input 1
n.c.
8
not connected
AD2
9
address input 2
P0
10
quasi-bidirectional I/O 0
P1
11
quasi-bidirectional I/O 1
P2
12
quasi-bidirectional I/O 2
n.c.
13
not connected
P3
14
quasi-bidirectional I/O 3
VSS
15
supply ground
P4
16
quasi-bidirectional I/O 4
P5
17
quasi-bidirectional I/O 5
n.c.
18
not connected
P6
19
quasi-bidirectional I/O 6
P7
20
quasi-bidirectional I/O 7
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
5 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
7. Functional description
Refer to Figure 1 “Block diagram of PCA8574/74A”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA8574/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of
8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 4 “PCA8574 address map” and Table 5 “PCA8574A address map”.
Remark: When using the PCA8574A, the General Call address (0000 0000b) and the
Device ID address (1111 100Xb) are reserved and cannot be used as device address.
Failure to follow this requirement will cause the PCA8574A not to acknowledge.
slave address
A6
A5
A4
A3
A2
A1
programmable
A0 R/W
002aab636
Fig 7. PCA8574/74A address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 or
PCF8574A is applied.
7.1.1 Address maps
Table 4.
PCA8574 address map
A6
A5
A4
A3
A2
A1
A0
Address
0
1
0
0
0
0
0
20h
0
1
0
0
0
0
1
21h
0
1
0
0
0
1
0
22h
0
1
0
0
0
1
1
23h
0
1
0
0
1
0
0
24h
0
1
0
0
1
0
1
25h
0
1
0
0
1
1
0
26h
0
1
0
0
1
1
1
27h
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
6 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
Table 5.
PCA8574A address map
A6
A5
A4
A3
A2
A1
A0
Address
0
1
1
1
0
0
0
38h
0
1
1
1
0
0
1
39h
0
1
1
1
0
1
0
3Ah
0
1
1
1
0
1
1
3Bh
0
1
1
1
1
0
0
3Ch
0
1
1
1
1
0
1
3Dh
0
1
1
1
1
1
0
3Eh
0
1
1
1
1
1
1
3Fh
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
The PCA8574/74A’s 8 ports (see Figure 2) are entirely independent and can be used
either as input or output ports. Input data is transferred from the ports to the
microcontroller in the Read mode (see Figure 9). Output data is transmitted to the ports in
the Write mode (see Figure 8).
This quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data directions. At power-on the I/Os are HIGH. In this mode only a current
source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising
edges into heavily loaded outputs. These devices turn on when an output is written HIGH,
and are switched off by the negative edge of SCL. The I/Os should be HIGH before being
used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as
inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the
write mode.
Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large
current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last
bit of the byte containing the slave address to logic 0 the write mode is entered. The
PCA8574/74A acknowledges and the master sends the data byte for P7 to P0 and is
acknowledged by the PCA8574/74A. The 8-bit data is presented on the port lines after it
has been acknowledged by the PCA8574/74A.
The number of data bytes that can be sent successively is not limited. The previous data
is overwritten every time a data byte has been sent.
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
7 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
SCL
1
2
3
4
5
6
7
8
9
slave address
data 1
SDA S A6 A5 A4 A3 A2 A1 A0 0
START condition
R/W
data 2
A P7 P6 1 P4 P3 P2 P1 P0 A P7 0 P5 P4 P3 P2 P1 P0 A
P5
acknowledge
from slave
P5
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
data output from port
tv(Q)
DATA 1 VALID
DATA 2 VALID
P5 output voltage
Itrt(pu)
P5 pull-up output current
IOH
INT
td(rst)
002aac120
Fig 8. Write mode (output)
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports.
If the data on the input port changes faster than the master can read, this data may be
lost.
slave address
data from port
SDA S A6 A5 A4 A3 A2 A1 A0 1
START condition
R/W
A
data from port
A
DATA 1
DATA 4
1
P
STOP
condition
acknowledge
from master
acknowledge
from slave
no acknowledge
from master
read from
port
DATA 2
data into
port
DATA 3
th(D)
DATA 4
tsu(D)
INT
tv(Q)
td(rst)
td(rst)
002aac121
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped
at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode).
Input data is lost.
Fig 9. Read input port register
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
8 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset
condition is released and the PCA8574/74A registers and I2C-bus/SMBus state machine
will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset
the device.
8.5 Interrupt output (INT)
The PCA8574/74A provides an open-drain interrupt (INT) which can be fed to a
corresponding input of the microcontroller (see Figure 8, Figure 9, and Figure 10). This
gives these chips a kind of master function which can initiate an action elsewhere in the
system.
An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the
signal INT is valid.
The interrupt disappears when data on the port is changed to the original setting or data is
read from or written to the device which has generated the interrupt.
In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the
write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely
deactivated (HIGH).
The interrupt is reset in the read mode on the rising edge of the read from port pulse.
During the resetting of the interrupt itself, any changes on the I/Os may not generate an
interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as
an INT.
VDD
device 1
device 2
device 8
PCA8574
PCA8574
PCA8574
INT
INT
INT
MICROCOMPUTER
INT
002aac682
Fig 10. Application of multiple PCA8574s with interrupt
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
9 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 11. Bit transfer
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12.)
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mba608
Fig 12. Definition of START and STOP conditions
9.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
10 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 13. System configuration
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
S
START
condition
2
8
9
clock pulse for
acknowledgement
002aaa987
Fig 14. Acknowledgement on the I2C-bus
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
11 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to
P7 are outputs. When used in this configuration, during a write, the input (P0 and P1)
must be written as HIGH so the external devices fully control the input ports. The desired
HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a
read, the logic levels of the external devices driving the input ports (P0 and P1) and the
previous written logic level to the output ports (P2 to P7) will be read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the
microprocessor that there is incoming data or a change of data on its ports without having
to communicate via the I2C-bus.
VDD
VDD
VDD
P0
P1
P2
P3
P4
P5
P6
P7
SDA
SCL
INT
CORE
PROCESSOR
AD0
AD1
AD2
temperature sensor
battery status
control for latch
control for switch
control for audio
control for camera
control for MP3
002aac123
Fig 15. Bidirectional I/O expander application
10.2 High current-drive load applications
The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring
additional drive, two port pins in the same octal may be connected together to sink up to
50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one
octal) can be connected together to drive 200 mA.
VDD
CORE
PROCESSOR
VDD
SDA
SCL
INT
AD0
AD1
AD2
VDD
P0
P1
P2
P3
P4
P5
P6
P7
LOAD
002aac124
Fig 16. High current-drive load application
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
12 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
11. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
−0.5
+6
V
IDD
supply current
-
±100
mA
ISS
ground supply current
-
±400
mA
VI
input voltage
VSS − 0.5
5.5
V
II
input current
-
±20
mA
IO
output current
-
±50
mA
Ptot
total power dissipation
-
400
mW
P/out
power dissipation per output
-
100
mW
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
[1]
[1]
operating
Total package (maximum) output current is 400 mA.
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
13 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
12. Static characteristics
Table 7.
Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
2.3
-
5.5
V
IDD
supply current
Operating mode; no load;
VI = VDD or VSS; fSCL = 400 kHz;
AD0, AD1, AD2 = static H or L
-
200
500
µA
Istb
standby current
Standby mode; no load;
VI = VDD or VSS; fSCL = 0 kHz
-
4.5
10
µA
VPOR
power-on reset voltage
-
1.8
2.0
V
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
−0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 2.3 V
20
35
-
mA
VOL = 0.4 V; VDD = 3.0 V
25
44
-
mA
VOL = 0.4 V; VDD = 4.5 V
30
57
-
mA
IL
leakage current
VI = VDD or VSS
−1
-
+1
µA
Ci
input capacitance
VI = VSS
-
5
10
pF
I/Os; P0 to P7
VOL = 0.5 V; VDD = 2.3 V
[2]
12
26
-
mA
VOL = 0.5 V; VDD = 3.0 V
[2]
17
33
-
mA
VOL = 0.5 V; VDD = 4.5 V
[2]
25
40
-
mA
[2]
-
-
200
mA
−30
−138
−300
µA
−0.5
−1.0
-
mA
input capacitance
[3]
-
2.1
10
pF
output capacitance
[3]
-
2.1
10
pF
3.0
-
-
mA
-
3
5
pF
LOW-level output current
IOL
IOL(tot)
total LOW-level output current
VOL = 0.5 V; VDD = 4.5 V
IOH
HIGH-level output current
VOH = VSS
Itrt(pu)
transient boosted pull-up current VOH = VSS; see Figure 8
Ci
Co
Interrupt INT (see Figure 8 and Figure 9)
IOL
LOW-level output current
Co
output capacitance
VOL = 0.4 V
Inputs AD0, AD1, AD2
VIL
LOW-level input voltage
−0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
−1
-
+1
µA
Ci
input capacitance
-
3.5
5
pF
[1]
The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD).
[2]
Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
[3]
The value is not tested, but verified on sampling basis.
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
14 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
13. Dynamic characteristics
Table 8.
Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Limits are for Fast-mode I2C-bus.
Symbol
Parameter
fSCL
Min
Typ
Max
Unit
SCL clock frequency
0
-
400
kHz
tBUF
bus free time between a STOP and START
condition
1.3
-
-
µs
tHD;STA
hold time (repeated) START condition
0.6
-
-
µs
tSU;STA
set-up time for a repeated START condition
0.6
-
-
µs
tSU;STO
set-up time for STOP condition
0.6
-
-
µs
tHD;DAT
data hold time
0
-
-
ns
0.1
-
0.9
µs
50
-
-
ns
tVD;ACK
data valid acknowledge
tVD;DAT
data valid
Conditions
time[1]
time[2]
tSU;DAT
data set-up time
100
-
-
ns
tLOW
LOW period of the SCL clock
1.3
-
-
µs
tHIGH
HIGH period of the SCL clock
-
-
µs
-
300
ns
0.6
[3][4]
fall time of both SDA and SCL signals
tf
20 +
0.1Cb[5]
0.1Cb[5]
tr
rise time of both SDA and SCL signals
20 +
-
300
ns
tSP
pulse width of spikes that must be suppressed
by the input filter[6]
-
-
50
ns
Port timing; CL ≤ 100 pF (see Figure 8 and Figure 9)
tv(Q)
data output valid time
-
-
4
µs
tsu(D)
data input set-up time
0
-
-
µs
th(D)
data input hold time
4
-
-
µs
Interrupt timing; CL ≤ 100 pF (see Figure 8 and Figure 9)
tv(D)
data input valid time
-
-
4
µs
td(rst)
reset delay time
-
-
4
µs
[1]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[4]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[5]
Cb = total capacitance of one bus line in pF.
[6]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
15 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
(A7)
tLOW
bit 6
(A6)
tHIGH
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
1/f
SCL
SCL
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.
Fig 17. I2C-bus timing diagram
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
16 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
14. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.7
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
2.54
7.62
3.9
3.4
8.25
7.80
9.5
8.3
0.254
2.2
inches
0.19
0.02
0.15
0.055
0.045
0.021
0.015
0.013
0.009
0.86
0.84
0.26
0.24
0.1
0.3
0.15
0.13
0.32
0.31
0.37
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT38-1
050G09
MO-001
SC-503-16
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 18. Package outline SOT38-1 (DIP16)
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
17 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A
X
c
HE
y
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
8
1
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.41
0.40
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT162-1
075E03
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 19. Package outline SOT162-1 (SO16)
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
18 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 20. Package outline SOT403-1 (TSSOP16)
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
19 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
D
SOT266-1
E
A
X
c
y
HE
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0
1.4
1.2
0.25
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
o
0
o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT266-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-152
Fig 21. Package outline SOT266-1 (SSOP20)
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
20 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
16. Soldering
16.1 Introduction
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
16.2 Through-hole mount packages
16.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
16.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
16.3 Surface mount packages
16.3.1 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 22) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
21 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
≥ 350
< 350
< 2.5
235
220
≥ 2.5
220
220
Table 10.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 22. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
22 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
16.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
16.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
16.4 Package related soldering information
Table 11.
Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Through-hole mount
Through-hole-surface
mount
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
CPGA, HCPGA
suitable
−
−
DBS, DIP, HDIP, RDBS, SDIP, SIL
suitable[3]
−
suitable
PMFP[4]
not suitable
not suitable
−
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
23 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
Table 11.
Suitability of IC packages for wave, reflow and dipping soldering methods …continued
Mounting
Package[1]
Soldering method
Wave
Surface mount
HTSSON..T[5],
not suitable
BGA,
LBGA,
LFBGA, SQFP, SSOP..T[5], TFBGA,
VFBGA, XSON
Reflow[2]
Dipping
suitable
−
DHVQFN, HBCC, HBGA, HLQFP,
HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[6]
suitable
−
PLCC[7], SO, SOJ
suitable
suitable
−
not
recommended[7][8]
suitable
−
SSOP, TSSOP, VSO, VSSOP
not
recommended[9]
suitable
−
CWQCCN..L[10],
not suitable
not suitable
−
LQFP, QFP, TQFP
WQCCN..L[10]
[1]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP
Semiconductors sales office.
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with
respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of
the moisture in them (the so called popcorn effect).
[3]
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
[4]
Hot bar soldering or manual soldering is suitable for PMFP packages.
[5]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed
through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C
measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[6]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate
between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the
heatsink surface.
[7]
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint
must incorporate solder thieves downstream and at the side corners.
[8]
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for
packages with a pitch (e) equal to or smaller than 0.65 mm.
[9]
Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely
not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil.
However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate
soldering profile can be provided on request.
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
24 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
17. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
GPIO
General Purpose Input/Output
HBM
Human Body Model
LED
Light Emitting Diode
IC
Integrated Circuit
I2C-bus
Inter-Integrated Circuit bus
ID
Identification
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
PLC
Programmable Logic Controller
PWM
Pulse Width Modulation
RAID
Redundant Array of Independent Disks
SMBus
System Management Bus
18. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA8574_PCA8574A_2
20070514
Product data sheet
-
PCA8574_PCA8574A_1
Modifications:
PCA8574_PCA8574A_1
•
•
Section 2 “Features”, last bullet item: changed “TSSOP20” to “TSSOP16”
•
Section 6.1 “Pinning”: deleted pin configuration for TSSOP20; added pin configuration for
TSSOP16
•
•
•
Table 2 title changed (added TSSOP16)
Table 1 “Ordering information”: changed package from TSSOP20 (SOT360-1) to
TSSOP16 (SOT403-1)
Table 3 title changed (deleted TSSOP20)
Section 14 “Package outline”: changed package from TSSOP20 (SOT360-1) to
TSSOP16 (SOT403-1)
20070117
Product data sheet
PCA8574_PCA8574A_2
Product data sheet
-
-
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
25 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PCA8574_PCA8574A_2
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 02 — 14 May 2007
26 of 27
PCA8574/74A
NXP Semiconductors
Remote 8-bit I/O expander for I2C-bus with interrupt
21. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
8
8.1
8.2
8.3
8.4
8.5
9
9.1
9.1.1
9.2
9.3
10
10.1
10.2
11
12
13
14
15
16
16.1
16.2
16.2.1
16.2.2
16.3
16.3.1
16.3.2
16.3.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 6
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6
I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7
Quasi-bidirectional I/O architecture . . . . . . . . . 7
Writing to the port (Output mode) . . . . . . . . . . . 7
Reading from a port (Input mode) . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interrupt output (INT) . . . . . . . . . . . . . . . . . . . . 9
Characteristics of the I2C-bus. . . . . . . . . . . . . 10
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
START and STOP conditions . . . . . . . . . . . . . 10
System configuration . . . . . . . . . . . . . . . . . . . 10
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application design-in information . . . . . . . . . 12
Bidirectional I/O expander applications . . . . . 12
High current-drive load applications . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Handling information. . . . . . . . . . . . . . . . . . . . 21
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Through-hole mount packages . . . . . . . . . . . . 21
Soldering by dipping or by solder wave . . . . . 21
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 21
Surface mount packages . . . . . . . . . . . . . . . . 21
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23
Package related soldering information . . . . . . 23
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
19
19.1
19.2
19.3
19.4
20
21
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
26
26
26
27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 May 2007
Document identifier: PCA8574_PCA8574A_2