INTEGRATED CIRCUITS PCA9504A Glue chip 4 Product data Supersedes data of 2003 Nov 10 Philips Semiconductors 2004 May 11 Philips Semiconductors Product data Glue chip 4 PCA9504A platforms based on Intel processors and chipsets that require additional external circuitry in order to function properly. It is used on entry servers/workstations (840 and 860 chipsets), high-end desktops (820 and 850 chipsets), as well as mid range (815, 830 and 845 chipsets) and low-end (810 chipset) motherboards. Some of these functionalities include meeting timing specifications, buffering signals, and switching between power wells. The PCA9504A Glue Chip 4 integrates miscellaneous motherboard logic and analog functions into a single, small footprint 56-pin TSSOP device. The Glue Chip 4 typically resides on the motherboard close to the I/O controller Hub (ICH) and is optimized for the Intel 82801BA I/O controller hub (ICH2). FEATURES • Dual, Strapping, Selectable Feature Sets • Audio-disable Circuit • Mute Audio Circuit • 5 V reference generation • 5 V standby reference generation • HD single color LED driver • IDE reset signal generation/PCIRST# buffers • PWROK (PWRGD_3V) signal generation • Power Sequencing / BACKFEED_CUT • Power Supply turn on circuitry • RMSRST# generation • Voltage translation for DDC to VGA monitor • HSYNCH / VSYNCH voltage translation to VGA monitor • 3-state buffers for test • Extra GP Logic gates • Power LED Drivers • Flash FLUSH# / INIT# circuit • 5 V I2C to 3.3 V SMBus conversion to 400 kHz • Requires both 3.3 V and 5.0 V operating voltages • 0 to +70 °C operating temperature range • ESD protection exceeds 1000 V HBM per JESD22-A114 and PIN CONFIGURATION VREF3IN 1 56 GP3_OUT V_5P0_STBY 2 55 GP3_IN V_3P3_STBY 3 54 STRAP GPO_FLUSH_CACHE/GP1_IN 4 53 VCCP_VREF A20M/GP1_INB 5 52 VSYNC_5V INIT/GP1_INA 6 51 HSYNC_5V FLUSH_OUT_CPU/GP1_OUT 7 50 VSYNC_3V INIT_OUT/GP2_OUT 8 49 HSYNC_3V CLK_IN 9 48 REF5V_STBY SEL_33_66 10 47 AUD_SHDN GND 11 46 MUTE_AUD PCIRST 12 PCRIST_OUT 13 AUD_EN 14 • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA • Package offered: TSSOP56 42 RSMRST 41 TEST_EN 3V_DDCSCL 17 40 GRN_LED 5V_DDCSCL 18 39 YLW_LED 3V_DDCSDA 19 38 YLW_BLNK 5V_DDCSDA 20 37 GRN_BLNK 36 SLP_S5 SLP_S3 22 35 SCK_BJT_GATE PS_ON 23 34 PWRGD_3V PRIMARY_HD 25 SCSI 26 The PCA9504A Glue Chip 4 is a highly integrated and cost-efficient custom ASIC that reduces logic part count, overall component cost, and board space requirements for PC designers and manufacturers. The Glue Chip 4 supports the latest generation of high-volume 43 GND IDE_RSTDRV 16 HD_LED 24 DESCRIPTION 44 REF5V AUD_RST 15 CPU_PRESENT 21 750 V CDM per JESD22-C101 45 VREF5IN 33 FPRST 32 PWRGD_PS 31 FLUSH_OUT_FWH SECONDARY_HD 27 30 LATCHED_BACKFED_CUT BACKFEED_CUT 28 29 GND SW00578 ORDERING INFORMATION PACKAGE TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER 56-Pin Plastic TSSOP 0 °C to +70 °C PCA9504ADGG PCA9504ADGG SOT364-1 Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. 2004 May 11 2 Philips Semiconductors Product data Glue chip 4 PCA9504A PIN DESCRIPTION PIN(S) SYMBOL FUNCTION 1 3I VREF3IN 3.3 V input 2 P V_5P0_STBY 5 V system standby power supply 3 P V_3P3_STBY 3 V system standby power supply 4 3IU GPO_FLUSH_CACHE / GP2_IN GPO from SIO / ICH2 / Buffer 2 input 5 REF A20M / GP1_INB A20M signal from ICH2 / NAND 1 input B 6 REF INIT / GP1_INA INIT signal from the ICH2 / Buffer 1 input A 7 5V OD FLUSH_OUT_CPU / GP1_OUT Open drain signal, goes to the CPU / NAND 1 output 8 5V OD INIT_OUT / GP2_OUT Delayed INIT signal into the CPU / Buffer 2 output 9 3I CLK_IN Either 33MHz or 66MHz clock, based on SEL_33_66 pin 10 3IU SEL_33_66 Strapping option for 33MHz or 66MHz CLK_IN 11, 29, 43 G GND Ground 12 3I PCRIST PCI reset signal 13 3O PCRIST_OUT Copy of PCRIST, increased drive-strength 14 3IU AUD_EN Audio enable input (GPO from ICH2 / SIO) 15 3O AUD_RST Audio reset output 16 5O IDE_RSTDRV IDE reset output, 5 V push/pull 17 3IOD 3V_DDCSCL DDCSCL input/output 3.3 V side 18 5IOD 5V_DDCSCL DDCSCL input/output 5 V side 19 3IOD 3V_DDCSDA DDCSDA input/output 3.3 V side 20 5IOD 5V_DDCSDA DDCSDA input/output 5 V side 21 3IU CPU_PRESENT CPU present signal from the processor 22 3I SLP_S3 Signal from ICH2 for transitioning to the S3 power state 23 5V OD PS_ON Power supply turn-on signal 24 5V OD HD_LED Hard drive front panel LED output 25 5IU PRIMARY_HD IDE primary drive active input 26 5IU SCSI SCSI drive active input 27 5IU SECONDARY_HD IDE secondary drive active input 28 5V OD BACKFEED_CUT Signal used for STR circuitry 30 5O LATCHED_BACKFEED_CUT Signal used for STR circuitry 31 5V OD FLUSH_OUT_FWH Open drain signal, goes to the FWH 32 5IU PWRGD_PS Power good signal from power supply 33 5IU FPRST Reset signal from the front panel 34 3O PWRGD_3V 3.3 V power good output 35 5V OD SCK_BJT_GATE Gate signal from the SCK BJT in suspend to RAM 36 3I SLP_S5 Signal from the ICH2 for transitioning to the S5 power state 37 3IU GRN_BLNK Power LED input, from SIO GPIO 38 3IU YLW_BLNK Power LED input, from SIO GPIO 39 5V OD YLW_LED Power LED output 40 5V OD GRN_LED Power LED output 41 5ID TEST_EN Test enable, 100K internal pull-down to GND 42 3O RSMRST Reset for the ICH2 resume well 44 AO REF5V Highest system supply reference voltage 45 5I VREF5IN 5V system primary supply input 46 3IU MUTE_AUD Signal from SIO to mute audio on power up/down 47 5O AUD_SHDN Signal to audio amp to signal shutdown 48 AO REF5V_STBY Highest system standby voltage 49 3I HSYNC_3V HSYNCH input from chipset video 2004 May 11 3 Philips Semiconductors Product data Glue chip 4 PCA9504A PIN DESCRIPTION CONTINUED PIN(S) SYMBOL FUNCTION 50 3I VSYNC_3V VSYNCH input from chipset video 51 5O HSYNC_5V HSYNCH output to monitor 52 5O VSYNC_5V VSYNCH output to monitor 53 AI VCCP_VREF Analog voltage reference for determining INIT/A20M input thresholds 54 3IV/3O STRAP Strapping option for GP or FLUSH mode (internal pull-up resistor) Note 1 55 5I GP3_IN Generic logic gate 3 input 56 5V OD GP3_OUT Generic logic gate 3 output NOTE: 1. The pin is internally pulled up to default to FLUSH mode. TYPE DESCRIPTION 3I 3.3 V input signal 3IU 3.3 V input signal with internal pull-up 5I 5 V input signal 5IU 5 V input signal with internal pull-up 5ID 5 V input signal with internal pull-down P Power (input) G Ground (input) 3O 3.3 V output signal 5O 5 V output signal 3V OD 3.3 V open-drain output signal 5V OD 5 v open-drain output signal AO Analog output AI Analog input 3IOD 3.3 V input/output open-drain 5IOD 5 V input/output open-drain REFL Input voltage levels referenced to VCCP_VREF FUNCTION TABLES Strapping Selection Pin STRAP (pin 54)1 MODE1 PIN NAME & (PIN NUMBER) 1 No connect FLUSH GPO_FLUSH_CACHE (4) 1 No connect FLUSH A20M (5) 1 No connect FLUSH INIT (6) 1 No connect FLUSH FLUSH_OUT_CPU (7) 1 No connect FLUSH INIT_OUT (8) 0 GND GP GP2_IN (4) 0 GND GP GP1_INB (5) 0 GND GP GP1_INA (6) 0 GND GP GP1_OUT (7) 0 GND GP GP2_OUT (8) NOTE: 1. The pin is internally pulled up to default to FLUSH mode. 2004 May 11 4 Philips Semiconductors Product data Glue chip 4 PCA9504A TYPICAL APPLICATION GLUE 4 INPUTS PIN 1 2 3 4 5 6 9 10 12 14 17 18 19 20 21 22 25 26 27 32 33 36 37 38 41 45 46 49 50 53 54 55 FUNCTION VREF3IN 5VSB 3VSB GP2_IN GP1_INB GP1_INA CLK_IN SEL_33_66 PCIRST* AUD_EN 3V_DDCSCL 5V_DDCSCL 3V_DDCSD A 5V_DDCSD A CPU_PRESENT* SLP_S3* PRIMAR Y_HD* SC5I* SECOND AR Y_HD* PWRGD_PS FPRST* SLP_S5* GRN_BLNK YL W_BLNK TEST_EN VREF5IN MUTE_A UD* HSYNCH_3V VSYNCH_3V VCCP_VREF STRAP GP3_IN V_3P3_STBY 1 kΩ 10 kΩ 10 kΩ GLUE CHIP 4 IN IN IN IN GPO_FLUSH_CACHE_PU* H_INIT_PU* P_PCIRST* TP_GLUE4_DDCSOL_3V IN IN IN CK_66M_GLUE IN IN IN IN IN IN VREF3IN 1 GLUE4_VREF5IN_R 2 V_5P0_STBY 17 3V_DDC5CL V_3P3_STBY 3 V_3P3_STBY 26 SCSI IDE_SEC_ACT* 27 SECOND AR Y_HD GPIO_A UD_EN 14 AUD_EN 47 AUD_SHDN TP_GLUE4_TESTEN_41 41 TEST_EN GLUE4_SEL_33_66_R 10 SEL_33–66 20 5V_DDCSD A 32 PWRGD_PS 19 3V_DDC5D A A_3V GLUE_FP_RST_R* REF5V 44 V_REF5V HD_LED 24 HD_LED* PCIRST_OUT 13 P_RST_SLO TS_R* AUD_RST 15 TP_A UD_RST* MUTE_A UD 46 MUTE_A UD_PNI* SCK_BJT_GA TE 35 TP–SCK–BJT_GA TE_ENABLE FLUSH_OUT_FWH 31 TP_GLUE4_FLUSH_OUT_FWH FLUSH_OUT_CPU/GP1_OUT 7 TP_GLUE4_GP1_OUT INIT_OUT/GP2_OUT 8 TP_GLUE4_8 IDE_RSTDR V 16 IDE_RST* BACKFEED_OUT 28 BACKFEED_CUT LATCHED_BACKFEED_OUT 30 VREG_BACKFEED_U4 PWRGD–3V 34 PWRGD_3V PS_ON 23 PS_ON* 33 FPRST 18 5V_DDCSCL SLP_S5* 36 SLP_55 RSMRST 42 RSMRST* SLP_S3* 22 SLP_S3 YL W_LED 39 GPIO_YL W_BLNK_HDR GPIO_GRN_BLNK 37 GRN_BLNK GRN_LED 40 GPIO_GRN_BLNK_HDR GPIO_YL W_BLNK 38 YLW_BLNK HSYNC_5V 51 TP_GLUE4_HSYNC5V TP_GLUE4_HSYNC3V 49 HSYNC_3V VSYNC_5V 52 TP_GLUE4_VSYNC5V TP_GLUE4_VSYNC3V 50 VSYNC_3V AUD_MIDI_OUT_B_PU 5 A20M/GP1_INB STRAP 54 GLUE4_STRAP GP3_OUT 56 PWRGD_PS_BUFF V5REF_SUS 48 REF5V_STBY GND 11 VCCP_VREF 53 VCCP_VREF GND 29 55 GP3_IN GND 43 OUT IN CLK_IN PRIMAR Y_HD PWRGD_PS GLUE4_VREF5IN_R V_5P0_STBY 25 A_5V 45 PCIRST IDE_PRI_ACT* TP_GLUE4_DDCSCL_5V 1 kΩ INIT/GP1_INA CPU_PRESENT TP_GLUE4_DDCSD IN 6 VREF5IN 12 8 NC IN GPO_FLUSH_CACHE/GP2–IN 21 NC IN 4 CPU_PRESENT* TP_GLUE4_DDCSD V_383_STBY V CC 3 V CC IN 100 Ω V_3P3_STBY IN OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT PWRGD_PS HAS WEAK 49.9 kΩ IC INTERNAL PULL–UP 10 kΩ SW01083 Figure 1. Typical application 2004 May 11 5 Philips Semiconductors Product data Glue chip 4 PCA9504A ABSOLUTE MAXIMUM RATINGS1 LIMITS SYMBOL PARAMETER CONDITION MIN UNIT MAX V_5P0_STBY DC 5.0V supply –0.5 +6.0 V V_3P3_STBY DC 3.3V supply –0.5 +6.0 V VI (5V) DC input voltage (5 V pins) Note 2 –0.5 V_5P0_STBY+0.5 V VO (5V) Output voltage range (5 V pins) Note 2 –0.5 V_5P0_STBY+0.5 V VI (3.3V) DC input voltage (3.3 V pins) Note 2 –0.5 V_3P3_STBY+0.5 V VO (3.3V) Output voltage range (3.3 V pins) Note 2 –0.5 V_3P3_STBY+0.5 V SPD Supply power dissipation 100 MW ESD Static Discharge voltage 2000 TSTG Storage temperature range –55 +150 °C TOTR Operating Temperature Range 0 70 °C V NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage rating may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VDD3 DC 3.3 V supply voltage 3.0 3.6 V VDDL DC 2.5 V supply voltage 4.75 5.25 V VI DC input voltage 0 VDD3 V VO DC output voltage 0 TA Operating ambient temperature range in free air 0 2004 May 11 6 VDDL VDD3 +70 V °C Philips Semiconductors Product data Glue chip 4 PCA9504A DC CHARACTERISTICS V_5P0_STBY = 5 V ± 5%; V_3P3_STBY = 3.3 V ± 10% LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C TEST CONDITION MIN TYP UNIT MAX STRAP VIH HIGH-level input voltage 2.0 VIL LOW-level input voltage IIH Input leakage HIGH VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –3 mA IIL Input leakage LOW –88 VIH HIGH-level input voltage 2.0 VIL LOW-level input voltage IIL Input leakage LOW IIH Input leakage HIGH VIH HIGH-level input voltage 2.2 VIL LOW-level input voltage IL Input leakage –1 Hys Input hysteresis 400 VIH HIGH-level input voltage 2.2 VIL LOW-level input voltage IIH Input leakage HIGH IIL Input leakage LOW –1 V 0.8 V 1 µA 0.4 V 2.4 V –26 µA AUD_EN VIL = 0 V V 0.8 V –88 –26 µA –1 1 µA PCIRST V 0.8 V 1 µA mV MUTE_AUD VIL = 0 V V 0.8 V –1 1 µA –88 –26 µA VREF5IN 0.85*V5P 0_STBY VIH HIGH-level input voltage VIL LOW-level input voltage IL Input leakage –1 VIH HIGH-level input voltage 2.2 VIL LOW-level input voltage IL Input leakage V 0.2*V5P 0_STBY V 1 µA VREF3IN –1 V 0.8 V 1 µA PRIMARY_HD VIH HIGH-level input voltage VIL LOW-level input voltage 0.7*5VSB V Hys Input hysteresis IIL Input leakage LOW VIL = 0 V –88 –26 µA IIH Input leakage HIGH VIH = 5VSB –1 1 µA 0.2*5VSB 400 V mV SECONDARY_HD VIH HIGH-level input voltage VIL LOW-level input voltage Hys Input hysteresis IIL Input leakage LOW 2004 May 11 0.7*5VSB V 0.2*5VSB 400 VIL = 0 V –88 7 V mV –26 µA Philips Semiconductors Product data Glue chip 4 PCA9504A LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C TEST CONDITION MIN IIH Input leakage HIGH VIH = 5VSB –1 TYP UNIT MAX 1 µA SCSI VIH HIGH-level input voltage 0.7*5VSB V VIL LOW-level input voltage Hys Input hysteresis IIL Input leakage LOW VIL = 0 V –88 –26 µA IIH Input leakage HIGH VIH = 5VSB –1 1 µA 0.2*5VSB 400 V mV FPRST VIH HIGH-level input voltage 0.7*5VSB V VIL LOW-level input voltage Hys Input hysteresis IIL Input leakage LOW VIL = 0 V –88 –26 µA IIH Input leakage HIGH VIH = 5VSB –1 1 µA 0.2*5VSB 400 V mV PWRGD_PS VIH HIGH-level input voltage VIL LOW-level input voltage 0.7*5VSB V Hys Input hysteresis IIL Input leakage LOW VIL = 0 V –88 –26 µA IIH Input leakage HIGH VIH = 5VSB –1 1 µA 0.2*5VSB 400 V mV GPO_FLUSH_CACHE/GP2_IN VIH HIGH-level input voltage 2.2 V VIL LOW-level input voltage 0.8 V IL Input leakage VIL = 0 V –88 –26 µA IIH Input leakage VIH = 5 V –1 1 µA 2.4 INIT / GP1_INA (GP Mode) VIH HIGH-level input voltage Part is strapped for GP mode VIL LOW-level input voltage Part is strapped for GP mode IL Input leakage Part is strapped for GP mode VCCP_Vref Bias voltage V 0.8 V –1 1 µA GP mode 1.95 2.1 V 1.5 INIT / GP1_INA (Flush Mode) VIH HIGH-level input voltage FLUSH mode VIL LOW-level input voltage FLUSH mode 0.4 V IIL Input leakage FLUSH mode –1 1 µA VCCP_Vref Bias voltage FLUSH mode 0.95 1.1 V 2004 May 11 8 V Philips Semiconductors Product data Glue chip 4 PCA9504A LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C TEST CONDITION MIN TYP UNIT MAX A20M / GP1_INB VIH HIGH-level input voltage FLUSH mode VIL LOW-level input voltage FLUSH mode 1.5 V IIL Input leakage FLUSH mode VCCP_Vref Bias voltage FLUSH mode VIH HIGH-level input voltage GP mode 2.4 VIL LOW-level input voltage GP mode 0.8 V IL Input leakage GP mode –1 1 µA VCCP_Vref Bias voltage GP mode 1.95 2.1 V 0.4 V –1 1 µA 0.95 1.1 V V CLK_IN VIH HIGH-level input voltage 2.2 V VIL LOW-level input voltage Hys Input hysteresis 250 IL Input leakage –1 VIH HIGH-level input voltage 2.0 VIL LOW-level input voltage Hys Input hysteresis 400 IIH Input leakage –1 1 µA IIL Input leakage –88 –26 µA 0.8 V mV 1 µA SEL_33_66 V 0.8 VIL = 0 V V mV SLP_S3 VIH HIGH-level input voltage VIL LOW-level input voltage 2.2 Hys Input hysteresis 400 IL Input leakage –1 VIH HIGH-level input voltage 2.2 VIL LOW-level input voltage Hys Input hysteresis 400 IL Input leakage –1 V 0.8 V mV 1 µA SLP_S5 V 0.8 V mV 1 µA CPU_PRESENT VIH HIGH-level input voltage 2.0 V VIL LOW-level input voltage Hys Input hysteresis IIH Input leakage VIH = 3VSB –1 1 µA IIL Input leakage VIL = 0 V –88 –26 µA 0.8 400 V mV TEST_EN VIH HIGH-level input voltage VIL LOW-level input voltage Hys Input hysteresis IIH Input leakage VIL = 0 V –1 1 µA IIL Input leakage VIH = 5VSB 20 88 µA 2004 May 11 0.7*5VSB V 0.2*5VSB 400 9 V mV Philips Semiconductors Product data Glue chip 4 PCA9504A LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C TEST CONDITION MIN TYP UNIT MAX HSYNC_3V VIH HIGH-level input voltage VIL LOW-level input voltage 2.2 IL Input leakage –1 VIH HIGH-level input voltage 2.2 VIL LOW-level input voltage IL Input leakage –1 VIH HIGH-level input voltage 2.2 VIL LOW-level input voltage IIH Input leakage IIL Input leakage V 0.8 V 1 µA VSYNC_3V V 0.8 V 1 µA GRN_BLNK VIL = 0 V V 0.8 V –1 1 µA –88 –26 µA YLW_BLNK VIH HIGH-level input voltage VIL LOW-level input voltage IIH Input leakage IIL Input leakage 2.0 VIL = 0 V V 0.8 V –1 1 µA –88 –26 µA GP3_IN VIH HIGH-level input voltage VIL LOW-level input voltage IL Input leakage 2.2 –1 V 0.8 V 1 µA 0.4 V AUD_RST VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –3 mA IOZ Off state output current 2.4 –1 V 1 µA 0.4 V AUD_SHDN VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –6 mA IOZ Off state output current 2.4 V –1 1 µA REF5V VOUT5 LOW-level output voltage VREF5in > 1.5 V VREF5in – 0.05 VREF5in + 0.05 V VOUT3 HIGH-level output voltage VREF3in > 1.5 V VREF3in – 0.05 VREF3in + 0.05 V IOUTL Off state output current –20 20 µA REF5V_STBY VOUT5 LOW-level output voltage V_5P0_STBY > 1.5 V V_5P0_STBY – 0.05 V_5P0_STBY + 0.05 V VOUT3 HIGH-level output voltage V_5P0_STBY > 1.5 V V_5P0_STBY – 0.05 V_5P0_STBY + 0.05 V IOUTL Off state output current –20 20 µA 0.4 V 1 µA HD_LED VOL LOW-level output voltage IOZ Off state output current 2004 May 11 IOL = 12 mA –1 10 Philips Semiconductors Product data Glue chip 4 PCA9504A LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C TEST CONDITION MIN TYP UNIT MAX IDE_RSTDRV VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –6 mA IOZ Off state output current 0.4 2.4 –1 V V 1 µA 0.4 V PCIRST_OUT VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –3 mA IOZ Off state output current 2.4 –1 V 1 µA 0.4 V PRWGD_3V VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –3 mA IOZ Off state output current 2.4 –1 V 1 µA 0.4 V 1 µA 0.4 V 1 µA 0.4 V 1 µA 0.4 V 1 µA 0.4 V INIT_OUT / GP2_OUT VOL LOW-level output voltage IOZ Off state output current IOL = 12 mA –1 FLUSH_OUT_CPU / GP1_OUT VOL LOW-level output voltage IOZ Off state output current IOL = 12 mA –1 BACKFEED_CUT VOL LOW-level output voltage IOZ Off state output current IOL = 6 mA –1 FLUSH_OUT_FWH VOL LOW-level output voltage IOZ Off state output current IOL = 6 mA –1 LATCHED_BACKFEED_CUT VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –6 mA IOZ Off state output current 2.4 –1 V 1 µA 0.4 V 1 µA 0.4 V PS_ON VOL LOW-level output voltage IOZ Off state output current IOL = 6 mA –1 RSMRST VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –3 mA IOZ Off state output current –1 1 µA VTRIP 5VSB LOW trip voltage 1.8 3.5 V 0.4 V 1 µA 2.4 V SCK_BJT_GATE VOL LOW-level output voltage IOZ Off state output current 2004 May 11 IOL = 6 mA –1 11 Philips Semiconductors Product data Glue chip 4 PCA9504A LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C TEST CONDITION MIN TYP UNIT MAX 3V_DDCSDA VOL LOW-level output voltage IOL = 6 mA IH Input leakage 5V_DDCSDA = VDD IOZ Off state output current 0.4 V –1 2.5 µA –1 1 µA 0.4 V –1 2.5 µA –1 1 µA 5V_DDCSDA VOL LOW-level output voltage IOL = 6 mA IH Input leakage 3V_DDCSDA = VDD IOZ Off state output current 3V_DDCSCL VOL LOW-level output voltage IOL = 6 mA IH Input leakage 5V_DDCSCL = VDD IOZ Off state output current 0.4 V –1 2.5 µA –1 1 µA 0.4 V –1 2.5 µA –1 1 µA 0.4 V 5V_DDCSCL VOL LOW-level output voltage IOL = 6 mA IH Input leakage 3V_DDCSCL = VDD IOZ Off state output current HSYNC_5V VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –6 mA IOZ Off state output current 3.8 –1 V 1 µA 0.4 V VSYNC_5V VOL LOW-level output voltage IOL = 6 mA VOH HIGH-level output voltage IOH = –6 mA IOZ Off state output current 3.8 –1 V 1 µA GRN_LED / YLW_LED VOL LOW-level output voltage IOZ Off state output current IOL = 24 mA 0.4 V –1 1 µA –1 1 µA GP3_OUT VOL LOW-level output voltage IOZ Off state output current 2004 May 11 IOL = 6 mA 12 Philips Semiconductors Product data Glue chip 4 PCA9504A AC CHARACTERISTICS VCC1 = 3.3 V; VCC = 5.0 V LIMITS SYMBOL Tamb = 0 _C to +70 _C PARAMETER MIN tRESET RSMRST tRESET_FALL RSMRST 4.0 TYP UNITS MAX 100 ms 100 ns tPHL/tPLH Propagation Delay AUD_EN to AUD_RST PCIRST to AUD_RST PCIRST to IDE_RSTDRV PCIRST to PCIRST_OUT 1.0 11.0 ns tPLH/tPHL Propagation Delay MUTE_AUD to MUTE_SHDN 2.5 6.0 ns tPLH/tPHL Propagation Delay PWRGD_PS to PWRGD_3V FPRST to PWRGD_3V 4.5 11.0 ns tPLH/tPHL Propagation Delay HSYNC_3V to HSYNC_5V VSYNC_3V to VSYNC_5V 2.0 5.0 ns tPLH/tPHL Propagation Delay PWRGD_PS to SCK_BJT_GATE FPRST to SCK_BJT_GATE 1.0 6.0 ns tPLZ/tPZL Open Drain Prop Delay PRIMARY_HD to HD_LED PRIMARY_HD to HD_LED PRIMARY_HD to HD_LED 1.0 5.0 ns tPLZ/tPZL Open Drain Prop Delay GP1_INA to GP1_OUT GP2_INA to GP1_OUT 3.0 25.0 ns tPLZ/tPZL Open Drain Prop Delay GP2_IN to GP2_OUT 3.0 7.0 ns tPLZ/tPZL Open Drain Prop Delay GP3_IN to GP3_OUT 1.0 4.0 ns tPLZ/tPZL Open Drain Prop Delay SLP_S3 to BACKFEED_OUT PRWGD_PS to BACKFEED_OUT 1.0 6.0 ns tPLZ/tPZL Open Drain Prop Delay CPU_PRESENT to PS_ON 2.0 10.0 ns tPLZ/tPZL Open Drain Prop Delay SLP_S3 to PS_ON 2.0 10.0 ns tPLZ/tPZL Open Drain Prop Delay BACKFEED_OUT to LATCHED_BACKFEED_OUT 2.0 11.0 ns tPLZ/tPZL Open Drain Prop Delay SLP_S5 to YLW_LED SLP_S5 to GRN_LED YLW_BLNK to YLW_LED GRN_BLNK to GRN_LED 1.0 5.0 ns tPLZ/tPZL Open Drain Prop Delay 3V_DDOSDA to 5V_DDOSDA 3V_DDOSDA to 5V_DDOSDA 1.0 5.0 ns tr, tf Rise and Fall Times HSYNC_5V VSYNC_5V 3.5 tr, tf Rise and Fall Times LATCHED_BACKFEED_OUT 2004 May 11 ns 1.0 13 µs NOTES Philips Semiconductors Product data Glue chip 4 PCA9504A WAVEFORMS VIH INPUT VM INPUT VM VM VIL tPLH tPHL tPLH tPHL VOH OUTPUT VM VM VM OUTPUT VM VM VOL SF01443 SW00720 Waveform 3. Waveform 1. VI VDD INPUT VI INPUT VM GND VM tPLZ GND tPZL VDD tPLZ OUTPUT LOW-to-OFF OFF-to-LOW tPZL VDD OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL VM tPHZ VX tPZH VOL SW00721 tPHZ tPZH Waveform 4. SW00722 Waveform 2. 2004 May 11 14 Philips Semiconductors Product data Glue chip 4 PCA9504A 5V REFERENCE GENERATION Supply REF5V VREF5IN < VREF3IN VREF3IN VREF5IN > VREF3IN VREF5IN 3.3 V VREF3IN 5V VREF5IN 5V 3.3 V REF5V SW00580 Figure 1. REF5V when VREF3IN ramps before VREF5IN 3.3 V VREF3IN 5V VREF5IN 5V REF5V SW00581 Figure 2. REF5V when VREF5IN ramps before VREF3IN 2004 May 11 15 Philips Semiconductors Product data Glue chip 4 PCA9504A 5V STANDBY REFERENCE GENERATION Standby Supply REF5V_STBY V_5PO_STBYtV_3P3_STBY V_3P3_STBY V_5PO_STBYuV_3P3_STBY V_5PO_STBY 3.3 V V_3P3_STBY 5V V_5P0_STBY 5V 3.3 V REF5V_STBY SW00582 Figure 3. REF5V_STBY when V_3P3_STBY ramps before V_5PO_STBY V_3P3_STBY V_5P0_STBY REF5V_STBY SW00583 Figure 4. REF5V_STBY when V_5PO_STBY ramps before V_3P3_STBY 2004 May 11 16 Philips Semiconductors Product data Glue chip 4 PCA9504A FLUSH OUT* / INIT OUT* CIRCUIT V_VCCP 1 kΩ VCC3 1 kΩ 1 kΩ H_INIT_OUT* ICH_A20M* CPU H_FLUSH_OUT_CPU* ICH_INIT* GLUE CHIP H_FLUSH_OUT_FWH* GPO_FLUSH_CACHE* FWH VCCP 50 Ω VCCP_VREF 1 µF 100 Ω SW00584 Figure 5. Block diagram for FLUSH_OUT*/INIT_OUT* circuit Case A20M* GPO FLUSH CACHE* INIT* FLUSH OUT CPU* FLUSH OUT FWH* INIT OUT* 1 1 falling edge 0 0 (for t1) 0 (for t1) 0, Hi-Z, then 0 (delayed by t1-t, then active for 2*t) 2 1 falling edge 1 0 (for t1) 0 (for t1) Hi-Z, 0 (delayed by t1-t, then active for 2*t) 3 X 1 0 Hi-Z Hi-Z 0 4 X 1 1 Hi-Z Hi-Z Hi-Z 5 0 falling edge 1 Hi-Z Hi-Z Hi-Z 6 0 falling edge 0 Hi-Z Hi-Z 0 NOTE: 1. Nominal value timings with tolerances are listed in the DC Characteristics table for t and t1. All Hi-Z outputs are shown as 1’s or HIGH in the following diagrams. 2004 May 11 17 Philips Semiconductors Product data Glue chip 4 PCA9504A A20M* GPO_FLUSH_CACHE* INIT* t1 FLUSH_OUT_CPU* t1 FLUSH_OUT_FWH* t t INIT_OUT* SW00585 Figure 6. Waveforms for Case 1 A20M* GPO_FLUSH_CACHE* INIT* t1 FLUSH_OUT_CPU* t1 FLUSH_OUT_FWH* t t INIT_OUT* SW00586 Figure 7. Waveforms for Case 2 2004 May 11 18 Philips Semiconductors Product data Glue chip 4 PCA9504A A20M* GPO_FLUSH_CACHE* INIT* FLUSH_OUT_CPU* FLUSH_OUT_FWH* INIT_OUT* SW00587 Figure 8. Waveforms for Case 3 A20M* GPO_FLUSH_CACHE* INIT* FLUSH_OUT_CPU* FLUSH_OUT_FWH* INIT_OUT* SW00588 Figure 9. Waveforms for Case 4 2004 May 11 19 Philips Semiconductors Product data Glue chip 4 PCA9504A A20M* GPO_FLUSH_CACHE* INIT* FLUSH_OUT_CPU* FLUSH_OUT_FWH* INIT_OUT* SW00589 Figure 10. Waveforms for Case 5 A20M* GPO_FLUSH_CACHE* INIT* FLUSH_OUT_CPU* FLUSH_OUT_FWH* INIT_OUT* SW00590 Figure 11. Waveforms for Case 6 2004 May 11 20 Philips Semiconductors Product data Glue chip 4 PCA9504A A20M* GPO_FLUSH_CACHE* t1 INIT* t1 FLUSH_OUT_CPU* t1 FLUSH_OUT_FWH* t t INIT_OUT* t SW00591 Figure 12. Waveforms for Case 7 A20M* GPO_FLUSH_CACHE* INIT* t1 FLUSH_OUT_CPU* FLUSH_OUT_FWH* t1 t t INIT_OUT* SW00592 Figure 13. Waveforms for boundary GPO_FLUSH_CACHE* Case • Timings should remain the same for both a 66 MHz or 33 MHz GPO_FLUSH_CACHE* – input to logic, GPO from the ICH2, programmed active LOW. CLK_IN input. • The boundary condition for INIT listed above, is a special case where immediately following the FLUSH_OUT*, INIT_OUT* cycle, the ICH2 asserts INIT* into the Glue Chip. • The boundary condition for GPO_FLUSH_CACHE* listed above, is a special case where immediately following the first assertion of GPO_FLUSH_CACHE*, the GPO is de-asserted, then re-asserted again before the timings have had a chance to complete. NOTE: 1. Nominal timing values with tolerances are listed in the DC Characteristics table. 2004 May 11 INIT* – input to logic, INIT* signal from the ICH2. A20M* – input to logic, A20M* signal from the ICH2. FLUSH_OUT_CPU* – output of logic, route to CPU FLUSH* pin. FLUSH_OUT_CPU* – output of logic, routed to FWH INIT* pin. INIT_OUT* – output of logic, routed to CPU INIT* pin. 21 Philips Semiconductors Product data Glue chip 4 PCA9504A T1 BACKFEED_CUT* T2 SLP_S5* LATCHED_BACKFEED_CUT SW00593 Figure 14. Power up signal sequencing Power up signal sequencing is shown in Figure 14. BACKFEED_CUT* is following the power rail up to its final value. LATCHED_BACKFEED_CUT should stay LOW, never turning on. SLP_S5* goes to its HIGH value when the power rails have stabilized, 25 msec after power on. BACKFEED_CUT* is pulled LOW a period T1 after SLP_S5* goes HIGH. T1 can be as short as 1msec. Typical measured values are 200 msec. T1 and T2 are guaranteed by the inherent design of the system and are not controlled by Glue Chip. SLP_S5* Tpropr Tpropf BACKFEED_CUT* Tf Tr LATCHED_BACKFEED_CUT SW00594 Figure 15. 1st sequence timing The first possible sequence is with SLP_S5*staying HIGH and BACKFEED_CUT* transitioning from LOW to HIGH, remaining HIGH for an undetermined period and then going back to LOW and the system is back at the end of the power-up sequence. The power-up sequence is shown in Figure 15. During these BACKFEED_CUT* transitions, the propagation delays, rise and fall times, and going into regulation times LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the end of the power-up sequence at any time. T4 T3 BACKFEED_CUT* SLP_S5* Tpropr Tpropf LATCHED_BACKFEED_CUT Tr Tf SW00595 Figure 16. 2nd sequence timing Signal sequencing for the second possible sequence is shown in Figure 16. BACKFEED_CUT* goes from LOW to HIGH and SLP_S5* goes from HIGH to LOW, 30 µsec to 65 µsec (T3) later. LATCHED_BACKFEED_CUT goes HIGH when BACKFEED_CUT* goes HIGH and then LATCHED_BACKFEED_CUT returns to LOW when SLP_S5* goes LOW. BACKFEED_CUT* stays HIGH and SLP_S5* stays LOW for an indeterminate time and then SLP_S5* will go HIGH. A minimum of 1msec (T4) later, BACKFEED_CUT* will go LOW and the system is back at the end of the power-up sequence. Typical measured values of T4 are 250 msec. During all transitions, the propagation delays, rise and fall times, and going into regulation times for LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the end of the power-up sequence at any time. 2004 May 11 22 Philips Semiconductors Product data Glue chip 4 PCA9504A RSMRST* GENERATION RSMRST* is a delayed 3.3 V hysteresis copy of V_5PO_STBY. RSMRST* is delayed going inactive from the rising edge of V_5PO_STBY by 32 ms, nominal. This delay starts when V_5PO_STBY hits the trip point. There is minimal delay on the falling edge. max V_5P0_STBY min VTRIP treset RSMRST* SW00596 Figure 17. Resume reset functionality V_5P0_STBY tRESET tRESET_FALL RSMRST* SW00597 Figure 18. Resume reset functionality during brown out 2004 May 11 23 Philips Semiconductors Product data Glue chip 4 PCA9504A AUDIO-DISABLE AUD_EN PCIRST AUD_RST 0 0 0 0 1 0 1 0 0 1 1 1 MUTE AUDIO CIRCUIT MUTE_AUD AUD_SHDN 0 1 1 0 HD SINGLE COLOR LED DRIVER PRIMARY_HD SECONDARY_HD SCSI HD_LED 0 0 0 0 0 X X 0 X 0 X 0 X X 0 0 1 1 1 HI–Z IDE RESET SIGNAL GENERATION AND PCRIST DRIVE STRENGTH PCIRST IDE_RSTDRV1 PCIRST_OUT 0 0 0 1 1 1 NOTE: 1. IDE_RSTDRV is a 5 V copy of PCIRST. PCIRST_OUT is a 3.3 V copy of PCIRST. PWRGD SIGNAL GENERATION FPRST PWRGD_PS PWRGD_3V 0 0 0 0 1 0 1 0 0 1 1 1 FLUSH_OUT / INIT_OUT CIRCUIT CASE A20M GPO_FLUSH_CACHE INIT FLUSH_OUT_CPU FLUSH_OUT_FWH INIT_OUT 1 1 Falling edge 0 0(for t1) 0(for t1) 0, Hi-Z, then 0 (delayed by t1-t, then active for 2*t) 2 1 Falling edge 1 0(for t1) 0(for t1) Hi-Z, 0 (delayed by t1-t, then active for 2*t) 3 X 1 0 Hi-Z Hi-Z 0 4 X 1 1 Hi-Z Hi-Z Hi-Z 5 0 Falling edge 1 Hi-Z Hi-Z Hi-Z 6 0 Falling edge 0 Hi-Z Hi-Z 0 CLK_IN AND SEL_33_66 2004 May 11 SEL_33_66 CLK_IN RATE 0 66 MHz 1 33 MHz 24 Philips Semiconductors Product data Glue chip 4 PCA9504A CLK_IN 2 CLK SEL_33_66 SW00603 Figure 19. GP_IN/GP_OUT GENERAL PURPOSE GATES GP1_INA GP1_INB GP1_OUT 0 0 1 0 1 1 1 0 1 1 1 0 GP_IN/GP_OUT GENERAL PURPOSE GATES (continued) GP2_IN GP2_OUT 0 1 1 0 GP_IN/GP_OUT GENERAL PURPOSE GATES (continued) GP3_IN GP3_OUT 0 0 1 1 POWER SEQUENCING / BACKFEED_CUT PWRGD_PS SLP_S3 BACKFEED_CUT 0 0 HI-Z 0 1 HI-Z 1 0 HI-Z 1 1 0 POWER SUPPLY TURN-ON CIRCUIT SLOTOCC SLP_S3 SLP_S3A 0 0 Hi-Z 0 1 0 1 0 Hi-Z 1 1 Hi-Z RAMBUS_SCK_BJT 2004 May 11 PWRGD_3V SCK_BJT_GATE 0 Hi-Z 1 0 25 Philips Semiconductors Product data Glue chip 4 PCA9504A VGA DCC VOLTAGE TRANSLATION 3V_DDCSDA 3V_DDCSCL 5V_DDCSDA 5V_DDCSCL 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 HSYNC / VSYNC VOLTAGE TRANSLATION HSYNC_3V HSYNC_5V VSYNC_3V VSYNC_5V 0 0 0 0 1 1 1 1 POWER LED DRIVER YLW_BLNK SLP_S5 YLW_LED GRN_BLNK SLP_S5 GRN_LED 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 HI-Z 1 1 Hi-Z 2004 May 11 26 Philips Semiconductors Product data Glue chip 4 PCA9504A TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm 2004 May 11 27 SOT364-1 Philips Semiconductors Product data Glue chip 4 PCA9504A REVISION HISTORY Rev Date Description _5 20040511 Product data (9397 750 13279). Supersedes data of 2003 Nov 10 (9397 750 12288). Modifications: • Page 24, Audio-disable table: AUD_EN column (reading veritcally) changed from ‘0000’ to ‘0011’. _4 20031110 Product data (9397 750 12288); ECN 853-2206 30409 dated 10 October 2003. Supersedes data of 28 March 2003 (9397 750 09602). _3 20030328 Product data (9397 750 09602); ECN: 853–2206 27930 (2003 Mar 28) 2004 May 11 28 Philips Semiconductors Product data Glue chip 4 PCA9504A Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 05-04 For sales offices addresses send e-mail to: [email protected]. Document order number: Philips Semiconductors 2004 May 11 29 9397 750 13279