PDU10256H
data 3
delay
devices, inc.
8-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU10256H)
FEATURES
•
•
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PACKAGES
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits 48-pin DIP socket
GND
ENB
1
48
GND
2
47
OUT
A0
7
42
VEE
8
41
A1
A2
GND
9
40
GND
PIN DESCRIPTIONS
IN
OUT
A0-A7
ENB
VEE
GND
Signal Input
Signal Output
Address Bits
Output Enable
-5 Volts
Ground
A3
15
34
VEE
16
33
A4
A5
GND
17
32
GND
IN
19
A6
23
25
A7
VEE
24
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
A7
VEE
A6
PDU10256H-xxC5 SMD
PDU10256H-xxMC5 Mil SMD
PDU10256H-xx DIP
PDU10256H-xxM Mil DIP
FUNCTIONAL DESCRIPTION
The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TDA, from the
input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following
formula:
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.
SERIES SPECIFICATIONS
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DASH NUMBER SPECIFICATIONS
Total programmed delay tolerance: 5% or 2ns,
whichever is greater
Inherent delay (TD0): 12ns typical
Setup time and propagation delay:
Address to input setup (TAIS): 3.6ns
Disable to output delay (TDISO): 1.7ns typical
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VEE: -5VDC ± 5%
Power Dissipation: 925mw typical (no load)
Minimum pulse width: 16% of total delay
1997 Data Delay Devices
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Part
Number
PDU10256H-.5
PDU10256H-1
PDU10256H-2
PDU10256H-3
PDU10256H-4
PDU10256H-5
PDU10256H-6
PDU10256H-8
PDU10256H-10
Incremental Delay
Per Step (ns)
0.5 ± 0.3
1.0 ± 0.5
2.0 ± 0.5
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.5
6.0 ± 1.5
8.0 ± 2.0
10.0 ± 2.0
Total
Delay (ns)
127.5 ± 6.4
255 ± 12.8
510 ± 25.5
765 ± 38.2
1020 ± 51.0
1275 ± 63.8
1530 ± 76.5
2040 ± 102
2550 ± 128
NOTE: Any dash number between .5 and 10
not shown is also available.
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU10256H
APPLICATION NOTES
possibility of spurious signals persists until the
required TDISH has elapsed.
ADDRESS UPDATE
The PDU10256H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
TOAX, is required before the address lines can
change. This time is given by the following
relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISH = Ai * TINC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
A7-A0
A i-1
Ai
TOAX
TAENS
TAIS
ENB
TENIS
PWIN
TDISH
IN
TDA
PWOUT
TDISO
OUT
Figure 1: Timing Diagram
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DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672
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http://www.datadelay.com
2
PDU10256H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TDT
TD0
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
MIN
TYP
127
12.0
1.7
UNITS
TINC
ns
ns
ns
ns
ns
1.0
3.6
3.6
See Text
See Text
12
32
200
6
16
100
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VEE
VIN
TSTRG
TLEAD
MIN
-7.0
VEE - 0.3
-55
MAX
0.3
0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
SYMBOL
VOH
VOL
VIH
VIL
IIH
IIL
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MIN
-1.020
-1.950
TYP
MAX
-0.735
-1.600
-1.070
-1.480
475
0.5
UNITS
V
V
V
V
µA
µA
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
NOTES
VIH = MAX,50Ω to -2V
VIL = MIN, 50Ω to -2V
VIH = MAX
VIL = MIN
3
PDU10256H
PACKAGE DIMENSIONS
48 47
42 41 40
34 33 32
25
.400
TYP.
1 2
7
8
9
15 16 17
19
23 24
2.450 TYP.
.020 .320
TYP. MAX.
.150
±.030
.018
TYP.
.100
.600
.700
.800
.012 TYP.
.300
TYP.
1.400
1.500
1.600
1.800
2.200
2.300
.075
PDU10256H-xx (Commercial DIP)
PDU10256H-xxM (Military DIP)
.020 TYP.
.040 TYP.
.010±.002
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
.882
±.005
.710 .590
±.005 MAX.
1
2
3
4
5
6
7
8
9
.007
±.005
10 11 12 13 14 15 16 17 18 19 20
.090
.100
1.100
2.080±.020
.280
MAX.
.050
±.010
PDU10256H-xxC5 (Commercial SMD)
PDU10256H-xxMC5 (Military SMD)
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DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672
Electronic-Library Service CopyRight 2003
http://www.datadelay.com
4
PDU10256H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance:
50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 10 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF
PULSE
GENERATOR
OUT
IN
DEVICE UNDER
TEST (DUT)
TRIG
OUT
IN
OSCILLOSCOPE
TRIG
ADDRESS SELECT
Test Setup
PERIN
PWIN
TRISE
INPUT
SIGNAL
TFALL
VIH
80%
50%
20%
80%
50%
20%
TRISE
OUTPUT
SIGNAL
VIL
TFALL
VOH
50%
50%
VOL
Timing Diagram For Testing
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DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5