PI6C487016 Low Skew, 1-to-16 LVCMOS / LVTTL Clock Driver Product Features Product Description • 16 LVCMOS/LVTTL outputs (4 banks of 4 outputs) The PI6C487016 is a low skew. 1:16 LVCMOS/LVTTL Clock Driver. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. • Selectable differential or single-ended clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximum output frequency: 250MHz • Independent bank control for ÷1 or ÷2 operation The divide select inputs, SELA:SELD, control the output frequency of each bank with either ÷1 or ÷2 frequency operation. The bank enable inputs, ENA:END, support enabling and disabling each bank of outputs individually. The outputs synchronized when enabling or disabling the clock outputs. The master reset input nMR/OE, resets the ÷1/÷2 flip flops and also controls the active and high impedance states of all outputs. • Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operations • Output skew: 170ps (max) • Bank skew: 50ps (max) • Part-to-part skew: 800ps (max) • 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply The PI6C487016 is characterized to operate with the core at 3.3V and the output banks at 3.3V, 2.5V or 1.8V. • -40° to +85°C ambient operating temperature • Available packages: -Pb-free & green 48-pin LQFP(FB) Pin Description Block Diagram QA3 VDDOA QA2 GND QA1 VDDOA QA0 GND CLK_SEL nCLK1 CLK1 VDD nMR/OE CLK0 0 ÷1 1 CLK1 nCLK1 1 ÷2 0 CLK_SEL D LE D 1 LE 4 4 QA0:QA3 VDD CLK0 SELA SELB SELC SELD ENA ENB ENC END nMR/OE GND QB0:QB3 0 SELA SELB 1 SELC 0 LE D SELD 1 ENA D LE 4 4 QC0:QC3 QD0:QD3 0 ENB ENC GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1 GND QC2 VDDOC QC3 GND QD0 VDDOD QD1 GND QD2 VDDOD QD3 END 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 1 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver Pin Descriptions Number Name Type Description 1, 48 VDD Power 2 CLK0 Input Pulldown 3, 4, 5, 6 SELA : SELD Input Pullup Controls frequency division for outputs. LVCMOS / LVTTL interface levels. QAx:QDx 7, 8, 9, 10 ENA : END Input Pullup Output enable for QAx : QDx Outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. 11 nMR/OE Input Pullup Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the outputs to high impedance. LVCMOS / LVTTL interface levels. 12, 16, 20, 24, 28, 32, 36, 40, 44 GND Power Supply Ground 13, 15, 17, 19 QD0 : QD3 Output Bank D Outputs, LVCMOS / LVTTL interface levels. 14, 18 VDDOD Power Voltage supply for QD0 : QD3 21, 23, 25, 27 QC0 : QC3 Output Bank C outputs, LVCMOS / LVTTL interface levels. 22, 26 VDDOC Power Voltage supply for QC0 : QC3 29, 31, 33, 35 QB0 : QB3 Output Bank B outputs, LVCMOS / LVTTL interface levels. 30, 34 VDDOB Power Voltage supply for QB0 : QB3 37, 39, 41, 43 QA0 : QA3 Output Bank A outputs, LVCMOS / LVTTL interface levels. 38, 42 VDDOA Power Voltage supply for QA0 : QA3 45 CLK_SEL Input 46 nCLK1 Input Pullup 47 CLK1 input Pulldown Core supply pins (3.3V) Pulldown LVCMOS / LVTTL clock input Clock select input, when HIGH, selecs CLK1, nCLK1 inputs. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. inverting differential clock input Non-inverting differential clock input Notes: 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values. Function Table Inputs Outputs nMR/OE ENx SELx Bank X Qx Frequency 0 X X Hi Z N/A 1 1 0 Active FIN/2 1 1 1 Active FIN 1 0 X Low N/A 2 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver Absolute Maxium Ratings Supply Voltage, VDD ...................... 4.6V Inputs, VI...................................................... -0.5V to VDD +0.5V Outputs, V0.................................................. -0.5V to VDDO +0.5V Package Thermal Impedance, ØJA ..... 47.9º C/W (0lfpm) Storage Temperature, TSTG................... -65ºC to +150ºC Notes: 1. Stresses byond those listed under Absolute Maximun Ratings may caouse permanent damage to the device. These ratings are stress specifcations only. Functional operation of products at these conditions or any conditions beyond those listed in the DC Characteristics or AC characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Pin Characteristics Symbol CIN Parameter Test Condition Min. Input Capacitance CPD ROUT Max. Units 4 RPULLDOWN Input Pulldown Resistor RPULLUP Typ. 51 Input Pullup Resistor Power Dissaipation Capacitance (per output) pF kΩ 51 VDD, VDDOX = 3.465V 18 VDD = 3.465, VDDOX = 2.625V 20 VDD = 3.465, VDDOX = 1.895V 30 Output Impedance 5 7 pf 12 Ω Power Supply DC Characteristics, (VDD = 3.3V ±5%, TA = -40º to +85ºC) Symbol VDD VDDOX IDD IDDOX Parameter Core Supply Voltage Output Supply Voltage Min. Typ. Max. 3.135 3.3 3.465 3.135 3.3 3.465 2.375 2.5 2.625 1.71 1.8 1.89 Core Supply Current Output Supply Units V 100 Current(1) mA 15 Note: 1. Measured with all outputs disabled (ENx=0, nMR=1) 3 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver LVCMOS/LVTTL DC Characteristics, (VDD = 3.3V ±5%, TA = -40º to +85ºC) Symbol VIH Parameter Input High Voltage Test Conditions VDD + 0.3 CLK0 2 VDD + 0.3 SELx, ENx, nMR/OE, CLK_SEL -0.3 0.8 CLK0 -0.3 1.3 IIH ENx, SELx, Input High Current nMR/OE CLK0, CLK_SEL ENx, SELx, nMR/OE CLK0, CLK_SEL VOH VOL Max. 2 Input Low Voltage Input Low Current Typ. SELx, ENX, nMR/OE, CLK_SEL VIL IIL Min. Output High Voltage(1) Output Low Voltage(1) IOZL Output Tristate Current Low IOZH Output Tristate Curretn High Units V 5 VDD = VIN = 3..465V 150 µA -150 VDD = 3.465, VIN = 0V -5 VDDOX = 3.3 ± 5% 2.6 VDDOX = 2.5 ± 5% 1.8 VDDOX = 1.8 ± 5% IOH = -2mA VDD - 0.45 VDDOX = 3.3 ± 5% 0.5 VDDOX = 2.5 ± 5% 0.5 VDDOX = 1.8 ± 5% IOH = -2mA 0.45 -5 5 V µA Notes: 1. Outputs terminate with 50Ω to VDDOX/2. See Parameter Measurement information, Output Load Test Circut Differential DC Characteristics, (VDD = 3.3V ±5%, TA = -40º to +85ºC) Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current Test Conditions Typ. Max. nCLK1 VIN = VDD = 3.465V 5 CLK1 VIN = VDD = 3.465V 150 nCLK1 VIN = 0V, VDD = 3.465V -150 CLK1 VIN = 0V, VDD = 3.465V -5 Peak-to-peak Input Voltage Common mode input Min. voltage(1,2) 0.15 1.3 GND + 0.5 VDD -0.85 Units µA V Notes: 1. For single ended application, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. 2. Common mode voltage is definded as VIH. 4 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver AC Characteristics, (VDD = 3.3V ±5%, VDDOX = 1.8V ±5% to 3.3V ±5%, TA = -40º to +85ºC)(7) Symbol fMAX Parameter CLK0(1) Propagation Delay, Low to High nCLK1(2) CLK0(1) CLK1, nCLK1(2) CLK0(1) CLK1, tsk(b) tsk(o) tsk(pp) Min. Typ. Output Frequency CLK1, TpLH Test Conditions Bank skew(3) Output skew(4) Part-to-Part nCLK1(2) VDDOX = 3.3V VDDOX = 2.5V VDDOX = 1.8V Output Rise/Fall Time(5) odc Output duty cycle tEN Output enable tDIS Output Units 250 MHz 2.3 3.4 3.9 2.5 3.4 3.9 2.3 3.5 4.0 2.5 3.5 4.0 2.4 3.9 4.7 2.6 3.9 4.7 Measured on the rising edge 50 Measured on the rising edge 170 skew(5) tR/tF Max. 800 20% to 80% time(6) 200 700 40 60 10 Disable Time(6) 10 ns ps % ns Notes: 1. Measured from the VDD/2 of the input to VDDOX/2 of the output 2. Measured from the differential input crossing point to VDDOX/2 of the output 3. Defined as a skew within a bankwith equal load conditions 4. Defined as a skew between outputs at the same supply voltage, same frequency, and with equal load conditions. Measured at VDDOX/2 5. Defined as a skew between outputs on a different devices operation at the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. 6. These parameters are guaranteed by characterizatoin. Not tested in prodution. 7. All parameters are measured at 250MHz with SEL [A:D] = 1 unless noted otherwise. 5 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver Parameter Measurement Information 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDOx SCOPE VDD LVCMOS Qx VDDOx Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V Core/3.3V Output Load AC Test Circuit 3.3V Core/2.5V Output Load AC Circuit 2.4±0.9V +0.9V±5% VDD SCOPE V DD VDDOx LVCMOS nCLK1 V Qx PP V Cross Points CMR CLK1 GND GND = -0.9V±5% 3.3V Core/1.8V Output Load AC Test Circuit Differential Input Level 6 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver Application Information Wiring the differenctial input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 adn R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. VDD Single Ended Clock Input R1 1K CLK1 nCLK1 C1 0.1µ R2 1K Figure 1: Single-ended Signal Driving Differential Input 7 PS8741D 07/29/05 PI6C487016 Low Skew, 1-to-16 LVCMOS/LVTTL Clock Driver Package Mechanical: 48-pin LQFP (FB) 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.09~0.20 GAUGE PLANE 0.25 mm 0° 7° 0.45 0.75 1.00 REF 1.45 1.35 1.60 MAX 0.10 C Seating Plane 0.17 0.27 0.50 BSC 0.05 0.15 Ordering Information Ordering Code Package Code Package Type PI6C487016FBE FB Pb-free & Green, 48-pin LQFP Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ 2. Number of Transistors = TBD Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 8 PS8741D 07/29/05