PO74G112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 04/19/09 74 Series GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency up to 750MHz with 15pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 2ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 mA Per JESD 17 . ESD Protection Exceeds JESD 22 . 5000-VHuman-BodyModel (A114-A) . 200-VMachineModel (A115-A) . Available in 16pin 150mil wide SOIC package . Available in 16pin 173mil wide TSSOP package Potato Semiconductor’s PO74G112A is designed for world top performance using submicron CMOS technology to achieve 750MHz TTL /CMOS output frequency with less than 2ns propagation delay. This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation. Logic Block Diagram Pin Configuration 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q 9 Pin Description INPUTS Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. OUTPUTS PRE CLR CLK J K Q L H X X X H L H L X X X L H Q L L X X X H H H H ↓ L L Q0 Q0 H H ↓ H L H L H H ↓ L H L H H H ↓ H H H H H X X 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND J PRE Q 1 K Q CLR J PRE Q 1 K Q CLR VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q Toggle Q0 Q0 1 Copyright © Potato Semiconductor Corporation PO74G112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 04/19/09 74 Series GHz Logic Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -55 to 125 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - 5.5 V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 5.5V - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation PO74G112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 04/19/09 74 Series GHz Logic Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 40 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Cin Cout Description Test Conditions Typ Input Capacitance Vin = 0V Output Capacitance Vout = 0V 4 6 Unit pF pF Notes: 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions (1) M ax - tsu th Setup time before CLK tPLH Propagation Delay CLK to Q CL = 15pF 2 t PHL Propagation Delay CLK to Q CL = 15pF 2 tr/tf Rise/Fall Time 0.8V – 2.0V 0.8 fmax Input Frequency CL=2pF - 15pF Hold time, data after CLK - Min Unit 0.5 ns 0.5 ns - ns 750 MHz ns ns Notes: 1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz 3 Copyright © Potato Semiconductor Corporation PO74G112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 04/19/09 74 Series GHz Logic Test Waveforms VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at V LOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VΔ VOL tPHZ VM VOH - VΔ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Test Circuit Vcc Pulse Generator 50Ω D.U.T 15pF to 2pF 4 Copyright © Potato Semiconductor Corporation PO74G112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 04/19/09 74 Series GHz Logic Packaging Mechanical Drawing: 16 pin SOIC 16 .149 .157 .2284 .2440 3.78 3.99 1 .0075 .0098 .386 .393 9.80 10.00 .016 .050 5.80 6.20 0.41 1.27 0.19 0.25 .0155 0.393 .0260 0.660 .053 .068 .050 BSC 1.27 .013 .020 0.330 0.508 .0040 .0098 1.35 1.75 0.10 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical Drawing: 16 pin TSSOP X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 5 Copyright © Potato Semiconductor Corporation PO74G112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 04/19/09 74 Series GHz Logic Ordering Information Ordering Code Package Top-Marking TA PO74G112ASU 16-pin SOIC Tube Pb-free & Green PO74G112AS -40°C to 85°C PO74G112ASR 16-pin SOIC Tape and reel Pb-free & Green PO74G112AS -40°C to 85°C PO74G112ATU 16-pin TSSOP Tube Pb-free & Green PO74G112AT -40°C to 85°C PO74G112ATR 16-pin TSSOP Tape and reel Pb-free & Green PO74G112AT -40°C to 85°C IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE S SOIC 16 16 8 Top Left Corner 39 (12”) 3000 64 (20”) 48 T TSSOP 16 12 8 Top Left Corner 39 (12”) 3000 64 (20”) 96 7 Copyright © Potato Semiconductor Corporation