PO74G2305A 3.3V 1:5 CMOS Clock Buffered Driver 750MHz TTL/CMOS Potato Chip FEATURES: DESCRIPTION: . Patented technology . Max input frequency > 1GHz . Operating frequency up to 750MHz with 2pf load . Operating frequency up to 600MHz with 5pf load . Operating frequency up to 300MHz with 15pf load . Operating frequency up to 125MHz with 50pf load . Very low output pin to pin skew < 80ps . Very low pulse skew < 130ps . VCC = 1.65V to 3.6V . Propagation delay < 1.5ns max with 15pf load . Low input capacitance: 3pf typical . 1:5 fanout . Available in 8pin 150mil wide SOIC package Potato Semiconductor’s PO74G2305A is designed for world top performance using submicron CMOS technology to achieve 750MHz TTL output frequency with less than 80ps output pin to pin skew. Pin Configuration INA O2 O1 GND 1 2 3 10/05/07 PO74G2305A is a 3.3V CMOS 1 input to 5 outputs Buffered driver to achieve 750MHz output frequency. Typical applications are clock and signal distribution. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. Logic Block Diagram 8 8-Pin SOIC 4 O5 7 O4 6 VDD 5 O3 Pin Description Pin Name INA O1 to O5 Description Input Outputs 1 Copyright © 2005-2006, Potato Semiconductor Corporation PO74G2305A 3.3V 1:5 CMOS Clock Buffered Driver 10/05/07 750MHz TTL/CMOS Potato Chip Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 5.5V - - 5 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -5 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA -0.7 -1.2 - V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © 2007, Potato Semiconductor Corporation PO74G2305A 3.3V 1:5 CMOS Clock Buffered Driver 10/05/07 750MHz TTL/CMOS Potato Chip Power Supply Characteristics Symbol Description Test Conditions (1) Min Typ Max Unit IccQ Quiescent Power Supply Current Vcc=Max, Vin=Vcc or GND - 0.1 50 uA ∆Icc Power Supply Current per Input High Vcc=Max, Vin= Vcc-0.6V - 50 300 uA Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current Capacitance Parameters (1) Description Test Conditions Typ Max Unit Cin Input Capacitance Vin = 0V 3 4 pF Cout Output Capacitance Vout = 0V - 6 pF Notes: 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions (1) M ax Unit tPLH Propagation Delay A to Bn CL = 15pF 1.5 ns tPHL Propagation Delay A to Bn CL = 15pF 1.5 ns tr/tf Rise/Fall Time 0.8V – 2.0V 0.8 ns tsk(p) Pulse Skew (Same Package) CL = 15pF, 125MHz 80 tsk(o) Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 0.13 ps ns Output Skew (Different Package) CL = 15pF, 125MHz 0.4 ns tsk(pp) fmax Input Frequency CL = 50pF 125 MHz fmax Input Frequency CL =15pF 300 MHz fmax Input Frequency CL = 5pF fmax Input Frequency CL = 2pF 600 750 MHz MHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3 Copyright © 2007, Potato Semiconductor Corporation PO74G2305A 3.3V 1:5 CMOS Clock Buffered Driver 750MHz TTL/CMOS Potato Chip 10/05/07 Test Waveforms Test Circuit 50Ω 4 Copyright © 2007, Potato Semiconductor Corporation PO74G2305A 3.3V 1:5 CMOS Clock Buffered Driver 10/05/07 750MHz TTL/CMOS Potato Chip Packaging Mechanical Drawing: 8 pin SOIC 8 0-8˚ .149 .157 3.78 3.99 .0099 .0196 0.25 x 45˚ 0.50 .016 .050 0.40 1.27 .2284 .2440 5.80 6.20 1 .189 .196 4.80 5.00 .053 .068 .016 .026 0.406 0.660 .0075 .0098 1.35 1.75 0.19 0.25 SEATING PLANE REF .050 BSC 1.27 .0040 0.10 .0098 0.25 .013 0.330 .020 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Ordering Code Package Top-Marking TA PO74G2305ASU 8-pin SOIC Tube Pb-free & Green PO74G2305AS -40°C to 85°C PO74G2305ASR 8-pin SOIC Tape and reel Pb-free & Green PO74G2305AS -40°C to 85°C 5 Copyright © 2007, Potato Semiconductor Corporation