PO49FCT3807 3.3V Dual 1:10 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip FEATURES: DESCRIPTION: . Operating frequency up to 500MHz with 2pf load . Operating frequency up to 450MHz with 5pf load . Operating frequency up to 320MHz with 15pf load . Operating frequency up to 120MHz with 50pf load . Very low output pin to pin skew < 350ps . Very low pulse skew < 100ps . VCC = 1.65V to 3.6V . Propagation delay < 2.0 ns max with 15pf load . Low input capacitance: 3pf typical . 1:10 fanout . Available in 20pin 150mil wide QSOP package . Available in 20pin 300mil wide SOIC package Potato Semiconductor’s PO49FCT3807G is designed for world top performance using submicron CMOS technology to achieve 500MHz output frequency with less than 350ps output skew. Pin Configuration 11/22/05 PO49FCT3807G is a 3.3V CMOS 1 input to 10 Output Buffered Driver. Typical applications are clock and signal distribution. Logic Block Diagram Pin Description Pin Name INA O1 to O10 Description Input Outputs 1 Copyright © 2005, Potato Semiconductor Corporation PO49FCT3807 3.3V Dual 1:10 CMOS Clock Buffered Driver 11/22/05 500MHz TTL/CMOS Potato Chip Maximum Ratings Description Note: Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to Vcc+0.5 V Output Voltage -0.5 to Vcc+0.5 V stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.4 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 3.6V - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © 2005, Potato Semiconductor Corporation PO49FCT3807 3.3V Dual 1:10 CMOS Clock Buffered Driver 11/22/05 500MHz TTL/CMOS Potato Chip Power Supply Characteristics Symbol Description Test Conditions (1) Min Typ Max Unit IccQ Quiescent Power Supply Current Vcc=Max, Vin=Vcc or GND - 0.1 30 uA ∆Icc Power Supply Current per Input High Vcc=Max, Vin= Vcc-0.6V - 50 300 uA Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current Capacitance Parameters (1) Description Test Conditions Typ Max Unit Cin Input Capacitance Vin = 0V 3 4 pF Cout Output Capacitance Vout = 0V - 6 pF Notes: 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions (1) M ax Unit tPLH Propagation Delay A to Bn CL = 15pF 2 ns tPHL Propagation Delay A to Bn CL = 15pF 2 ns tr/tf Rise/Fall Time 0.8V – 2.0V 0.8 ns tsk(p) Pulse Skew (Same Package) CL = 15pF, 250MHz 0.1 ns tsk(o) Output Pin to Pin Skew (Same Package) CL = 15pF, 250MHz 0.35 ns Output Skew (Different Package) CL = 15pF, 250MHz 0.4 ns tsk(pp) fmax Input Frequency CL = 50pF 100 MHz fmax Input Frequency CL =15pF 320 MHz fmax Input Frequency CL = 5pF 450 MHz fmax Input Frequency CL = 2pF 500 MHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3 Copyright © 2005, Potato Semiconductor Corporation PO49FCT3807 3.3V Dual 1:10 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Test Waveforms Test Circuit 50Ω 4 Copyright © 2005, Potato Semiconductor Corporation PO49FCT3807 3.3V Dual 1:10 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Packaging Mechanical Drawing: 20 pin QSOP Packaging Mechanical Drawing: 20 pin SOIC 5 Copyright © 2005, Potato Semiconductor Corporation PO49FCT3807 3.3V Dual 1:10 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Packaging Mechanical Drawing: 20 pin QSOP Packaging Mechanical Drawing: 20 pin SOIC 5 Copyright © 2005, Potato Semiconductor Corporation