PT4741—48V 70-W Quad-Output DC/DC Converter for DSL SLTS167A - APRIL 2002 - REVISED NOVEMBER 2002 Features • Input Voltage: 36V to 75V • Designed for AC6 ADSL Line-Interface Driver/Receivers • Powers up to 64 Channels • Quad Outputs (±8V, ±3.75V) • Dual Logic On/Off Control • Output Current Limit • Unbalanced Load Protection • Fixed Frequency Operation • Over-Temperature Shutdown Description • • • • Under-Voltage Lockout 1500VDC Isolation Solderable Copper Case Space-Saving Package 1.9 sq. in. PCB Area (suffix N) • Safety Approvals: UL60950 CSA 22.2 950 VDE EN60950 (Pending) Ordering Information The PT4741 Excalibur™ power module is a 70-watt quad-output DC/DC converter that is designed to meet the power requirements of Texas Instruments’ TNETD7112. The TNETD7112 is a dual-channel line-interface driver/receiver that compliments the AC6 ADSL chipset for use in POTS (plain old telephone service) applications. To conserve power, the TNETD7112 line drivers require two pairs of complimentary power supply voltages. These are ±8V and ±3.75V respectively. The PT4741 module operates from a standard (–48V) telecom central office supply and provides all four supply voltages as two com- plimentary balanced loads. (This product is not suitable for unbalanced load applications.) The load capacity allows the PT4741 to operate up to 32 line-driver ICs, representing 64 ADSL channels. The PT4741 incorporates many features to simplify system integration. These include a flexible On/Off enable control, input under-voltage lock-out, and over-temperature protection. All outputs are short-circuit protected, and internally sequenced to meet the TNETD7112 power-up and power-down requirements. The module is packaged in a space-saving solderable copper case, requires no heat sink, and can occupy as little as 1.9 in2 of PCB area. PT4741o = ±8.0/±3.75V PT Series Suffix (PT1234 x ) Case/Pin Configuration Vertical Horizontal SMD Order Suffix Package Code N A C (EKD) (EKA) (EKC) (Reference the applicable package code drawing for the dimensions and PC layout) Typical Application To Additional Channels Power Filter PT4741 21 ±Vo 1 Adj +VIN +Vo 1 1 18 +V IN COM 19 3 4 EN2 –Vo 1 EN1 +8V Co 1 33µF + Co 2 33µF + 20 VEEH VCCH ½ Dual-Channel ADSL Driver/Receiver (TNETD7112) –8V TXP 26 ±Vo 2 Adj –V IN +Vo 2 2 23 –V IN COM 24 –Vo 2 VEEHS VCCHS 25 +3.75V Co 3 150µF + Co 4 150µF + AGND RXP DGND RXN TXN VEEL VCCL Power Filter –3.75V Co1, Co 2 Co3, Co 4 EN1 & EN2 pins: For technical support and more information, see inside back cover or visit www.ti.com = Required 33µF = Required 150µF See On/Off Enable Logic PT4741—48V 70-W Quad-Output DC/DC Converter for DSL SLTS167A - APRIL 2002 - REVISED NOVEMBER 2002 Environmental Specifications Characteristics Symbols Conditions Min Typ Max Units Operating Temperature Range Solder Reflow Temperature Storage Temperature Reliability Ta Treflow Ts MTBF Over Vin Range Surface temperature of module pins or case — Per Bellcore TR-332 50% stress, Tc =40°C, ground benign Per Mil-STD-883D, Method 2002.3 1 msec, ½ Sine, mounted Mil-STD-883D, Method 2007.2 Suffix N 20-2000 Hz Suffix A, C Vertical/Horizontal –40 — –40 1.6 — — — — 85 (i) 215 (ii) 125 — °C °C °C 106 Hrs — — — — TBD TBD (iii) TBD (iii) 90 115 — — — — 125 Mechanical Shock Mechanical Vibration Weight ShutdownTemperature Flammability — OTP — G’s G’s grams °C Meets UL 94V-O Notes: (i) See SOA curves or consult factory for appropriate derating. (ii) During solder reflow of SMD package version, do not elevate the module case, pins, or internal component temperatures above a peak of 215°C. For further guidance refer to the application note, “Reflow Soldering Requirements for Plug-in Power Surface Mount Products,” (SLTA051). (iii) Only the case pins on through-hole pin configurations (N & A) must be soldered. For more information see the applicable package outline drawing. Pin Configuration On/Off Enable Logic Pin Function Pin Function Pin Function Pin 3 1 +Vin 10 Do Not Connect 19 COM 2 –Vin 11 Pin Not Present 20 –Vo1 3 EN 2 12 Pin Not Present 21 ±Vo1 Adjust 4 EN 1 13 Pin Not Present 22 Do Not Connect 5 Do Not Connect 14 Pin Not Present 23 +Vo2 6 Do Not Connect 15 Pin Not Present 24 COM 7 Do Not Connect 16 Pin Not Present 25 –Vo2 8 Do Not Connect 17 Pin Not Present 26 ±Vo2 Adjust 9 Do Not Connect 18 +Vo1 Note: Shaded functions indicate those pins that are at primary-side potential. Pin 4 Output Status × 1 Off 1 0 On 0 × Off Notes: Logic 1 =Open collector Logic 0 = –Vin (pin 2) potential For positive Enable function, connect pin 4 to pin 2 and use pin 3. For negative Enable function, leave pin 3 open and use pin 4. Pin Descriptions +Vin: The positive input supply for the module with respect to –Vin. When powering the module from a –48V telecom central office supply, this input is connected to the primary system ground. –Vin: The negative input supply for the module, and the 0VDC reference for the EN 1, and EN 2 inputs. When powering the module from a +48V supply, this input is connected to the 48V(Return). EN 1: The negative logic input that activates the module output. This pin must be connected to –Vin to enable the module’s outputs. A high impedance disables the module’s outputs. EN 2: The positive logic input that activates the module output. If not used, this pin should be left open circuit. Connecting this input to –Vin disables the module’s outputs. +Vo 1: This is the positive high-output voltage. It is the balanced compliment of (–Vo1) and referenced to the secondary COM node. +Vo 2: This is the positive low-output voltage. It is the balanced complement of (–Vo2) and referenced to the secondary COM node. –Vo 2: The negative low-output voltage, which is the balanced compliment of (+Vo2) with respect to COM. COM: This is the common node and the secondary reference for all four regulated output voltages. It provides a return for any unbalanced load current, and is DC isolated from the input supply pins. ±Vo1 Adjust: Using a single resistor, this pin allows the simultaneous adjustment of both +Vo1 and -Vo1 magnitude with respect to the COM node. Adjustment can be higher or lower than the preset value. If not used this pin should be left open circuit. ±Vo2 Adjust: Using a single resistor, this pin allows the simultaneous adjustment of both +Vo2 and -Vo2 magnitudes with respect to the COM node. Adjustment can be higher or lower than the preset value. If not used this pin should be left open circuit. –Vo 1: The negative high-output voltage, which is the balanced compliment of (+Vo1) with respect to COM. For technical support and more information, see inside back cover or visit www.ti.com PT4741—48V 70-W Quad-Output DC/DC Converter for DSL SLTS167A - APRIL 2002 - REVISED NOVEMBER 2002 PT4741 Electrical Specifications (Unless otherwise stated, the operating conditions are:- Ta =25°C, V in =48V, and I o =Iomax) Min PT4741 Typ Max Units 0 0 — — — — 36 — 7.76 3.82 — — — — 7.6 3.75 — — — — — — — — — — — — — — — — 8.0 3.94 ±TBD ±TBD ±0.05 ±0.2 — — 86 — — 75 2 ±10 (1) 3 (1) 4 2.5 (1) 3.5 (1) ±100 (2) ±100 (2) ±200 ±200 75 80 8.24 4.06 (3) — — ±0.25 ±0.5 8.4 4.13 (3) — 75 50 — — — — — A — 300 — mA ƒs Shutdown & latch off (within 1ms) Over Vin and Io ranges 550 600 650 kHz Von Voff Vin increasing Vin decreasing — — 34 32 — — V 4 –0.2 — — Open 0.8 Characteristics Symbols Conditions Output Current Io1, Io2 Balanced load ±Vo1 ±Vo2 ±Vo1 ±Vo2 ±Vo1 ±Vo2 Load imbalance Transient imbalance (<1ms) Input Voltage Range Vin Set-Point Voltage Vo1, Vo2 Continuous Surge (1 minute) Either output to COM Temperature Variation Regtemp –40°C ≤Ta ≤+85°C, Io =Iomin Line Regulation Load Regulation Total Output Voltage Variation Regline Regload ∆Vo tot All outputs, Over Vin range All outputs, 0≤Io≤Iomax Includes set-point, line, load, –40°C ≤Ta ≤+85°C Efficiency Vo Ripple (pk-pk) η Vn Transient Response ttr Vos Vox adj IoLIM Output Adjust Range Balanced Load Current Limit Threshold Unbalanced Load Shutdown Threshold Switching Frequency Under Voltage Lockout Iocomsc ±Vo1 (8.0 V) ±Vo2 (3.75V) ±Vo1 ±Vo2 ±Vo1 (8.0 V) ±Vo2 (3.75V) Measured from each output to COM, 0 to 20MHz bandwidth 0.1A/µs load step, 50% to 75% Iomax Vo over/undershoot Each ±Vo adjusted as pair Shutdown, auto restart ±Vo1 ±Vo2 ±Vo1 ±Vo2 (2) mA mA V V %Vo %Vo %Vo V % mVpp µSec %Vo %Vo A Enable Control (pins 3 & 4) High-Level Input Voltage Low-Level Input Voltage Low-Level Input Current VIH VIL Referenced to –Vin (pin 2) IIL Pin connected to –Vin (pin 2) — –0.16 –0.27 mA Standby Input Current Iin standby pins 3 & 4 open circuit — 5 20 mA — 2.4 33 150 1500 — 10 — — — 2,200 — Internal Input Capacitance Cint External Output Capacitance Co Primary/Secondary Isolation Each output to COM V iso C iso R iso ±Vo1 ±Vo2 (4) (4) — 1,000 1,000 — — — V µF (5) (5) µF V pF MΩ A balanced load is defined as the current flowing out of (+Vox) being to equal that flowing into (–Vox). The current flowing in the COM termnal is zero. The load imbalance is the difference between the current flowing out of (+Vox) and flowing into (–Vox). The difference flows in the COM terminal. The nominal output voltage of ±Vo2 is 3.94V. The output voltage and tolerance is defined as 3.75V, –0%, +10%. The Enable inputs (pins 3 & 4) have internal pull-ups. Leaving pin 3 open-circuit and connecting pin 4 to –V in allows the the converter to operate when input power is applied. The maximum open-circuit voltage is 5V. (5) Capacitance added to each pair of complimentary output voltages (±Vox) must be divided equally between (+Vox) and (–Vox) with respect to the COM termnial. E.g. Co 1 must equal Co2, and Co 3 must equal Co4. Notes: (1) (2) (3) (4) For technical support and more information, see inside back cover or visit www.ti.com Typical Characteristics PT4741—48V 70-W Quad-Output DC/DC Converter for DSL SLTS167A - APRIL 2002 - REVISED NOVEMBER 2002 Performance Characteristics; Vin =48V Output Ripple Vout1 vs ±Iout 1 & ±Iout2 Output Ripple ±Vout2 vs ±Iout 1 & ±Iout2 25 25 20 20 ± Iout2 3.5A 2.0A 1.5A 1.0A 0.5A 15 10 ± Vo2 Ripple - mV ± Vo1 Ripple - mV (See Note A) 5 ± Iout1 2.5A 2.0A 1.5A 1.0A 0.5A 15 10 5 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 ± Iout1 (A) 2.5 3 3.5 Load Regulation ±Vout2 vs ±Iout1 8.04 3.96 8.03 3.955 8.02 8.01 Vo (+) Vo (–) 8 7.99 7.98 Load Regulation |∆Vout 2| (V) Load Regulation |∆Vout 1| (V) Load Regulation ±Vout1 vs ±Iout 1 7.97 3.95 3.945 Vo (+) Vo (–) 3.94 3.935 3.93 3.925 7.96 3.92 0 0.5 1 1.5 2 2.5 0 0.5 1 ± Iout1 (A) 1.5 2 2.5 3 3.5 ± Iout2 (A) Cross Regulation ±Vout1 vs ±Iout 2 Cross Regulation ±Vout2 vs ±Iout 1 8.04 3.96 8.03 3.955 8.02 8.01 Vo (+) Vo (–) 8 7.99 7.98 Cross Regulation |Vout2| (V) Cross Regulation |∆Vout 1| (V) 2 ± Iout2 (A) 3.95 3.945 Vo (+) Vo (–) 3.94 3.935 3.93 3.925 7.97 3.92 7.96 0 0.5 1 1.5 2 ± Iout2 (A) 2.5 3 3.5 0 0.5 1 1.5 2 2.5 ± Iout1 (A) Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. For technical support and more information, see inside back cover or visit www.ti.com Typical Characteristics PT4741—48V 70-W Quad-Output DC/DC Converter for DSL SLTS167A - APRIL 2002 - REVISED NOVEMBER 2002 Performance Characteristics; Vin =48V (See Note A) PT4741 Safe Operating Area (SOA) (See Note B) (All outputs proportionally loaded from 0 to 100% of full load) Efficiency vs ±Iout1 & ±Iout2 SOA vs Total Output Power; V in =48V 100 90 Efficiency - % ± Iout2 3.5A 2.0A 1.5A 1.0A 0.5A 80 70 60 Ambient Temperature (°C) 80 90 Airflow 70 300LFM 200LFM 150LFM 100LFM Nat conv 60 50 40 30 50 20 0.0 0.5 1.0 1.5 2.0 2.5 0 ± Iout1 (A) 10 20 30 40 50 60 70 Total Output Power (W) Power Dissipation vs ±Iout1 & ±Iout2 12 ± Iout2 10 3.5A 3.0A 2.5A 2.0A 1.5A 1.0A 0.5A 0.1A Pd - Watts 8 6 4 2 0 0 0.5 1 1.5 2 2.5 ± Iout1 (A) Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT4741 Operating Features of the PT4741 Quad-Output DC/DC Converter for DSL Line Drivers Balanced Load Fault Protection Under-Voltage Lock-Out A balanced load fault is the result of excess current flowing from one +Vo output directly to the corresponding –Vo output. The current flowing in or out of the COM node (pins 19 & 24) under this condition is within normal operating limits. Both (±)dual outputs from the PT4741 DC/DC converter incorporate protection against this type of load fault. This includes an absolute current limit in combination with a fault timeout period. When the balanced fault current from either ±dual output exceeds the “Balanced Load Current Limit Threshold” (see data sheet specifications), the converter initially limits the fault current to approximately 200% of the maximum output current rating. If the fault persists for more than 200ms the converter shuts down, forcing the voltage at all four regulated outputs to simultaneously fall to zero. Following shutdown the converter will periodically attempt to recover by executing a soft-start power-up. The converter will continually cycle through successive over-current shutdowns and restarts until the fault is removed. The Under-Voltage Lock-Out (UVLO) circuit prevents operation of the converter whenever the input voltage to the module is insufficient to maintain output regulation. The UVLO has approximately 2V of hysterisis. This is to prevent oscillation with a slowly changing input voltage. Below the UVLO threshold the module is off and the enable control inputs, EN1 and EN2 are inoperative. Imbalanced Load Fault Protection An imbalanced load fault is the result of excess current flowing between any one of the +Vo (or the –Vo) outputs, and the COM node (pins 19 & 24). When the current sensed in the COM node exceeds the “Unbalanced Load Shutdown Threshold” (see data sheet specifications), the PT4741 shuts down and latches off within 1ms. Once latched off, the module must be reset by momentarily interrupting the input power source. Over-Temperature Protection The PT4741 DC/DC converter has an internal temperature sensor, which monitors the temperature of the module’s internal components. If the sensed temperature exceeds a nominal 115°C, the converter will shut down. The converter will automatically restart when the sensed temperature returns to about 100°C. Primary-Secondary Isolation The PT4741 DC/DC converter incorporates electrical isolation between the input terminals (primary) and the output terminals (secondary). All converters are production tested to a withstand voltage of 1500VDC. The isolation complies with UL60950 and EN60950, and the requirements for operational isolation. This allows the converter to be configured for either a positive or negative input voltage source. The regulation control circuitry for these modules is located on the secondary (output) side of the isolation barrier. Control signals are passed between the primary and secondary sides of the converter. The data sheet ‘Pin Descriptions’ and ‘Pin-Out Information’ provides guidance as to which reference (primary or secondary) that must be used for each of the external control signals. Input Current Limiting The converter is not internally fused. For safety and overall system protection, the maximum input current to the converter must be limited. Active or passive current limiting can be used. Passive current limiting can be a fast acting fuse. A 125-V fuse, rated no more than 10A, is recommended. Active current limiting can be implemented with a current limited “Hot-Swap” controller. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT4741 Adjusting the Output Voltages of the PT4701 & PT4741 Quad-Output DC/DC Converters The PT4741 quad-output DC/DC converter produces two pairs of balanced ±Vo complimentary output voltages. The magnitude of each balanced pair of outputs may be adjusted higher or lower by up to ±10%. The adjustment method uses a single external resistor 1, which adjusts the magnitude of the respective +Vo and –Vo simultaneously. The value of the resistor determines the magnitude of adjustment, and the placement of the resistor determines the direction of adjustment (increase or decrease). The resistor values can be calculated using the appropriate formula (see below). The formula constants are provided in Table 3-2. Alternatively the resistor value may be selected directly from Table 3-3 and Table 3-4, for ±Vo1 and ±Vo2 respectively. The placement of each resistor is as follows. Adjust Down: To decrease the magnitude of the complimentary output voltages, add a resistor (R2), between the appropriate Vo x Adj (Vo1 Adj or Vo2 Adj,) and the +Vo x voltage rail. See Figure 3-1(b) and Table 3-1 for the resistor placement and pin connections. Figure 3-1b To adjust the magnitude of a +V o & –V o pair lower PT4741 # ±V x Adj (R 2) # +Vo x Adjust Up: To increase the magnitude of the complimentary output voltages, add a resistor R1 between the appropriate ±Vox Adj (‘±Vo1 Adj’ or ‘±Vo2 Adj’) and the -Vox voltage rail. See Figure 3-1(a) and Table 3-1 for the resistor placement and pin connections. +Vo x COM # –Vo x –Vo x # - See Table 3-1 for pin connections, where ±Vo x indicates ±Vo 1, or ±Vo 2 Figure 3-1a Table 3-1; Adjust Resistor Pin Connections To adjust the magnitude of a +V o & –Vo pair higher PT4741 ±V x Adj # To Adjust Up Connect R1 from to R1 +Vo x # ±Vox Adj +Vo x To Adjust Down Connect (R2) from to ±Vox Adj +Vox ±Vo1 21 –Vox 20 21 18 ±Vo2 26 25 26 23 COM –Vo x # –Vo x # - See Table 3-1 for pin connections, where ±Vo x indicates ±Vo 1, or ±Vo 2 Notes: 1. Use only a single 1% (or better) tolerance resistor in either the R1 or (R2) location to adjust a specific output. Place the resistor as close to the ISR as possible. 2. Never connect capacitors to any of the ‘Vox Adj’ pins. Any capacitance added to these control pins will affect the stability of the respective regulated output. Calculation of Resistor Adjust Values The adjust resistor value may also be calculated using an equation. Note that the equation for R1 [Adjust Up] is different to that for (R2) [Adjust Down]. R1 [Adjust Up] = (R2) [Adjust Down] = Where: Vo Va Vr Ro Rs For technical support and more information, see inside back cover or visit www.ti.com = = = = = 2 Vr Ro Va – Vo – Rs kΩ Ro (2 Va – Vr ) – Rs 2 (Vo – Va ) kΩ Original output voltage (±Vox) Adjusted output voltage (±Vax) The reference voltage from Table 3-2 The resistance value in Table 3-2 The series resistance from Table 3-2 Application Notes continued PT4741 Table 3-2 ADJUSTMENT RANGE AND FORMULA PARAMETERS Vo(nom) Va(min) Va(max) Vr Ro (kΩ) Ω) Rs (kΩ ±Vo1 Bus ±Vo2 Bus 8.0V 7.2V 8.8V 2.5V 14.3 20.0 3.94V 3.55 4.33 1.24V 13.0 16.2 Table 3-3 ADJUSTMENT RESISTOR VALUES FOR ±Vo1 Table 3-4 ADJUSTMENT RESISTOR VALUES FOR Vo2 Adj. Resistor Adj. Resistor % Adjust ±Va(req’d) –10% 7.20V – 9% 7.28V – 8% 7.36V – 7% 7.44V – 6% 7.52V – 5% 7.60V – 4% 7.68V – 3% 7.76V – 2% 7.84V – 1% 7.92V 0% 8.00V + 1% 8.08V + 2% 8.16V + 3% 8.24V + 4% 8.32V + 5% 8.40V + 6% 8.48V + 7% 8.56V + 8% 8.64V + 9% 8.72V +10% 8.80V R1 = Black, R2 = (Blue) R1/(R 2) (86.4)kΩ (99.8)kΩ (117.0)kΩ (138.0)kΩ (167.0)kΩ (207.0)kΩ (267.0)kΩ (368.0)kΩ (569.0)kΩ (1.17)MΩ 203.0kΩ 91.7kΩ 54.5kΩ 35.9kΩ 24.7kΩ 17.2kΩ 11.9kΩ 7.9kΩ 4.8kΩ 2.3kΩ R1/(R 2) ±Va(req’d) 3.546V (80.3)kΩ 3.585V (92.5)kΩ 3.625V (108.0)kΩ 3.664V (127.0)kΩ 3.704V (153.0)kΩ 3.743V (190.0)kΩ 3.782V (245.0)kΩ 3.822V (336.0)kΩ 3.861V (519.0)kΩ 3.900V (1.07)MΩ 3.940V 3.979V 188.0kΩ 4.019V 86.1kΩ 4.058V 52.0kΩ 4.098V 34.9kΩ 4.137V 24.7kΩ 4.176V 17.9kΩ 4.216V 13.0kΩ 4.255V 9.4kΩ 4.295V 6.5kΩ 4.334V 4.3kΩ R1 = Black, R2 = (Blue) For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT4741 Using the On/Off Enable Controls on the PT4741 Quad-Output DC/DC Converter The PT4741 is a quad-output DC/DC converter that is specifically designed for powering DSL line driver ICs. The converter incorporates two output enable controls. EN1 (pin 4) is the Negative Enable input, and EN2 (pin 3) is the Positive Enable input. Both inputs are electrically referenced to –Vin (pin 2) on the primary or input side of the converter. A pull-up resistor is not required, but may be added if desired. Voltages of up to 70V can be safely applied to the either of the Enable pins. pin 4 in order to enable the outputs of the converter. An example of this configuration is detailed in Figure 2. Note: The converter will only produce and output voltage if a valid input voltage is applied to ±Vin. Figure 2; Negative Enable Configuration DC/DC Module 3 4 EN 2 EN 1* BSS138 1 =Outputs On Automatic (UVLO) Power-Up Connecting EN1 (pin 4) to -Vin (pin 2) and leaving EN2 (pin 3) open-circuit configures the converter for automatic power up. (See data sheet “Typical Application”). The converter control circuitry incorporates an “Under Voltage Lockout” (UVLO) function, which disables the converter until the minimum specified input voltage is present at ±Vin. (See data sheet Specifications). The UVLO circuitry ensures a clean transition during power-up and power-down, allowing the converter to tolerate a slowrising input voltage. For most applications EN1 and EN2, can be configured for automatic power-up. Positive Output Enable (Negative Inhibit) To configure the converter for a positive enable function, connect EN1 (pin 4) to -Vin (pin 2), and apply the system On/Off control signal to EN2 (pin 3). In this configuration, a low-level input voltage (-Vin potential) applied to pin 3 disables the converter outputs. Figure 1 is an example of this configuration. Figure 1; Positive Enable Configuration –VIN 2 –Vin On/Off Output Voltage Sequencing The PT4741 converter power-up characteristics meet the requirements of Texas Instruments’ TNETD7112 dual-channel line-interface driver/receiver ICs. All four outputs from the converter are internally sequenced to power up in unison. Figure 3 shows the waveforms from a PT4741 following the application of power. There is a delay of appoximately 25ms from the application power to the point that the output voltages begin to rise. The converter typically produces a fully regulated output within 75ms.The waveforms of Figure 3 were measured with loads of approximately 50% on each output, with an input source of 48VDC. Figure 3; PT4741 Power-up Sequence DC/DC Module 3 4 BSS138 +Vo1 (2V/Div) EN 2 EN 1* +Vo2 (2V/Div) 1 =Outputs Off –VIN 2 –Vin –Vo2 (2V/Div) Negative Output Enable (Positive Inhibit) To configure the converter for a negative enable function, EN2 (pin 3) is left open circuit, and the system On/Off control signal is applied to EN1 (pin 4). A low-level input voltage (-Vin potential) must then be applied to –Vo1 (2V/Div) HORIZ SCALE: 10ms/Div For technical support and more information, see inside back cover or visit www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated