PT6470 Series
14-A 3.3-V Input Adjustable
Integrated Switching Regulator
SLTS180A - JANUARY 2003 - REVISED JUNE 2003
Features
•
•
•
•
•
•
•
•
3.3 V Input
14 A Output Current
Low-Profile (8mm)
DSP Compatible
High Efficiency (Up to 95%)
Adjustable Output Voltage
On/Off Inhibit Function
Pre-Bias Start-up Capability
Description
Ordering Information
The PT6470 Excalibur™ series of integrated
switching regulators (ISRs) combines outstanding power density with a comprehensive list of
features. They are an ideal choice for applications
where board space is a premium and performance
cannot be compromised. These modules provide a
full 14 A of output current, yet are housed in a
low-profile, 12-pin, package that is almost half
the size of the previous generation of products.
The integral copper case construction requires
no heatsink, and offers the advantages of solderability and a small footprint (0.64 in² for suffix
‘N’). Both through-hole and surface mount pin
configurations are available.
The PT6470 series operates from a 3.3-V
input to provide a convenient point-of-load power
source for the industry’s latest high-performance
DSPs and microprocessors. The series includes
output voltage options as low as 1.0V DC.
Other features include external output voltage
adjustment, on/off inhibit, pre-bias startup, short
circuit protection, and an output remote sense.
PT6472H
PT6473H
PT6474H
PT6475H
PT6476H
PT6477H
•
•
•
•
Over-Current Protection
Output Remote Sense
Optional Output Capacitor
Small Footprint
(0.64 in², Suffix ‘N’)
• Surface Mount Compatible
• IPC Lead Free 2
Pin-Out Information
Pin Function
= 2.5 Volts
= 2.0 Volts
= 1.8 Volts
= 1.5 Volts
= 1.2 Volts
= 1.0 Volts
PT Series Suffix (PT1234x )
Case/Pin
Configuration
Order
Suffix
Inhibit*
2
3
Vin
Vin
4
Vin
5
GND
6
7
GND
GND
8
GND
9
Vout
Package
Code
10
11
Vout
+V sense
(EPH)
(EPJ)
(EPK)
12
Vo Adjust
N
A
C
Vertical
Horizontal
SMD
1
(Reference the applicable package code drawing for the dimensions and PC board layout)
* Denotes negative logic:
Open = Output enabled
Ground = Output disabled
Standard Application
Vo Adjust
+VSENSE
12
2–4
PT6470
1
+
CIN
470 µF
(Required)
VOUT
9–10
5–8
COUT
330 µF
(Optional)
+
VIN
11
L
O
A
D
Inhibit
GND
GND
Cin = Required 470 µF
Cout = Optional 330 µF
For technical support and more information, see inside back cover or visit www.ti.com
PT6470 Series
14-A 3.3-V Input Adjustable
Integrated Switching Regulator
Specifications
SLTS180A - JANUARY 2003 - REVISED JUNE 2003
(Unless otherwise stated, T a =25 °C, V in =3.3 V, C in =470 µF, Cout =0 µF, and Io =Iomax)
PT6470 SERIES
Typ
Max
Characteristics
Symbols
Conditions
Min
Output Current
Input Voltage Range
Set-Point Voltage Tolerance
Temperature Variation
Line Regulation
Load Regulation
Total Output Variation
Io
Vin
Vo tol
∆Regtemp
∆Regline
∆Regload
∆Regtot
Vin =3.3 V
Over Io range
0
2.95
—
—
—
—
—
—
—
±0.5
±10
±12
14
3.65
±2
—
—
—
A
V
%Vo
%Vo
mV
mV
—
—
±3
%Vo
Efficiency
η
—
—
—
—
—
—
—
93
92
91
89
87
85
20
—
—
—
—
—
—
—
mVpp
—
—
—
—
—
50
100
27.5
±15 (1) (2)
300
—
—
—
—
—
µSec
mV
A
%
kHz
Vin –0.5
–0.2
—
—
470 (4)
0
–40 (6)
—
–40
—
—
–10
10
—
330 (5) (6)
—
—
—
Open (3)
0.8
—
—
—
3,300
85 (7)
215 (8)
125
V
µA
mA
µF
µF
°C
°C
°C
8.0
—
—
106 Hrs
—
500
—
G’s
—
—
20
20 (9)
10
—
—
G’s
grams
Vo Ripple (pk-pk)
Transient Response
Over-Current Threshold
Output Voltage Adjust
Switching Frequency
Inhibit Control (pin1)
Input High Voltage
Input Low Voltage
Input Low Current
Inhibit Input Current
External Input Capacitance
External Output Capacitance
Operating Temperature Range
Solder Reflow Temperature
Storage Temperature
Reliability
Vr
ttr
∆Vtr
ITRIP
Vo adj
ƒs
VIH
VIL
IIL
Iin inhibit
Cin
Cout
Ta
Treflow
Ts
MTBF
Mechanical Shock
Mechanical Vibration
Weight
Flammability
—
—
–40 °C <Ta < +85 °C
Over Vin range
Over Io range
Includes set-point, line, load,
–40 °C ≤ Ta ≤ +85 °C
PT6472 (2.5 V)
Io =10 A
PT6473 (2.0 V)
PT6474 (1.8 V)
PT6475 (1.5 V)
PT6476 (1.2 V)
PT6477 (1.0 V)
20MHz bandwidth
1 A/µs load step, 50 to 100 % I omax,
Cout =330 µF
Recovery Time
Vo over/undershoot
Reset, followed by auto-recovery
Over Vin and Io ranges
Referenced to GND (pins 5–8)
Pin 1 to GND
Pin 1 to GND
Over Vin range
Surface temperature of module pins or case
—
Per Bellcore TR-332
50 % stress, Ta =40 °C, ground benign
Mil-STD-883D, Method 2002.3
Half Sine, mounted to a fixture
Mil-STD-883D, Method 2007.2,
Suffix N
20-2000 Hz, PCB mounted
Suffixes A, C
—
Materials meet UL 94V-0
Units
%
Notes: (1) This is a typical value. For the adjustment limits of a specific model consult the related application note on output voltage adjustment.
(2) The output voltage of the PT6472 (2.5 V) should not be adjusted higher than 2.5 V.
(3) The Inhibit control (pin 1) has an internal pull-up, and if left open-circuit the module will operate when input power is applied. A small low-leakage
(<100 nA) MOSFET is recommended to control this input. See application notes for more information.
(4) A 470 µF electrolytic input capacitor is required for proper operation. The capacitor must be rated for a minimumm of 0.7 Arms of ripple current.
(5) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load will improve the transient response.
(6) For operation below 0 °C, COUT must have stable characteristics. Use either low-ESR tantalum or Oscon® type capacitors.
(7) See SOA curves or consult factory for the appropriate derating.
(8) During solder reflow of SMD package version do not elevate the module case, pins, or internal component temperature above a peak of 215 °C. For
further guidance refer to the application note, “Reflow Soldering Requirements for Plug-in Power Surface Mount Products,” (SLTA051).
(9) The case pins on the through-hole package types (suffixes N & A) must be soldered. For more information see the applicable package outline drawing.
For technical support and more information, see inside back cover or visit www.ti.com
PT6470 Series
14-A 3.3-V Input Adjustable
Integrated Switching Regulator
SLTS180A - JANUARY 2003 - REVISED JUNE 2003
Pin Descriptions
VIN: The positive supply voltage input for the module
with respect to the common GND.
VOUT: This is the regulated output voltage from the module with respect to the common GND.
GND: The common node to which the input, output, and
external control signals are referenced.
Inhibit*: This is an open-collector (open-drain) negative
logic input that is referenced to GND. Pulling this pin
low disables the module’s output voltage. If Inhibit* is
left open-circuit, the output will be active whenever a
valid input source is applied.
Vo Adjust: This pin is used to trim the output voltage
over a typical range of ±15 % of nominal. The adjustment method uses an external resistor. The resistor is
connected from Vo Adjust to either the GND or (+)Sense,
in order to adjust the output either up or down, respectively.
Vsense: An external remote sense input is provided to
allow the regulation circuit to compensate for voltage
drop between the module and the load. For optimal
voltage accuracy Vsense should be connected to VOUT. If
desired, Vsense may also be left open circuit.
Typical Characteristics
Performance Data; Vin =3.3 V (See Note A)
Efficiency vs Output Current
Power Dissipation vs Output Current
100
5
4
PT6472
PT6473
PT6474
PT6475
PT6476
PT6477
80
70
60
Pd - Watts
Efficiency - %
90
3
2
1
50
0
0
2
4
6
8
10
12
14
0
Iout (A)
2
4
6
8
Iout (A)
Output Ripple vs Output Current
35
30
Ripple - mV
25
PT6475
PT6474
PT6473
PT6476
PT6477
PT6472
20
15
10
5
0
0
2
4
6
8
10
12
14
Iout (A)
Note A: Characteristic data has been developed from actual products tested at 25 °C. This data is considered typical data for the ISR.
For technical support and more information, see inside back cover or visit www.ti.com
10
12
14
Typical Characteristics
PT6470 Series
14-A 3.3-V Input Adjustable
Integrated Switching Regulator
SLTS180A - JANUARY 2003 - REVISED JUNE 2003
Safe Operating Curve, Vin =3.3 V (See Note B)
90
PT6472; VOUT =2.5 V
Ambient Temperature (°C)
80
Airflow
70
200LFM
120LFM
60LFM
Nat Conv
60
50
40
30
20
0
2
4
6
8
10
12
14
Iout (A)
90
PT6477; VOUT =1 V
Ambient Temperature (°C)
80
Airflow
70
200LFM
120LFM
60LFM
Nat Conv
60
50
40
30
20
0
2
4
6
8
10
12
14
Iout (A)
Note B: SOA curves represent operating conditions at which internal components are at or below manufacturer’s maximum rated operating temperatures.
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT6460 & PT6470 Series
Operating Features and System Considerations
for the PT6460 & PT6470 Regulator Series
The PT6460 (5-V input) and the PT6470 (3.3-V input)
series of integrated switching regulators (ISRs) provide
step-down voltage conversion for output loads of up to
14 A.
Power up & Soft-Start Timing
Following either the application of a valid input source
voltage, or the removal of a ground signal to the Inhihit*
control pin (with input power applied), the regulator will
initiate a soft-start power up. A soft start slows the rate at
which the output voltage rises and introduces a short time
delay, td (approximately 2 ms), into the power-up sequence.
Figure 1-1 shows the power-up characteristic of a PT6464
(5-V input, 1.8-V output) with a 8.5-A load.
Figure 1-1
Vo (1V/Div)
Output Remote Sense
The (+)Sense pin allows the regulator to compensate for
limited amounts of ‘IR’ voltage drop in the positive output
connection resistance. This is the voltage drop incurred
in the PCB trace between Vout (pins 9 & 10) of the regulator and the load some distance away. Connecting (+)Sense
to the positive load terminal improves the voltage regulation at the load, particularly when the load current
fluctuates. Although not recommended, leaving (+)Sense
disconnected will not damage the regulator or the load
circuitry. An internal 10 Ω resistor, connected between
the sense pin and the output, keeps the output voltage in
regulation.
With the sense pin connected, the difference between
the voltage measured between V out and GND at the
regulator, and that measured from (+)Sense to GND, is
the amount of IR drop being compensated by the regulator. This should be limited to 0.3 V maximum.
Note: The remote sense feature is not designed to compensate
for the forward drop of non-linear or frequency dependent
components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors,
ferrite beads, and fuses. When these components are enclosed
by the remote sense connections they are effectively placed
inside the regulation control loop, which can adversely affect
the stability of the regulator.
Vin (2V/Div)
Pre-Bias Startup
td
Iin (2A/Div)
HORIZ SCALE: 5ms/Div
Over-Current Protection
To protect against load faults, these ISRs incorporate
output over-current protection. Applying a load that
exceeds the over-current threshold (see data sheet specifications) will cause the regulated output to shut down.
Following shutdown the ISR will periodically attempt to
recover by initiating a soft-start power-up. This is often
described as a “hiccup” mode of operation, whereby the
module continues in a cycle of successive shutdown and
power up until the load fault is removed. During this
period, the average current flowing into the fault is
significantly reduced. Once the fault is removed, the
converter automatically recovers and returns to normal
operation.
In complex digital systems an external voltage can sometimes be present at the output of the regulator during
power up. For example, this voltage may be backfed
through a dual-supply logic component such as an FPGA
or ASIC. Another path might be via a clamp diode (to a
lower supply voltage) as part of a power-up sequencing
implementation.
Although the PT6460 (5-V input) and PT6470 (3.3-V
input) series of regulators will sink current under steadystate conditions, they will not do so during startup. This
feature allows these regulators to start up while an external
voltage is simultaneously applied to the output. To facilitate
this feature the input voltage must always be greater than
or equal to the output voltage throughout the power-up
and power-down sequence. Startup includes both the
application of a valid input source voltage, or the removal
of a ground signal from the Inhibit* control (pin 1) with
a valid input source applied. The output of the regulator
is also effectively off (tri-state), during the period that
the Inhibit* control is held low.
Note: If the pre-bias is greater than the nominal regulation
voltage, the module will begin sinking current at the end of its
soft-start power-up sequence. This could overstress the regulator if
the current exceeds its rated output.
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT6460 & PT6470 Series
Capacitor Recommendations for the
PT6460 & PT6470 Regulator Series
Input Capacitor:
The recommended input capacitor is determined by a
minimum of 470 µF capacitance and 700 mA minimum
ripple current rating.
Ripple current and <100 mΩ equivalent series resistance
(ESR) values are the major considerations, along with
temperature, when when designing with different types
of capacitors. Tantalum capacitors have a recommended
minimum voltage rating of 2× (maximum DC voltage +
AC ripple). This is necessary to insure reliability for
input voltage bus applications.
Output Capacitors (Optional):
The ESR of the capacitors should be less than 150 mΩ.
Electrolytic capacitors have marginal ripple performance at
frequencies greater than 400 kHz but excellent low frequency transient response. Above the ripple frequency,
ceramic capacitors are necessary to improve the transient
response and reduce any high frequency noise components
apparent during higher current excursions. Preferred low
ESR type capacitor part numbers are identified in Table 2-1.
Tantalum Capacitors( Optional Output Capacitors)
Tantalum type capacitors can be used for the output but
only the AVX TPS, Sprague 593D/594/595, or Kemet
T495/T510 series. These capacitors are recommended
over many other tantalum types due to their higher rated
surge, power dissipation, and ripple current capability.
As a caution the TAJ series by AVX is not recommended.
This series has considerably higher ESR, reduced power
dissipation, and lower ripple current capability. The TAJ
series is less reliable than the AVX TPS series when determining power dissipation capability. Tantalum or Oscon®
types are recommended for applications where ambient
temperatures fall below 0 °C.
Capacitor Table
Table 2-1 identifies the characteristics of capacitors from
a number of vendors with acceptable ESR and ripple
current (rms) ratings. The number of capacitors required
at both the input and output buses is identified for each
capacitor type.
This is not an extensive capacitor list. Capacitors from other
vendors are available with comparable specifications. Those listed
are for guidance. The RMS ripple current rating and ESR
(at 100kHz) are critical parameters necessary to insure both
optimum regulator performance and long capacitor life.
Table 2-1: Input/Output Capacitors
Capacitor Vendor/
Series
Capacitor Characteristics
Quantity
Working
Voltage
Value(µF)
(ESR) Equivalent
Series Resistance
Maximum Ripple
Current @105°C
(Irms)
Physical Size
(mm)
Input
Bus
Output
Bus
Panasonic
FC (Radial)
16 V
10 V
470
560
0.09 Ω
0.09 Ω
755 mA
755 mA
10x12.5
10×12.5
1
1
1
1
EEUFC1C471
EEUFC1A561
FK (SMT)
25 V
35 V
470
470
0.08 Ω
0.06 Ω
850 mA
1100 mA
10x10.2
12.5×13.5
1
1
1
1
EEVFK1E471P
EEVFK1V471Q
16 V
10 V
10 V
470
680
680
0.090 Ω
0.090 Ω
0.015 Ω
760 mA
770 mA
4735 mA
10x12.5
10x12.5
10×10.5
1
1
1
1
1
1
LXZ16VB471M10X12LL
LXZ10VB681M10X12LL
10FX680M
Nichicon PL/PM
16 V
16 V
330
470
0.12÷2=0.06 Ω
0.09 Ω
745 mA
770 mA
10x12.5
10x15
2
1
1
1
UPM1C331MPH6
UPM1C 471MPH6
NX Series (SMT)
10 V
330
0.024 Ω
3770 mA
10x8
2
1
PNX1A330MCAR1GS
Sanyo-Os-con SP
SVP (SMT)
10 V
10 V
470
560
0.015 Ω
0.013 Ω
>4500 mA
>5200 mA
10×10.5
11×12.7
1
1
1
1
10SP470M
10SVP560M
AVX Tantalum
TPS (SMT)
10 V
10 V
470
470
0.045 Ω
0.060 Ω
1723 mA
1826 mA
7.3L×5.7W
×4.1H
1
1
1
1
TPSE477M010R0045
TPSV477M010R0060
Kemet Polymer
Tantalum
T520/T530 (SMT)
10 V
10 V
330
330
0.040 Ω
0.015 Ω
1800 mA
>3800 mA
4.3W×7.3L
×4.0H
2
2
1
1
T520X337M010AS
T530X337M010AS
Sprague Tantalum
594D (SMT)
10 V
680
0.090 Ω
1660 mA
7.2L×6W
×4.1H
1
1
595D687X0010R2T
United Chemi-con
LXZ/LXV
FX
Vendor Part Number
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT6460 & PT6470 Series
Adjusting the Output Voltage of the PT6460 &
PT6470 ISR Series
The output voltage of the PT6460 (5-V input) and the
PT6470 (3.3-V input) series of power modules may be
adjusted higher or lower than the pre-set voltage. The
adjustment method requires a single external resistor.
The value of the resistor can either be calculated using
the formulas given below, or simply selected from the
range of values given in Table 3-2. Table 3-1 gives the
allowable adjustment range for each model as V a (min)
and Va (max). Refer to Figure 3-1 for the placement of
the required resistor. Resistor R1 adjusts the output voltage
up, and the resistor (R2) adjusts it down.
The values of (R1) [adjust down], and R2 [adjust up],
can be calculated using the following formulas. Refer to
Figure 3-1 for the placement of the required resistor;
either (R1) or R2 as appropriate.
Ro (Va – 0.8)
Vo – Va
(R1)
=
R2
=
Where:
Vo
Va
Ro
Rs
Adjust Up: An increase in the output voltage is obtained
by adding a resistor R2, between Vo Adjust (pin 12) and
GND (pin 5).
0.8 Ro
Va – Vo
– Rs
kΩ
– Rs
kΩ
= Original output voltage
= Adjusted output voltage
= The resistance value from Table 3-1
= The series resistance from Table 3-1
Adjust Down: Add a resistor (R1), between Vo Adjust (pin 12)
and +Vsense (pin 11).
Notes:
1. Use a 1 % (or better) tolerance resistor in either the (R1)
or R2 location. Place the resistor as close to the ISR as
possible.
Figure 3-1
2. Never connect capacitors from Vo adj to either GND or
Vout. Any capacitance added to the Vo adjust pin will affect
the stability of the ISR.
11
+Vsense
+VIN
2–4
PT6460/70
Vin
Inhibit*
1
CIN
560 µF
(Req'd)
GND
5–8
Vout
+VO
9–10
Vo(adj)
3. If the remote sense feature is not being used, the adjust
resistor (R1) can also be connected to Vout, (pins 9–10)
instead of +Vsense.
12
(R 1)
Adj Down
+
COUT
330 µF
(Optional)
4. The PT6472 may not be adjusted higher than the
nominal output voltage of 2.5 V. There is insufficient
input voltage to allow for any increase in output voltage.
+
R2
Adjust Up
COM
COM
Table 3-1
ISR OUTPUT VOLTAGE ADJUSTMENT RANGE AND FORMULA PARAMETERS
Series Pt. Nos.
5-V Bus:
PT6461
PT6462
PT6463
PT6464
3.3-V Bus:
N/A
PT6472
PT6473
PT6474
PT6465
PT6475
PT6466
PT6476
PT6467
PT6477
Vo (nom)
3.3 V
2.5 V
2.0 V
1.8 V
1.5 V
1.2 V
1V
Va (min)
2.6 V
2.0 V
1.66 V
1.52 V
1.31 V
1.1 V
0.95 V
Va (max)
3.63 V
2.8 V *
2.32 V
2.1 V
1.82 V
1.52 V
Ω)
Ro (kΩ
10.2
10.7
10.0
10.2
Ω)
Rs (kΩ
24.9
24.9
24.9
24.9
9.76
24.9
* The PT6472 may not be adjusted higher than its nominal output voltage of 2.5 V. See note 4
For technical support and more information, see inside back cover or visit www.ti.com
1.32 V
10.0
10.2
24.9
24.9
Application Notes continued
PT6460, PT6470 Series
Table 3-2
ISR ADJUSTMENT RESISTOR VALUES
Series Pt. Nos.
5.0V Bus:
PT6461
PT6462
3.3V Bus:
N/A
PT6472
Vo (nom)
3.3 V
2.5 V
Va (req.d)
PT6463
PT6473
2.0 V
PT6464
PT6474
1.8 V
PT6465
PT6475
1.5 V
PT6466
PT6476
1.2 V
PT6467
PT6477
1.0V
Va (req.d)
3.60
2.3 kΩ
2.300
3.55
7.7 kΩ
2.250
7.1 kΩ
3.50
15.9 kΩ
2.200
15.1 kΩ
3.45
29.5 kΩ
2.150
28.4 kΩ
3.40
56.7 kΩ
2.100
55.1 kΩ
3.35
138.0 kΩ
2.050
135.0 kΩ
3.30
1.8 kΩ
2.000
2.3 kΩ
7.7 kΩ
15.9 kΩ
3.25
(475.0) kΩ
1.950
(205.0) kΩ
3.20
(220.0) kΩ
1.900
(85.1) kΩ
56.7 kΩ
3.15
(135.0) kΩ
1.850
(45.1) kΩ
138.0 kΩ
3.10
(92.4) kΩ
1.800
(25.1) kΩ
3.05
(66.9) kΩ
1.750
(13.1) kΩ
(169.0) kΩ
6.3 kΩ
3.00
(49.9) kΩ
1.700
(5.1) kΩ
(66.9) kΩ
14.1 kΩ
2.95
(37.5) kΩ
1.650
(32.9) kΩ
27.2 kΩ
2.90
(28.6) kΩ
1.600
(15.9) kΩ
53.2 kΩ
2.85
(21.6) kΩ
1.550
(5.7) kΩ
131.0 kΩ
2.80
(15.9) kΩ
3.6 kΩ
1.500
2.75
(11.3) kΩ
9.3 kΩ
1.475
(239.0) kΩ
2.70
(7.4) kΩ
17.9 kΩ
1.450
(102.0) kΩ
7.1 kΩ
2.65
(4.1) kΩ
32.2 kΩ
1.425
(56.4) kΩ
10.7 kΩ
2.60
(1.3) kΩ
60.7 kΩ
1.400
(33.7) kΩ
15.1 kΩ
146.0 kΩ
1.375
(20.0) kΩ
20.8 kΩ
1.350
(10.9) kΩ
28.4 kΩ
(4.4) kΩ
39.1 kΩ
2.550
2.500
29.5 kΩ
1.1 kΩ
1.8 kΩ
4.2 kΩ
2.450
See note 4 (328.0) kΩ
1.325
2.400
(146.0) kΩ
1.300
55.1 kΩ
2.3 kΩ
2.350
(85.7) kΩ
1.275
81.8 kΩ
4.8 kΩ
2.300
(55.3) kΩ
1.250
135.0 kΩ
7.7 kΩ
2.250
(37.2) kΩ
1.225
295.0 kΩ
11.4 kΩ
2.200
(25.0) kΩ
1.200
2.150
(16.4) kΩ
1.175
(125.0) kΩ
21.7 kΩ
2.100
(9.9) kΩ
1.150
(45.1) kΩ
29.5 kΩ
2.050
(4.8) kΩ
1.125
(18.4) kΩ
40.4 kΩ
2.000
(0.8) kΩ
1.100
(5.1) kΩ
56.7 kΩ
15.9 kΩ
1.075
83.9 kΩ
1.050
138.0 kΩ
1.025
302.0 kΩ
1.000
R1 = Black
0.975
(46.5) kΩ
0.950
(5.7) kΩ
R2 = (Blue)
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT6460 & PT6470 Series
Using the Inhibit Control of the PT6460 & PT6470
Series of Step-Down ISRs
The PT6460 (5-V input) and the PT6470 (3.3-V input)
series of integrated switching regulators (ISRs) provide
step-down voltage conversion for output loads of up to
14 A. For applications that require the output voltage
to be held off, these ISRs incorporate an Inhibit* control
(pin 1). The Inhibit* control input can be used for powerup sequencing or whenever there is a requirement for
the output voltage from the ISR to be turned off.
The ISR functions normally with pin 1 open circuit,
providing a regulated output whenever a valid source
voltage is applied between Vin (pins 2–3) and GND (pins
5–8). When a low-level ground signal is applied to pin 1,
the regulator output is turned off 2 and the input current
is significantly reduced 3.
Turn-On Time: In the circuit of Figure 4-1, turning Q1 on
applies a low-voltage to the Inhibit* control (pin 1) and
disables the output of the regulator 2. If Q1 is then turned
off, the ISR executes a soft-start power up. Power up
consists of a short delay (approx. 2 msec), followed by a
period in which the output voltage rises to the full regulation voltage. The module produces a regulated output
voltage within 10 msec. Figure 4-2 shows the typical rise
in both the output voltage and input current for a PT6464
(1.8 V), following the turn-off of Q1. The turn off of Q1
corresponds to the rise in the waveform, Q1 Vds. The
waveforms were measured with a 5VDC input voltage,
and 8.5-A load.
Figure 4-2
Figure 4-1 shows the typical application of the Inhibit*
function. Note the discrete transistor, Q1. The Inhibit*
control has its own internal pull-up to Vin potential. An
open-collector or open-drain device is recommended to
control this input 1. The voltage thresholds are given in
Table 4-1.
Vo (1V/Div)
Iin (2A/Div)
Table 4-1; Inhibit Control Requirements
Parameter
Enable (VIH)
Disable (VIL)
Min
Typ
Max
Vin – 0.5 V
–0.2 V
—
Open
—
+0.8 V
—
–0.2 mA
—
I IL
Q1Vds (5V/Div)
HORIZ SCALE: 2ms/Div
Figure 4-1
+VSENSE
11
+Vsense
+VIN
2–4
PT6464
Vin
Inhibit*
1
CIN
560 µF
(Req'd)
+
Q1
BSS138
GND
5–8
Vout
VOUT
9–10
Vo(adj)
12
COUT
330 µF
(Optional)
+
L
O
A
D
1 =Inhibit
COM
Notes:
1. Use an open-collector device with a breakdown voltage
of at least 10 V (preferably a discrete transistor) for the
Inhibit* control input. A pull-up resistor is not necessary.
To disable the output voltage the control pin should be
pulled low to less than +0.8 VDC.
GND
2. When a ground signal is applied to the Inhibit* control
(pin 1) the module output is effectively turned off (tristate). The output voltage decays to zero as the load
impedance discharges the output capacitors.
3. When the output is disabled via the Inhibit* pin, the
input current is reduced to approximately 5 to 10 mA.
For technical support and more information, see inside back cover or visit www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PT6472N
ACTIVE
SIP MOD
ULE
EPH
12
21
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
PT6474N
ACTIVE
SIP MOD
ULE
EPH
12
21
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
PT6475A
ACTIVE
SIP MOD
ULE
EPJ
12
21
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
PT6475C
ACTIVE
SIP MOD
ULE
EPK
12
21
Pb-Free
(RoHS)
Call TI
Level-3-215C-168HRS
PT6475N
ACTIVE
SIP MOD
ULE
EPH
12
21
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
PT6476N
ACTIVE
SIP MOD
ULE
EPH
12
21
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MMSI003A – SEPTEMBER 2001 – REVISED JUNE 2002
EPK (R–MSIP–G12)
METAL SINGLE-IN-LINE MODULE
SUFFIX C
0.017 (0,43) TYP.
0.835 (21,21)
MAX.
0.675 (17,14)
MAX.
Gage Plane
Seating Plane
1.71 (43,43) MAX.
0.006 (0,15)
0°–6°
0.080 (2,03)
1
0.315 (8,00)
0.025 (0,63)
TYP.
0.017 (0,43) TYP.
0.160 (4,06) TYP.
0.100 (2,54) TYP.
0.032 (0,81)
TYP.
0.040 (1,01) TYP.
ø0.065 (1,65) MIN. 4 Places
Plated through connected
to ground plane
0.100
(2,54)
0.050
(1,27)
1.770 (44,95)
0.050
(1,27)
1.670 (42,42)
0.050
(1,27)
0.040
(1,01)
Note I
0.200 (5,08)
0.210
(5,33)
0.505
(12,83) 0.670
(17,10)
Note F
1
0.140
(3,55)
0.090
(2,28)
0.070
(1,77)
Note G
Note H
0.100
(2,54)
0.040 (1,01)
0.165
(4,19)
Note E
0.050 (1,27)
12 Places
0.100 (2,54)
11 Places
0.280 (7,11)
0.080 (2,03)
0.285 (7,24)
PC LAYOUT
4203206/B 06/02
NOTES: A.
B.
C.
D.
E.
F.
All linear dimensions are in inches (mm).
This drawing is subject to change without notice.
2 place decimals are " 0.030 (" 0, 76 mm).
3 place decimals are " 0.010 (" 0, 25 mm).
Recommended mechanical keep-out area.
Power pin connections should utilize two or more
vias per input, ground and output pin.
POST OFFICE BOX 655303
G. Vias are recommended to improve copper adhesion.
H. Solder mask openings to copper island for solder
joints to mechanical pins. Electrically connect
case to ground plane.
I. Case outline reference.
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MMSI004 – SEPTEMBER 2001
EPJ (R–MSIP–G12)
METAL SINGLE-IN-LINE MODULE
Suffix A
0.835 (21,21)
MAX.
0.675 (17,14)
MAX.
1.71 (43,43) MAX.
1
0.315 (8,00)
Note G
0.025 (0,63) TYP.
0.160 (4,06) TYP.
0.017 (0,43) TYP.
0.100 (2,54) TYP.
0.032 (0,81)
TYP.
0.140 (3,55) MIN.
See Note F
0.040 (1,01) TYP.
0.050 (1,27)
ø0.065 (1,65) MIN. 4 Places
Plated through connected
to ground plane
1.770 (44,95)
1.670 (42,42)
Note H
0.140 (3,55)
0.505 (12,83)
0.090 (2,28)
0.580 (14,73)
1
0.100 (2,54)
ø0.045 (1,14) MIN.
Plated through
12 Places
Note E
4 Places
0.100 (2,54)
11 Places
0.040 (1,01)
0.280 (7,11)
0.080 (2,03)
0.285 (7,24)
PC LAYOUT
4203205/A 08/01
NOTES: A.
B.
C.
D.
E.
F.
All linear dimensions are in inches (mm).
This drawing is subject to change without notice.
2 place decimals are " 0.030 (" 0, 76 mm).
3 place decimals are " 0.010 (" 0, 25 mm).
Recommended mechanical keep-out area.
Electrical pin length mounted on circuit board
seating plane to pin end.
G. Electrically connect case to ground plane.
H. Case outline reference.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MMSI069 – SEPTEMBER 2001
EPH (R–MSIP–T12)
METAL SINGLE-IN-LINE MODULE
Suffix N
0.48 (12,19) MAX.
0.315 (8,00)
1.71 (43,43) MAX.
0.032 (0,81) TYP.
1
0.040 (1,01) TYP.
0.675 (17,14)
MAX.
Note G
0.025 (0,63) TYP.
0.017 (0,43) TYP.
0.160 (4,06) TYP.
0.100 (2,54) TYP.
0.140 (3,55) MIN.
See Note F
1.75 (44,45)
1.670 (42,42)
0.040 (1,01)
Note E
ø0.065 (1,65) MIN. 4 Places
Plated through. See Note G.
0.51
(12,95)
0.35
(8,89)
1
ø0.045 (1,14) MIN.
Plated through
12 Places
0.040 (1,01)
0.285 (7,24)
0.100 (2,54)
11 Places
0.200 (5,08)
0.080 (2,03)
0.080 (2,03)
2 Places
4203204/A 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (mm).
This drawing is subject to change without notice.
2 place decimals are 0.030 (0,76mm).
3 place decimals are 0.010 (0,25mm).
POST OFFICE BOX 655303
E. Recommended mechanical keep out area.
F. Electrical pin length mounted on circuit board seating
plane to pin end.
G. Electrically connect case to ground plane.
• DALLAS, TEXAS 75265
1
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