Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Features Introduction • Precision supply-voltage monitor The PT7A751X/752X/753X family microprocessor - 4.63V (PT7A7511, 7521, 7531) (µP) supervisory circuits are targeted to improve - 4.38V (PT7A7512, 7522, 7532) reliability and accuracy of power-supply circuitry in - 3.08V (PT7A7513, 7523, 7533) µP systems. These devices reduce the complexity and - 2.93V (PT7A7514, 7524, 7534) number of components required to monitor power- - 2.63V (PT7A7515, 7525, 7535) supply and battery functions. - 2.32V (PT7A7516, 7526, 7536) The main functions are: - 2.20V (PT7A7517, 7527, 7537) • 200ms reset pulse width 1. Asserting reset output during power-µp, power- • Debounced TTL/CMOS-compatible manual- down and brownout conditions for µP system; 2. Detecting power failure or low-battery conditions reset input with a 1.25V threshold detector; • Independent watchdog timer 1.6sec time-out (not 3. Watchdog functions (not for PT7A753x). available for PT7A7531 - 7537) • Reset output signal: Applications - Active-low only (PT7A7511 - 7517) - Active-high only (PT7A7521 - 7527) • Power-supply circuitry in µP systems - Active-high and active-low (PT7A7531 - 7537) • Voltage monitor for power-fail or low battery warning • Guaranteed RESET/RESET valid at VCC = 1.2V PT0082(05/02) 1 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Contents Features ....................................................................................................................................................... 1 Block Diagram ............................................................................................................................................ 1 Introduction ................................................................................................................................................. 1 Pin Information ........................................................................................................................................... 4 Pin Configuration .............................................................................................................................. 4 Pin Description .................................................................................................................................. 4 Functional Description ................................................................................................................................ 5 Reset Output ...................................................................................................................................... 5 Watchdog Timer ................................................................................................................................ 5 Manual Reset ..................................................................................................................................... 5 Power-Fail Comparator ..................................................................................................................... 5 Function Reference Table .................................................................................................................. 6 Detailed Specifications ................................................................................................................................ 7 Absolute Maximum Ratings .............................................................................................................. 7 Recommended Operation Condition ................................................................................................. 7 DC Electrical Characteristics ............................................................................................................. 8 AC Electrical Characteristics ............................................................................................................. 9 Ordering Information ................................................................................................................................ 10 Mechanical Information ............................................................................................................................ 11 Notes ......................................................................................................................................................... 12 PT0082(05/02) 2 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Block Diagram Figure 1. Block Diagram of PT7A7511-7517/7521-7527 WDI Watchdog Transition Detector Vcc 250uA Watchdog Timer WDO Timebase for Reset & Watchdog MR Reset Generator RESET (RESET) Vcc V RST PFI PFO 1.25V Figure 2. Block Diagram of PT7A7531-7537 Vcc 250uA RESET MR Reset Generator RESET Vcc VRST PFI PFO 1.25V PT0082(05/02) 3 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Information Pin Configuration Figure 3. Pin Configuration PT7A7511P-7517P PT7A7511W-7517W 8-Pin PDIP/8-Pin SOIC PT7A7521P-7527P PT7A7521W-7527W 8-Pin PDIP/8-Pin SOIC PT7A7531P-7537P PT7A7531W-7537W 8-Pin PDIP/8-Pin SOIC MR 1 8 WDO MR 1 8 WDO MR 1 8 RESET V CC 2 7 RESET V CC 2 7 RESET V CC 2 7 RESET GND 3 6 WDI GND 3 6 WDI GND 3 6 NC PFI 4 5 PFO PFI 4 5 PFO PFI 4 5 PFO Top View Pin Description Table 1. Pin Description P in Na m e Typ e MR I Vcc Power Power Su p p ly GND Ground G r ou n d R efer en ce for all signals PFI I Power -Fa il Volt a ge Mon it or I n p u t: When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or Vcc when not used. PFO O Power -Fa il O u t p u t : it gets low and sinks current when PFI is less than 1.25V; otherwise PFO stays high. I Wa t ch d og I n p u t: If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and WDO goes low. Floating WDI or connecting WDI to a high-impedance three-state buffer disables the watchdog feature. The internal watchdog timer clears whenever reset is asserted. WDI is threestated, or WDI sees a rising or falling edge. WDI NC Descr ip t ion Ma n u a l-R eset : triggers a reset pulse when pulled below 0.8V, active low. It has an internal 250µA pull-up current and be driven from a TTL or CMOS logic line as well as shorted to ground with a switch. No C on n ect O R eset O u t p u t p u lses: low for 200ms when triggered, and stays low whenever Vcc is below the reset threshold. It remains low for 200ms after Vcc rises above the reset threshold or MR goes from low to high. A watchdog timeout will not trigger RESET unless WDO is connected to MR. WDO O Wa t ch d og O u t p u t : pulls low when the internal watchdog timer finishes its 1.6sec count and does not go high again until the watchdog is cleared. WDO also goes low during low-line conditions. Whenever Vcc is below the reset threshold, WDO stays low; however, unlike RESET, WDO does not have minimum pulse width. As soon as Vcc rises above the reset threshold, WDO goes high with no delay. RESET O T h e inver se of R E SE T: active high. Whenever RESET is high, RESET is low. RESET PT0082(05/02) 4 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Functional Description Watchdog Timer The PT75xx family can assert reset output during power-up, power-down and brownout conditions for uP system, detect power failure or low-battery conditions with a 1.25V threshold detector and have watchdog functions. Refer to Table 2 for their individual features. The typical application see Figure 4. The watchdog circuit monitors the µP’s activity. If the µP does not toggle the watchdog input (WDI) within 1.6sec and WDI is not in high impedance, WDO goes low. As long as RESET is asserted or the WDI input is in high impedance, the watchdog timer will stay cleared and will not count. As soon as reset is released and WDI is driven high or low, the timer will start counting. Pulses as short as 50ns can be detected. Reset Output Typically, WDO will be connected to the non-maskable interrupt input (NMI) of a µP. When VCC drops below the reset threshold, WDO will go low whether or not the watchdog timer has timed out yet. Normally this would trigger an NMI interrupt, but RESET goes low simultaneously, and thus overrides the NMI interrupt. If WDI is left unconnected, WDO can be used as a low-line output. Since floating WDI disables the internal timer, WDO goes low only when VCC falls below the reset threshold, thus functioning as a low-line output. The supervisory circuits can assert reset for a microprocessor during power-up, power-down and brownout to prevent code execution errors. On power-up, once VCC reaches about 1.2V, RESET is a guaranteed logic low of 0.4V or less. As VCC rises, RESET stays low. When VCC rises above the reset threshold, an internal timer releases RESET after about 200ms. RESET pulses low whenever VCC drops below the reset threshold (brownout condition). If brownout occurs in the middle of a previously initiated reset pulse, the pulse continues for at least another 140ms. Manual Reset The manual-reset input (MR) allows reset to be triggered by a push-button switch. The switch is effectively debounced by the 140ms minimum reset pulse width. MR is TTL/CMOS logic compatible, so it can be driven by any logic reset output. On power-down, once VCC falls below the reset threshold, RESET stays low and is guaranteed to be 0.4V or less until Vcc drops below 1V. The PT7A752x and PT7A753x active-high RESET output is simply the complement of the RESET output, and is guaranteed to be valid with VCC down to 1.2V. Some µPs, such as Intel’s 80C51, require an active-high reset pulse. Power-Fail Comparator The power-fail comparator will send out a Low signal once detects a voltage lowered than 1.25V. It can be used for various purposes because its output and non-inverting input are not internally connected. The inverting input is internally connected to a 1.25V reference. Figure 4. Typical Application Circuit IN DC Linear Regulator µP OUT Vcc Vcc RESET µP Supervisory Circuit PFI WDI WDO MR PFO PT0082(05/02) 5 RESET I/O Line NMI Interrupt Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Reference Table Table 2. Function Table of PT7A75xx Family Part No. Reset Threshold PT7A7511 4.63V PT7A7521 PT7A7531 PT7A7512 PT7A7522 Reset Active Low Nom. Reset Time Nom. Watch dog or High (ms), t RS Time (sec), t WD Power Fail Comp. Manual Reset Input 1.6 1.25V detector Yes LOW 200 4.63V HIGH 200 1.6 1.25V detector Yes 4.63V LOW, HIGH 200 unavailable 1.25V detector Yes 4.38V LOW 200 1.6 1.25V detector Yes 4.38V HIGH 200 1.6 1.25V detector Yes PT7A7532 4.38V LOW, HIGH 200 unavailable 1.25V detector Yes PT7A7513 3.08V LOW 200 1.6 1.25V detector Yes PT7A7523 3.08V HIGH 200 1.6 1.25V detector Yes PT7A7533 3.08V LOW, HIGH 200 unavailable 1.25V detector Yes PT7A7514 2.93V LOW 200 1.6 1.25V detector Yes PT7A7524 2.93V HIGH 200 1.6 1.25V detector Yes PT7A7534 2.93V LOW, HIGH 200 unavailable 1.25V detector Yes PT7A7515 2.63V LOW 200 1.6 1.25V detector Yes PT7A7525 2.63V HIGH 200 1.6 1.25V detector Yes PT7A7535 2.63V LOW, HIGH 200 unavailable 1.25V detector Yes PT7A3516 2.32V LOW 200 1.6 1.25V detector Yes PT7A3526 2.32V HIGH 200 1.6 1.25V detector Yes PT7A3536 2.32V LOW, HIGH 200 unavailable 1.25V detector Yes PT7A7517 2.20V LOW 200 1.6 1.25V detector Yes PT7A7527 2.20V HIGH 200 1.6 1.25V detector Yes PT7A7537 2.20V LOW, HIGH 200 unavailable 1.25V detector Yes PT0082(05/02) 6 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Detailed Specifications Absolute Maximum Ratings Storage Temperature ....................................................... -65oC to +150oC Ambient Temperature with Power Applied ....................... -40oC to +85oC Supply Voltage to Ground Potential (Vcc to GND) ........... -0.3V to +7.0V DC Input Voltage (All inputs except Vcc and GND) ..... -0.3V to VCC+0.3V DC Output Current (All outputs) .................................................... 20mA Power Dissipation ........................................................................ 500mW (Depend on package) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operation Condition Table 3. DC Electrical Characteristics Sym VCC Descr ip t ion Min Typ Ma x Un it Supply Voltage for 75x1, 75x2 4.5 5.0 5.5 V Supply Voltage for 75x3, 75x4 3.0 3.3 5.5 V Supply Voltage for 75x5, 75x6, 75x7 2.7 3.0 5.5 V VCC > 4.0V 2.0 2.4 VCC ≤ 4.0V 0.7VCC V 0.7VCC V VIH1 MR Input High Voltage VIH2 WDI Input High Voltage VIL1 MR Input Low Voltage VIL2 WDI Input Low Voltage TA Operating Temperature PT0082(05/02) Test C on d it ion s V VCC > 4.0V 0.8 V VCC ≤ 4.0V 0.2VCC V 0.3VCC V -40 7 85 O C Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical Characteristics Table 4. DC Electrical Characteristics Sym ICC VRST VRTH VOH VOL VPFT Descr ip t ion Test C on d it ion s Operational Power Supply Current T7A75x1/75x2 VCC = 5V PT7A75x3/75x4 VCC = 3.3V PT7A75x5 VCC = 3.0V PT7A75x6/75x7 VCC = 2.5V Left WDI un-connected (No output load) Min Typ Ma x Un it 30 200 µΑ TA=25oC VRN-1.5% VRN VRN+1.5% PT7A75x1 4.560 4.630 4.699 PT7A75x2 4.314 4.380 4.446 PT7A75x3 3.034 3.080 3.126 PT7A75x4 2.886 2.930 2.974 PT7A75x5 2.590 2.630 2.669 PT7A75x6 2.285 2.320 2.355 PT7A75x7 2.167 2.200 2.233 Reset Threshold Voltage * Reset Threshold Hysteresis * Output HIGH Voltage Output LOW Voltage PFI Input Threshold IPFI PFI Input Current IWDI Average WDI Input Current** IMR MR Input Current V VCC varies between VRN – 5% 70 Vcc > 4.5V Isource=800µA VCC-1.5 Vcc > 2.7V Isource=500µA 0.8VCC Vcc >1.8V Isource=150µA 0.8VCC mV V Vcc > 4.5V Isink=3.2mA 0.4 Vcc > 2.7V Isink=1.2mA 0.3 Vcc > 1.2V Isink=100µA 0.3 V VPFI varies from1.0V to 1.5V (TA = 25oC) 1.23 1.25 1.27 V VPFI varies from1.0V to 1.5V 1.20 1.25 1.30 V 2.00 PFI connected to VCC PFI connected to GND µA -2.00 30 WDI connected to VCC WDI connected to GND -100 -30 MR = 0, VCC= 5V -600 -250 100 -100 µA µA * Valid for both RESET and RESET. VRN is nominal reset threshold voltage. ** WDI is internally serviced within the watchdog period if WDI is left unconnected. PT0082(05/02) 8 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics Table 5. AC Electrical Characteristics Sym Descr ip t ion Test C on d it ion s Min Typ Ma x Un it s tRS Reset Pulse Width MR from low to High 140 200 280 ms tWD Watchdog Timeout Period WDI and MR tied to VCC, VCC > VRN + 5% 1.0 1.6 2.25 s tMR MR Pulse Width tMD MR to RESET Delay tWP WDI Pulse Width 150 ns VCC = 5.0V 250 50 ns ns Figure 5. Watchdog Timing Diagram tWP tWD tWD tWD 5V WDI 0V 5V WDO 0V 5V Externally Triggered by MR RESET 0V tRS 5V RESET 0V Figure 6. Watchdog Timing Diagram VCC VRT VRT 5V tRS tRS 0V 5V RESET 0V MR 5V tMD 0V tMR 5V WDO 0V PT0082(05/02) 9 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Ordering Information P a r t N o. R e s e t Thr e s hold Pa ck a ge P a r t N o. R e s e t Thr e s hold Pa ck a ge PT7A7511P 4.63V PDIP- 8 PT7A7511W 4.63V SO IC- 8 (150mil) PT7A7521P 4.63V PDIP- 8 PT7A7521W 4.63V SO IC- 8 (150mil) PT7A7531P 4.63V PDIP- 8 PT7A7531W 4.63V SO IC- 8 (150mil) PT7A7512P 4.38V PDIP- 8 PT7A7512W 4.38V SO IC- 8 (150mil) PT7A7522P 4.38V PDIP- 8 PT7A7522W 4.38V SO IC- 8 (150mil) PT7A7532P 4.38V PDIP- 8 PT7A7532W 4.38V SO IC- 8 (150mil) PT7A7513P 3.08V PDIP- 8 PT7A7513W 3.08V SO IC- 8 (150mil) PT7A7523P 3.08V PDIP- 8 PT7A7523W 3.08V SO IC- 8 (150mil) PT7A7533P 3.08V PDIP- 8 PT7A7533W 3.08V SO IC- 8 (150mil) PT7A7514P 2.93V PDIP- 8 PT7A7514W 2.93V SO IC- 8 (150mil) PT7A7524P 2.93V PDIP- 8 PT7A7524W 2.93V SO IC- 8 (150mil) PT7A7534P 2.93V PDIP- 8 PT7A7534W 2.93V SO IC- 8 (150mil) PT7A7515P 2.63V PDIP- 8 PT7A7515W 2.63V SO IC- 8 (150mil) PT7A7525P 2.63V PDIP- 8 PT7A7525W 2.63V SO IC- 8 (150mil) PT7A7535P 2.63V PDIP- 8 PT7A7535W 2.63V SO IC- 8 (150mil) PT7A7516P 2.32 PDIP- 8 PT7A7516W 2.32 SO IC- 8 (150mil) PT7A7526P 2.32 PDIP- 8 PT7A7526W 2.32 SO IC- 8 (150mil) PT7A7536P 2.32 PDIP- 8 PT7A7536W 2.32 SO IC- 8 (150mil) PT7A7517P 2.20 PDIP- 8 PT7A7517W 2.20 SO IC- 8 (150mil) PT7A7527P 2.20 PDIP- 8 PT7A7527W 2.20 SO IC- 8 (150mil) PT7A7537P 2.20 PDIP- 8 PT7A7537W 2.20 SO IC- 8 (150mil) PT0082(05/02) 10 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information Figure 7. 8-Pin SOIC PT0082(05/02) 11 Ver:1 Data Sheet PT7A7511-7517/7521-7527/7531-7537 µP Supervisor Circuits |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes Pericom Technology Inc. Email: [email protected] Web-Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0082(05/02) 12 Ver:1