RENESAS R5F213MCQNNP

Datasheet
R8C/3MQ Group
RENESAS MCU
1.
R01DS0044EJ0100
Rev.1.00
Aug 11, 2011
Overview
1.1
Features
The R8C/3MQ Group single-chip MCU functions as a low-power-consumption transceiver which supports
2.4 GHz compliant to IEEE802.15.4 standard and incorporates the R8C CPU core, employing sophisticated
instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions
at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/3MQ Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 1 of 47
R8C/3MQ Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/3MQ Group.
Table 1.1
Item
CPU
Specifications for R8C/3MQ Group (1)
Function
Central processing
unit
Memory
ROM, RAM,
Data flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RE
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
62.5 ns (f(BCLK) = 16 MHz, VCC = 2.7 to 3.6 V)
125 ns (f(BCLK) = 8 MHz, VCC = 2.2 to 3.6 V)
250 ns (f(BCLK) = 4 MHz, VCC = 1.8 to 3.6 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/3MQ Group.
• Power-on reset
• Voltage detection 2 (detection level of voltage detection 1 selectable)
CMOS I/O ports: 18 (including XCIN and XCOUT), selectable pull-up resistor
(for some ports)
• 3 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, low-speed
on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• Interrupt Vectors: 69
• External: 11 sources (INT × 3, key input × 8)
• Priority levels: 7 levels
• 14 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 17
• Transfer modes: 2 (normal mode, repeat mode)
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait
one-shot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Page 2 of 47
R8C/3MQ Group
Table 1.2
1. Overview
Specifications for R8C/3MQ Group (2)
Item
Function
Serial Interface (UART0)
Specification
Shared with clock synchronous serial I/O mode and clock asynchronous serial
I/O
Synchronous Serial
Communication Unit (SSU)
1 (shared with I2C bus)
I2C bus
RF
1 (shared with SSU)
RF frequency
Reception
sensitivity
Transmission
output level
Baseband
Encryption
AES
Flash Memory
Operating Frequency/
Supply Voltage (in single mode)
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
2405 MHz to 2480 MHz
-95 dBm
0 dBm
• 127-byte transmit RAM, 127-byte receive RAM × 2
• Automatic ACK response function
• 26-bit timer: Compare function in 3 channels
AES Encryption/Decryption (Key length 128bits)
• Programming and erasure voltage: VCC = 1.8 to 3.6 V (in CPU rewrite mode)
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function
f(BCLK) = 16 MHz, VCC = 2.7 to 3.6 V)
f(BCLK) = 8 MHz (VCC = 2.2 to 3.6V)
f(BCLK) = 4 MHz, VCC = 1.8 to 3.6 V)
Note: f(XIN) = fixed at 16 MHz
Page 3 of 47
R8C/3MQ Group
Table 1.2
Item
1. Overview
Specifications for R8C/3MQ Group (2)
Function
Current Consumption (1)
Operating Ambient Temperature
Package
Specification
RF = Tx: 18 mA
RF = Rx (reception in progress): 25 mA
RF = Rx (reception standby): 24 mA
RF = Rx (reception standby)/wait mode: 23 mA
RF = idle: 4 mA
RF = off: 2.5 mA
*The above applies when:
f(XIN) = 16 MHz, f(BCLK)= 4 MHz, and VCC = VCCRF = 1.8 to 3.6 V
RF = Tx: 19 mA
RF = Rx (reception in progress): 26 mA
RF = Rx (reception standby): 25 mA
RF = Rx (reception standby)/wait mode: 23 mA
RF = idle: 5 mA
RF = off: 3.5 mA
*The above applies when:
f(XIN) = 16 MHz, f(BLCK) = 8 MHz, and VCC = VCCRF = 2.2 to 3.6 V
RF = Tx: 21.5 mA
RF = Rx (reception in progress): 28.5 mA
RF = Rx (reception standby): 27.5 mA
RF = Rx (reception standby)/wait mode: 23 mA
RF = idle: 7.5 mA
RF = off: 6 mA
*The above applies when:
f(XIN) = 16 MHz, f(BLCK) = 16 MHz, and VCC = VCCRF = 2.7 to 3.6 V
Low-speed on-chip oscillator mode (f(BCLK) = 15.6 kHz): 80 µA
Low-speed clock mode (f(BCLK) = 32 kHz, flash memory low-powerconsumption mode): 95 µA
Low-speed clock mode (f(BCLK) = 32 kHz, flash memory off/program operation
on RAM: 45 µA
Wait mode (system clock = XCIN (32 kHz)), peripheral function clock on: 6 µA
Wait mode (system clock = XCIN (32 kHz)), peripheral function clock off: 4.5 µA
Wait mode (system clock = fOCO-S (125 kHz)), peripheral function clock on:
13 µA
Wait mode (system clock = fOCO-S (125 kHz)), peripheral function clock off:
7.5 µA
Stop mode (all clocks off): 2 µA
*When VCC = VCCRF = 1.8 to 3.6 V and RF = off
−20°C to 85°C (N version)
40-pin HWQFN
Package code: PWQN0040KB-A (previous code: 40PJS-A)
Note:
1. Refer to 5. Electrical Characteristics for details on the measurement conditions.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 4 of 47
R8C/3MQ Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/3MQ Group. Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/3MQ Group.
Table 1.3
Product List for R8C/3MQ Group
Part No.
R5F213M6QNNP
R5F213M7QNNP
R5F213M8QNNP
R5F213MAQNNP
R5F213MCQNNP
Current of Aug 2011
ROM Capacity
Program ROM
Data flash
32 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
RAM
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
7 Kbytes
7.5 Kbytes
Package Type
Remarks
PWQN0040KB-A N version
Part No. R 5 F 21 3M 8 Q N NP
Package type:
NP: PWQN0040KB-A (0.5-mm pin-pitch, 6-mm square body)
Classification
N: Operating ambient temperature -20°C to 85°C
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/3MQ Group
R8C/3x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/3MQ Group
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 5 of 47
R8C/3MQ Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
1
8
6
Port P0
Port P1
Port P3
3
Port P4
Peripheral functions
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
UART or
clock synchronous serial I/O
(8 bits × 1)
System clock generation
circuit
XIN-XOUT
XCIN-XCOUT
Low-speed on-chip oscillator
I2C bus or SSU
(8 bits × 1)
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
DTC
Voltage detection circuit
Memory
R8C CPU core
RF baseband
R0H
R1H
R0L
R1L
R2
R3
SB
ISP
INTB
A0
A1
FB
ROM (1)
USP
RAM (2)
PC
FLG
Multiplier
Notes:
1. ROM size varies with the product type.
2. RAM size varies with the product type.
Figure 1.2
Block Diagram
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 6 of 47
R8C/3MQ Group
1.4
1. Overview
Pin Assignment
VCCRF[REGIN]
VREG1[IFVDD]
RFION
RFIOP
21
VSSRF1
30 29 28 27 26 25 24 23 22
VSSRF2
VREGOUT1
VREG2[LNA/MIX/PAVDD]
VSSRF[REGGND]
VREG3[PLLAVDD]
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines Pin Name Information by Pin Number.
VREGOUT2[VCO]
31
20
IFRXTN
VREG4[PLLDVDD]
32
19
IFRXTP
P0_4/TREO(/TRCIOB)/ASW
33
18
P1_0/KI0(/TRCIOD)
P3_7/SDA/SSO/TRAO
34
17
P1_1/KI1(/TRCIOA/TRCTRG)
P3_5/SCL/SSCK(/TRCIOD)
P3_4/SSI(/TRCIOC)
35
16
15
P1_2/KI2(/TRCIOB)
P1_3/KI3/TRBO (/TRCIOC)
P3_3/INT3/SCS(/TRCCLK)
37
P1_4/KI4(/TXD0/TRCCLK)
P3_1(/TRBO)
PWQN0040KB-A(40PJS-A)
(Top view)
14
38
13
P1_5/KI5(/INT1/RXD0/TRAIO)
P3_0(/TRAO)
39
Bottom side: DIEGND
12
P1_6/KI6(/CLK0)
P4_5/INT0
40
11
P1_7/KI7/INT1(/TRAIO)
R8C/3MQ Group
4
5
6
7
8
9
10
RESET
VSS1
MODE
VCC
P4_3(/XCIN)
P4_4(/XCOUT)
VSS2[OSCGND]
3
XIN
2
XOUT
1
VREGOUT3[OSC]
36
Notes:
1. The function in parentheses can be assigned to the pin by a program.
2. [ ] indicates the internal function name related to the pin.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
4. Connect the metal pad (DIEGND) of the package’s bottom side to the board’s GND side.
Figure 1.3
Pin Assignment (Top View)
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 7 of 47
R8C/3MQ Group
Table 1.4
1. Overview
Pin Name Information by Pin Number
Pin
Number
Control Pin
1
2
3
4
VREGOUT3
VSS2
XIN
XOUT
5
RESET
VSS1
MODE
VCC
(XCIN)
(XCOUT)
6
7
8
9
10
Port
Interrupt
I/O Pin Functions for Peripheral Modules
Serial
Timer
SSU I2C bus
Interface
P4_3
P4_4
(TRAIO)
11
P1_7
KI7/INT1
12
P1_6
KI6
13
P1_5
KI5(/INT1)
(TRAIO)
(RXD0)
14
P1_4
KI4
(TRCCLK)
(TXD0)
15
P1_3
KI3
TRBO(/TRCIOC)
16
P1_2
KI2
(TRCIOB)
17
P1_1
KI1
(TRCIOA/TRCTRG)
18
P1_0
KI0
(TRCIOD)
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
(CLK0)
IFRXTP
IFRXTN
VCCRF
VREGOUT1
VREG1
VREG2
VSSRF
RFIOP
RFION
VSSRF1
VSSRF2
VREG3
VREGOUT2
VREG4
P0_4
P3_7
P3_5
P3_4
37
P3_3
38
39
P3_1
P3_0
40
P4_5
Bottom
side
RF Pin
Other
INT3
TREO(/TRCIOB)
TRAO
(TRCIOD)
(TRCIOC)
SSO
SSCK
SSI
ASW
(TRCCLK)
SCS
SDA
SCL
(TRBO)
(TRAO)
INT0
DIEGND
Note:
1. The function in parentheses can be assigned to the pin by a program.
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Aug 11, 2011
Page 8 of 47
R8C/3MQ Group
1.5
1. Overview
Pin Functions
Tables 1.5 and 1.6 list Pin Functions.
Table 1.5
Pin Functions (1)
Item
Power supply input
Pin Name
VCC, VSS1
Reset input
MODE
XIN clock input
XIN clock output
XCIN clock input
XCIN clock output
RESET
MODE
XIN
XOUT
XCIN
XCOUT
INT interrupt input
INT0, INT1, INT3
I
Key input interrupt
input
Timer RA
KI0 to KI7
I
Timer RB
Timer RC
Timer RE
Serial interface
SSU
I2C bus
I/O ports
I: Input
I
I
I/O
I
O
TRAIO
TRAO
TRBO
TRCCLK
TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
TREO
CLK0
RXD0
TXD0
SSI
SCS
SSCK
SSO
SCL
SDA
P0_4, P1_0 to P1_7,
P3_0, P3_1,
P3_3 to P3_5, P3_7,
P4_3 to P4_5
O: Output
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
I/O Type
Description
—
Apply 1.8 to 3.6 V to the VCC pin.
Apply 0 V to the VSS1 pin.
I
Input “L” on this pin resets the MCU.
Connect this pin to VCC via a resistor.
These pins are provided for XIN clock oscillation circuit I/O.
Connect a crystal oscillator between the XIN and XOUT pins.
These pins are provided for XCIN clock oscillation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins.
INT interrupt input pins.
INT0 is used as an input pin for timer RB and timer RC.
Key input interrupt input pins.
I/O
O
O
I
I
I/O
Timer RA I/O pin.
Timer RA output pin.
Timer RB output pin.
External clock input pin.
External trigger input pin.
Timer RC I/O pins.
O
I/O
I
O
I/O
I/O
Divided clock output pin.
Transfer clock I/O pin.
Serial data input pin.
Serial data output pin.
Data I/O pin.
Chip-select signal I/O pin.
I/O
I/O
I/O
I/O
I/O
Clock I/O pin.
Data I/O pin.
Clock I/O pin
Data I/O pin
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
I/O: Input and output
Page 9 of 47
R8C/3MQ Group
1. Overview
Table 1.6
Pin Functions (2)
Item
Analog power
supply input
Pin Name
VCCRF, VSSRF,
VSSRF1, VSSRF2,
VSS2, DIEGND
VREG1
VREG2
VREG3
VREG4
Regulator output
I/O Type
—
—
—
—
—
VREGOUT1
—
VREGOUT2
—
VREGOUT3
—
RF I/O
Test pins
External antenna
switch control
output
I: Input
RFIOP, RFION
IFRXTN, IFRXTP
ASW
O: Output
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
I/O
I/O
O
Description
Apply the same voltage as the VCC of 1.8 V to 3.6 V to
VCCRF. Apply 0 V to VSSRF, VSSRF1, VSSRF2, VSS2,
and DIEGND.
1.5 V IF VDD pin. Connect to the VREGOUT1 pin.
1.5 V LNA/MIX/PA VDD pin. Connect to the VREGOUT1 pin.
1.5 V PLL ANALOG VDD pin. Connect to the VREGOUT1
pin.
1.5 V PLL DIGITAL VDD pin. Connect to the VREGOUT1
pin.
On-chip regulator output (1.5 V) pin for the analog circuit.
Connect only a bypass capacitor between pins VREGOUT1
and VSS.
Use only as the power supply for pins VREG1, VREG2,
VREG3, and VREGF4.
Regulator output (1.5 V) pin for the VCO circuit.
Connect only a bypass capacitor between pins VREGOUT2
and VSS.
Do not use as the power supply for other circuits.
Regulator output (1.5 V) pin for the XIN oscillation circuit.
Connect only a bypass capacitor between pins VREGOUT3
and VSS.
Do not use as the power supply for other circuits.
RF I/O pins
Ports for testing. Leave open or apply 0 V.
Signal output pin to control the external antenna switch.
If antenna switch control is not required, leave open.
I/O: Input and output
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R8C/3MQ Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
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Aug 11, 2011
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R8C/3MQ Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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R8C/3MQ Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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Aug 11, 2011
Page 13 of 47
R8C/3MQ Group
3.
3. Memory
Memory
3.1
R8C/3MQ Group
Figure 3.1 is a Memory Map of R8C/3MQ Group. The R8C/3MQ Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with
address 0FFFFh. However, for products with internal ROM (program ROM) capacity of 64 Kbytes or more, the
internal ROM is also allocated higher addresses, beginning with address 0FFFFh.
For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh, and a 96-Kbyte internal
ROM is allocated addresses 04000h to 1BFFFh.
The fixed interrupt vector table is allocated addresses 08000h to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
SFR
(Refer to 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0FFD8h
0XXXXh
Reserved area
02C00h
02FFFh
03000h
SFR
(Refer to 4. Special Function
Registers (SFRs))
0FFDCh
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
R5F213M6QNNP
32 Kbytes
08000h
–
2.5 Kbytes
00DFFh
R5F213M7QNNP
48 Kbytes
04000h
–
4 Kbytes
013FFh
R5F213M8QNNP
64 Kbytes
04000h
13FFFh
6 Kbytes
01BFFh
R5F213MAQNNP
96 Kbytes
04000h
1BFFFh
7 Kbytes
01FFFh
R5F213MCQNNP
128 Kbytes
04000h
23FFFh
7.5 Kbytes
021FFh
Figure 3.1
Memory Map of R8C/3MQ Group
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 14 of 47
R8C/3MQ Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.11 list the special
function registers. Table 4.12 lists the ID Code Areas and Option Function Select Area.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
SFR Information (1) (0000h to 002Fh) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00101000b
00h
00h
00h
0XXXXXXXb (2)
00000100b
XXh
XXh
00111111b
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
Clock Prescaler Reset Flag
CPSRF
00h
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer
reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 15 of 47
R8C/3MQ Group
Table 4.2
Address
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
4. Special Function Registers (SFRs)
SFR Information (2) (0030h to 006Fh) (1)
Register
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
CMPA
VCAC
Symbol
00h
00h
After Reset
Voltage detection Register 2
VCA2
00h (3)
00100000b (4)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
Voltage Monitor 1 Circuit Control Register
WDT Detection Flag
VW1C
VW2C
1100X010b (3)
1100X011b (4)
10001010b
10000010b
Flash Memory Ready Interrupt Control Register
BB Timer Compare 2 Interrupt Control Register
FMRDYIC
BBTIM2IC
XXXXX000b
XXXXX000b
Timer RC Interrupt Control Register
TRCIC
XXXXX000b
Timer RE Interrupt Control Register
TREIC
XXXXX000b
Key Input Interrupt Control Register
KUPIC
XXXXX000b
SSU Interrupt Control Register/IIC bus Interrupt Control Register (2)
SSUIC/IICIC
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
S0TIC
S0RIC
XXXXX000b
XXXXX000b
Bank 0 Reception Complete/IDLE Interrupt Control Register (5)
BBRX0IC/BBIDELIC
XXXXX000b
Timer RA Interrupt Control Register
TRAIC
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
BB Timer Compare 1 Interrupt Control Register
INT0 Interrupt Control Register
CCA Complete Interrupt Control Register
BB Timer Compare 0 Interrupt Control Register
BBTIM1IC
INT0IC
BBCCAIC
BBTIM0IC
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
Address Filter Interrupt Control Register
Transmit Overrun Interrupt Control Register
Transmission Complete Interrupt Control Register
Receive Overrun 1 Interrupt Control Register
BBADFIC
BBTXORIC
BBTXIC
BBRXOR1IC
XXXXX000b
XXXXX000b
XX00XX00b
XXXXX000b
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
3. The LVDAS bit in the OFS register is set to 1.
4. The LVDAS bit in the OFS register is set to 0.
5. Can be selected by the BANK0INTSEL bit in the BBTXRXMODE4 register.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 16 of 47
R8C/3MQ Group
4. Special Function Registers (SFRs)
Table 4.3
SFR Information (3) (0070h to 00AFh) (1)
Address
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
Register
PLL Lock Detection Interrupt Control Register
Receive Overrun 0/Calibration Complete Interrupt Control Register (3)
Voltage Monitor 1 Interrupt Control Register
Bank 1 Reception Complete/Clock Regulator Interrupt Control Register (2)
Symbol
BBPLLIC
BBRXOR0IC/BBCALIC
VCMP1IC
BBRX1IC/BBCREGIC
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
DTC Activation Control Register
DTCTL
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTCEN0
DTCEN1
DTCEN2
DTCEN3
00h
00h
00h
00h
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN5
DTCEN6
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Can be selected by the BANK1INTSEL bit in the BBTXRXMODE4 register.
3. Can be selected by the ROR0INTSEL bit in the BBTXRXMODE4 register.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 17 of 47
R8C/3MQ Group
Table 4.4
Address
00B0h
:
00DFh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
4. Special Function Registers (SFRs)
SFR Information (4) (00B0h to 011Fh) (1)
Register
Symbol
After Reset
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
P0
P1
PD0
PD1
XXh
XXh
00h
00h
Port P3 Register
P3
XXh
Port P3 Direction Register
Port P4 Register
PD3
P4
00h
XXh
Port P4 Direction Register
PD4
00h
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
00h
00h
00h
FFh
FFh
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 18 of 47
R8C/3MQ Group
Table 4.5
Address
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
:
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
4. Special Function Registers (SFRs)
SFR Information (5) (0120h to 019Fh) (1)
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
Register
Symbol
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
TRCCR2
TRCDF
TRCOER
After Reset
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
Timer RA Pin Select Register
Timer RB/RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
00h
00h
00h
00h
UART0 Pin Select Register
U0SR
00h
SSU/IIC Pin Select Register
SSUIICSR
00h
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
INTSR
PINSR
00h
00h
SS Bit Counter Register
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
SS Transmit Data Register H (2)
SS Receive Data Register L / IIC bus Receive Data Register (2)
SS Receive Data Register H (2)
SS Control Register H / IIC bus Control Register 1 (2)
SS Control Register L / IIC bus Control Register 2 (2)
SS Mode Register / IIC bus Mode Register (2)
SS Enable Register / IIC bus Interrupt Enable Register (2)
SS Status Register / IIC bus Status Register (2)
SS Mode Register 2 / Slave Address Register (2)
SSBR
SSTDR / ICDRT
SSTDRH
SSRDR / ICDRR
SSRDRH
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 19 of 47
R8C/3MQ Group
Table 4.6
Address
01A0h
:
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
:
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
:
02FFh
4. Special Function Registers (SFRs)
SFR Information (6) (01A0h to 02FFh) (1)
Register
Symbol
After Reset
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
00h
00h
Address Match Interrupt Register 0
RMAD0
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
Address Match Interrupt Enable Register 1
AIER1
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
00h
00h
Port P1 Drive Capacity Control Register
P1DRR
00h
Drive Capacity Control Register 0
Drive Capacity Control Register 1
DRR0
DRR1
00h
00h
Input Threshold Control Register 0
Input Threshold Control Register 1
VLT0
VLT1
00h
00h
External Input Enable Register 0
INTEN
00h
INT Input Filter Select Register 0
INTF
00h
Key Input Enable Register 0
Key Input Enable Register 1
KIEN
KI1EN
00h
00h
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 20 of 47
R8C/3MQ Group
Table 4.7
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
4. Special Function Registers (SFRs)
SFR Information (7) (2C00h to 2C6Fh) (1)
Register
Symbol
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Control Data 0
DTCD0
DTC Control Data 1
DTCD1
DTC Control Data 2
DTCD2
DTC Control Data 3
DTCD3
DTC Control Data 4
DTCD4
DTC Control Data 5
DTCD5
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 21 of 47
R8C/3MQ Group
Table 4.8
Address
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
4. Special Function Registers (SFRs)
SFR Information (8) (2C70h to 2CAFh) (1)
Register
Symbol
DTC Control Data 6
DTCD6
DTC Control Data 7
DTCD7
DTC Control Data 8
DTCD8
DTC Control Data 9
DTCD9
DTC Control Data 10
DTCD10
DTC Control Data 11
DTCD11
DTC Control Data 12
DTCD12
DTC Control Data 13
DTCD13
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 22 of 47
R8C/3MQ Group
Table 4.9
Address
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
4. Special Function Registers (SFRs)
SFR Information (9) (2CB0h to 2CEFh) (1)
Register
Symbol
DTC Control Data 14
DTCD14
DTC Control Data 15
DTCD15
DTC Control Data 16
DTCD16
DTC Control Data 17
DTCD17
DTC Control Data 18
DTCD18
DTC Control Data 19
DTCD19
DTC Control Data 20
DTCD20
DTC Control Data 21
DTCD21
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 23 of 47
R8C/3MQ Group
Table 4.10
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
2D02h
2D03h
2D04h
2D05h
2D06h
2D07h
2D08h
2D09h
2D0Ah
2D0Bh
2D0Ch
2D0Dh
2D0Eh
2D0Fh
2D10h
2D11h
2D12h
2D13h
2D14h
2D15h
2D16h
2D17h
2D18h
2D19h
2D1Ah
2D1Bh
2D1Ch
2D1Dh
2D1Eh
2D1Fh
2D20h
2D21h
2D22h
2D23h
2D24h
2D25h
2D26h
2D27h
2D28h
2D29h
2D2Ah
2D2Bh
2D2Ch
2D2Dh
2D2Eh
2D2Fh
4. Special Function Registers (SFRs)
SFR Information (10) (2CF0h to 2D2Fh) (1)
Register
Symbol
DTC Control Data 22
DTCD22
DTC Control Data 23
DTCD23
Baseband Control Register
Transmit/Receive Reset Register
Transmit/Receive Mode Register 0
Transmit/Receive Mode Register 1
Receive Frame Length Register
Receive Data Counter Register
RSSI/CCA Result Register
Transmit/Receive Status Register 0
Transmit Frame Length Register
Transmit/Receive Mode Register 2
Transmit/Receive Mode Register 3
Receive Level Threshold Set Register
Transmit/Receive Control Register
CSMA Control Register 0
CCA Level Threshold Set Register
Transmit/Receive Status Register 1
RF Control Register
Transmit/Receive Mode Register 4
CSMA Control Register 1
CSMA Control Register 2
PAN Identifier Register
BBCON
BBTXRXRST
BBTXRXMODE0
BBTXRXMODE1
BBRXFLEN
BBRXCOUNT
BBRSSICCARSLT
BBTXRXST0
BBTXFLEN
BBTXRXMODE2
BBTXRXMODE3
BBLVLVTH
BBTXRXCON
BBCSMACON0
BBCCAVTH
BBTXRXST1
BBRFCON
BBTXRXMODE4
BBCSMACON1
BBCSMACON2
BBPANID
Short Address Register
BBSHORTAD
Extended Address Register
BBEXTENDAD0
BBEXTENDAD1
BBEXTENDAD2
BBEXTENDAD3
Timer Read-Out Register 0
BBTIMEREAD0
Timer Read-Out Register 1
BBTIMEREAD1
Timer Compare 0 Register 0
BBCOMP0REG0
Timer Compare 0 Register 1
BBCOMP0REG1
Timer Compare 1 Register 0
BBCOMP1REG0
Timer Compare 1 Register 1
BBCOMP1REG1
Timer Compare 2 Register 0
BBCOMP2REG0
Timer Compare 2 Register 1
BBCOMP2REG1
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
80h
00h
30h
00h
80h
00h
00h
80h
00h
00h
00h
9Ch
05h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 24 of 47
R8C/3MQ Group
Table 4.11
Address
2D30h
2D31h
2D32h
2D33h
2D34h
2D35h
2D36h
2D37h
2D38h
2D39h
2D3Ah
2D3Bh
2D3Ch
2D3Dh
2D3Eh
2D3Fh
2D40h
:
2D45h
2D46h
2D47h
:
2D63h
2D64h
2D65h
2D66h
2D67h
2D68h
2D69h
2D6Ah
2D6Bh
2D6Ch
2D6Dh
2D6Eh
2D6Fh
2D70h
2D71h
2D72h
2D73h
2D74h
2D75h
2D76h
2D77h
2D78h
2D79h
2D7Ah
2D7Bh
2D7Ch
2D7Dh
2D7Eh
2D7Fh
2D80h
2D81h
2D82h
2D83h
:
2DFFh
2E00h
:
2E7Eh
2E7Fh
2D80h
:
2EFEh
2EFFh
2F00h
:
2FFFh
4. Special Function Registers (SFRs)
SFR Information (11) (2D30h to 2FFFh) (1)
Time Stamp Register 0
Register
Symbol
BBTSTAMP0
Time Stamp Register 1
BBTSTAMP1
Timer Control Register
Backoff Period Register
BBTIMECON
BBBOFFPROD
00h
00h
00h
00h
00h
00h
PLL Division Register 0
PLL Division Register 1
Transmit Output Power Register
RSSI Offset Register
BBPLLDIVL
BBPLLDIVH
BBTXOUTPWR
BBRSSIOFS
65h
09h
00h
F6h
Automatic ACK Response Timing Adjustment Register
BBACKRTNTIMG
22h
Verification Mode Set Register
BBEVAREG
00h
IDLE Wait Set Register
BBIDELWAIT
01h
ANTSW Output Timing Set Register
BBANTSWTIMG
72h
RF Initial Set Register
BBRFINI
XXh
XXh
ANTSW Control Register
BBANTSWCON
00h
Transmit RAM
Transmit RAM
Transmit RAM
TRANSMIT_RAM_START
Receive RAM
Receive RAM
Receive RAM
After Reset
TRANSMIT_RAM_END
RECIEVE_RAM_START
RECIEVE_RAM_END
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 25 of 47
R8C/3MQ Group
Table 4.12
Address
:
FFDBh
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
4. Special Function Registers (SFRs)
ID Code Areas and Option Function Select Area
Area Name
Option Function Select Register 2
Symbol
OFS2
After Reset
(Note 1)
ID1
(Note 2)
ID2
(Note 2)
ID3
(Note 2)
ID4
(Note 2)
ID5
(Note 2)
ID6
(Note 2)
ID7
(Note 2)
Option Function Select Register
OFS
(Note 1)
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
At shipment, the option function select area is set to FFh. It is set to the written value after written by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
At shipment, the ID code areas are set to FFh. They are set to the written value after written by the user.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 26 of 47
R8C/3MQ Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Rated Value
Unit
VCC
Symbol
Digital supply voltage
−0.3 to 3.8
V
VCCRF
Analog supply voltage
−0.3 to 3.8
V
VI
Input voltage
RESET, MODE, P0_4, P1,
P3_0, P3_1, P3_3 to P3_5,
P3_7, P4_3 to P4_5
−0.3 to VCC + 0.3
V
VO
Output voltage
P0_4, P1, P3_0, P3_1, P3_3
to P3_5, P3_7, P4_3 to P4_5
−0.3 to VCC + 0.3
V
VRFIO
RF I/O pins
RFIOP, RFION
−0.3 to 2.1
V
VTESTIO
Test ports
IFRXTP, IFRXTN
−0.3 to 2.1
V
VANAIN
1.5 V analog supply
(input)
VREG1, VREG2, VREG3,
VREG4
−0.3 to 2.1
V
VANAOUT
1.5 V analog supply
(output)
VREGOUT1, VREGOUT2,
VREGOUT3
−0.3 to 2.1
V
VXINOUT
Main clock I/O
XIN, XOUT
Pd
Power dissipation
Topr
Operating ambient
temperature
Tstg
Parameter
Storage temperature
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Condition
−0.3 to 2.1
V
300
mW
(1) During MCU operation
under the conditions other
than (2) and (3) below.
−20 to 85
°C
(2) During programming and
erasing of the flash
memory using a serial
programmer or parallel
programmer.
0 to 60
(3) During on-chip debugging
with the E8a emulator
connected
10 to 35
−20°C ≤ Topr ≤ 85°C
−65 to 150
°C
Page 27 of 47
R8C/3MQ Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions (1)
Symbol
VCC
Parameter
Digital supply
voltage
Conditions
Standard
Min.
Typ.
Max.
(1) During MCU operation under the
conditions other than (2) and (3)
below.
1.8
3.3
3.6
(2) During programming and erasing of
the flash memory using a serial
programmer or parallel programmer.
2.7
—
3.6
(3) During on-chip debugging with the
E8a emulator connected
2.7
—
3.6
Unit
V
VCCRF
Analog supply voltage
1.8
3.3
3.6
V
VSS/
VSS2/
VSSRF/
VSSRF1/
VSSRF2/
DIEGND
Supply voltage
—
0
—
V
VIH
Input “H” voltage Other than CMOS input
VSS1, VSS2, VSSRF, VSSRF1,
VSSRF2, DIEGND
CMOS Input level
input
switching
function
(I/O port)
VIL
0.8 VCC
—
VCC
V
Input level selection: 2.7 V ≤ VCC ≤ 3.6 V 0.55 VCC
0.35 VCC
1.8 V ≤ VCC < 2.7 V 0.65 VCC
—
VCC
V
—
VCC
V
Input level selection: 2.7 V ≤ VCC ≤ 3.6 V
0.5 VCC
1.8 V ≤ VCC < 2.7 V
0.7 VCC
—
VCC
V
0.8 VCC
—
VCC
V
Input level selection: 2.7 V ≤ VCC ≤ 3.6 V 0.85 VCC
0.7 VCC
1.8 V ≤ VCC < 2.7 V 0.85 VCC
—
VCC
V
—
VCC
V
0
—
0.2 VCC
V
Input level selection: 2.7 V ≤ VCC ≤ 3.6 V
0.35 VCC
1.8 V ≤ VCC < 2.7 V
0
—
0.2 VCC
V
0
—
0.2 VCC
V
Input level selection: 2.7 V ≤ VCC ≤ 3.6 V
0.5 VCC
1.8 V ≤ VCC < 2.7 V
0
—
0.3 VCC
V
0
—
0.2 VCC
V
Input level selection: 2.7 V ≤ VCC ≤ 3.6 V
0.7 VCC
1.8 V ≤ VCC < 2.7 V
0
—
0.45 VCC
V
0
—
0.35 VCC
V
Input “L” voltage Other than CMOS input
CMOS Input level
input
switching
function
(I/O port)
IOH(sum)
Peak sum output “H”
current
Sum of all pins IOH(peak)
—
—
−160
mA
IOH(sum)
Average sum output “H”
current
Sum of all pins IOH(avg)
—
—
−80
mA
IOH(peak)
Peak output “H” current
Drive capacity Low
—
—
−10
mA
Drive capacity High
—
—
−40
mA
—
—
−5
mA
IOH(avg)
Average output “H”
current
Drive capacity Low
Drive capacity High
—
—
−20
mA
IOL(sum)
Peak sum output “L”
current
Sum of all pins IOL(peak)
—
—
160
mA
IOL(sum)
Average sum output “L”
current
Sum of all pins IOL(avg)
—
—
80
mA
IOL(peak)
Peak output “L” current
Drive capacity Low
—
—
10
mA
Drive capacity High
—
—
40
mA
Drive capacity Low
—
—
5
mA
IOL(avg)
Average output “L”
current
f(XIN)
XIN clock input oscillation frequency
Drive capacity High
—
—
20
mA
1.8 V ≤ VCC ≤ 3.6 V
—
16
—
MHz
f(XCIN)
XCIN clock input oscillation frequency
1.8 V ≤ VCC ≤ 3.6 V
30
32.768
35
kHz
—
System clock frequency
f(XIN)=16 MHz
1.8 V ≤ VCC ≤ 3.6 V
—
—
16
MHz
f(BCLK)
CPU clock frequency
f(XIN)=16 MHz
2.7 V ≤ VCC ≤ 3.6 V
—
—
16
MHz
2.2 V ≤ VCC < 2.7 V
—
—
8
1.8 V ≤ VCC < 2.2 V
—
—
4
Notes:
1. VCC = 1.8 to 3.6 V and Topr = −20°C to 85°C, unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 28 of 47
R8C/3MQ Group
5. Electrical Characteristics
P0
P1
P3
P4
Figure 5.1
30 pF
Ports P0, P1, P3 and P4 Timing Measurement Circuit
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 29 of 47
R8C/3MQ Group
Table 5.3
Symbol
—
—
—
td(SR-SUS)
—
—
5. Electrical Characteristics
Flash Memory (Program ROM) Electrical Characteristics
Parameter
Conditions
Program/erase endurance (2)
Byte program time
Block erase time
Time delay from suspend request until
suspend
Interval from erase start/restart until
following suspend request
Time from suspend until erase restart
1,000 (3)
—
—
—
td(CMDRST- Time from when command is forcibly
READY)
stopped until reading is enabled
—
Program, erase voltage
—
—
—
Read voltage
Program, erase temperature
Data hold time (7)
Min.
CPU rewrite mode
Standard serial I/O mode
Parallel I/O mode
Ambient temperature = 55°C
Standard
Typ.
—
80
0.3
—
0
—
—
—
—
—
1.8
2.7
2.7
1.8
0
20
—
—
—
—
—
—
Max.
—
500
—
5 + CPU clock
× 3 cycles
—
30 + CPU clock
× 1 cycle
30 + CPU clock
× 1 cycle
3.6
3.6
3.6
3.6
60
—
Unit
times
µs
s
ms
µs
µs
µs
V
V
°C
year
Notes:
1. VCC = 2.7 to 3.6 V and Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 30 of 47
R8C/3MQ Group
Table 5.4
Symbol
—
—
—
—
—
td(SR-SUS)
—
—
5. Electrical Characteristics
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Parameter
Conditions
Program/erase endurance (2)
Byte program time
(program/erase endurance ≤ 1,000 times)
Byte program time
(program/erase endurance > 1,000 times)
Block erase time
(program/erase endurance ≤ 1,000 times)
Block erase time
(program/erase endurance > 1,000 times)
Time delay from suspend request until
suspend
Interval from erase start/restart until
following suspend request
Time from suspend until erase restart
Program, erase voltage
—
—
Read voltage
Program, erase temperature
—
Data hold time (7)
Max.
—
times
160
1500
µs
—
300
1500
µs
—
0.2
1
s
—
0.3
1
s
—
—
ms
0
—
5 + CPU clock
× 3 cycles
—
—
—
µs
—
—
1.8
2.7
2.7
1.8
−20
0
0
20
—
—
—
—
—
—
—
—
30 + CPU clock
× 1 cycle
30 + CPU clock
× 1 cycle
3.6
3.6
3.6
3.6
85
60
60
—
10,000 (3)
—
td(CMDRST- Time from when command is forcibly
READY)
stopped until reading is enabled
—
Standard
Typ.
—
Min.
CPU rewrite mode
Standard serial I/O mode
Parallel I/O mode
CPU rewrite mode
Standard serial I/O mode
Parallel I/O mode
Ambient temperature = 55°C
Unit
µs
µs
V
V
°C
year
Notes:
1. VCC = 1.8 to 3.6 V and Topr = −20°C to 85°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 31 of 47
R8C/3MQ Group
5. Electrical Characteristics
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Fixed time
Clock-dependent
time
Access restart
td(SR-SUS)
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Table 5.5
Time delay until Suspend
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet0
—
Voltage detection level Vdet0_0
—
td(E-A)
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (2)
Voltage detection 0 circuit response time (3)
At the falling of VCC from
3.6 V to (Vdet0_0 − 0.1) V
VCA25 = 1, VCC = 3.0 V
Min.
1.80
—
Standard
Typ.
1.90
6
Max.
2.05
150
—
—
1.5
—
—
100
Unit
V
µs
µA
µs
Notes:
1. The measurement condition is VCC = 1.8 V to 3.6 V and Topr = −20°C to 85°C.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.6
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Vdet1
Parameter
Condition
Standard
Typ.
2.50
Max.
2.70
Unit
Voltage detection level Vdet1_2 (2)
At the falling of VCC
Min.
2.30
(2)
2.75
2.95
3.15
V
—
0.07
—
V
—
60
150
µs
—
—
1.7
—
—
100
µA
Voltage detection level Vdet1_5
Hysteresis width at the rising of VCC in voltage
detection 1 circuit
At the falling of VCC
—
—
Voltage detection 1 circuit response time (3)
—
td(E-A)
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts (4)
At the falling of VCC from
3.6 V to (Vdet1_0 − 0.1) V
VCA26 = 1, VCC = 3.0 V
V
µs
Notes:
1. The measurement condition is VCC = 1.8 V to 3.6 V and Topr = −20°C to 85°C.
2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 32 of 47
R8C/3MQ Group
5. Electrical Characteristics
Power-on Reset Circuit (2)
Table 5.7
Symbol
Parameter
Condition
External power VCC rise gradient
trth
(1)
Min.
0
Standard
Typ.
Max.
—
50,000
Unit
mV/msec
Notes:
1. The measurement condition is Topr = −20°C to 85°C, unless otherwise specified.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
tw(por) (2)
Voltage detection 0
circuit response time
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of User’s Manual: Hardware for details.
2. tw(por) indicates the duration the external power V CC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 33 of 47
R8C/3MQ Group
Table 5.8
5. Electrical Characteristics
System Clock Low-Speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
fOCO-S
—
Parameter
Condition
Min.
100
—
Low-speed on-chip oscillator frequency
Oscillation stability time
Standard
Typ.
125
30
Max.
150
100
Unit
kHz
µs
Note:
1. VCC = 1.8 V to 3.6 V and Topr = −20°C to 85°C, unless otherwise specified.
Table 5.9
Watchdog Timer Low-Speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
fOCO-WDT Low-speed on-chip oscillator frequency
—
Oscillation stability time
Min.
Standard
Typ.
Max.
60
—
125
30
250
100
Unit
kHz
µs
Note:
1. VCC = 1.8 V to 3.6 V and Topr = −20°C to 85°C, unless otherwise specified.
Table 5.10
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
Parameter
Condition
Min.
—
Time for internal power supply stabilization during
power-on (2)
Standard
Typ.
Max.
—
2,000
Unit
µs
Notes:
1. The measurement condition is VCC = 1.8 to 3.6 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
Table 5.11
Symbol
Timing Requirements of Synchronous Serial Communication Unit (SSU) (1)
tSUCYC
SSCK clock cycle time
tHI
tLO
tRISE
SSCK clock “H” width
SSCK clock “L” width
SSCK clock rising
time
tFALL
SSCK clock falling
time
tSU
tH
Min.
4
Standard
Typ.
—
Max.
—
Master
0.4
0.4
—
—
—
—
0.6
0.6
1
Slave
Master
—
—
—
—
1
1
—
100
1
—
—
—
1
—
—
1tCYC + 50
—
—
Parameter
Conditions
Slave
SSO, SSI data input setup time
SSO, SSI data input hold time
Slave
tLEAD
SCS setup time
tLAG
tOD
Slave
SCS hold time
SSO, SSI data output delay time
tSA
SSI slave access time
tOR
SSI slave out open time
Unit
tCYC (2)
tSUCYC
tSUCYC
tCYC (2)
µs
tCYC (2)
µs
ns
tCYC (2)
ns
1tCYC + 50
—
—
ns
—
—
1.5
—
—
—
—
—
—
—
—
1.5tCYC + 100
1.5tCYC + 200
1.5tCYC + 100
1.5tCYC + 200
tCYC (2)
ns
ns
ns
ns
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
Notes:
1. VCC = 1.8 V to 3.6 V and Topr = −20°C to 85°C, unless otherwise specified.
2. 1tCYC = 1/f1(s)
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 34 of 47
R8C/3MQ Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 35 of 47
R8C/3MQ Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 36 of 47
R8C/3MQ Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 37 of 47
R8C/3MQ Group
Table 5.12
5. Electrical Characteristics
Timing Requirements of I2C bus Interface
Symbol
Parameter
Standard
Typ.
—
12tCYC + 600 (2)
—
3tCYC + 300 (2)
Condition
Min.
Max.
—
Unit
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
tSCLL
SCL input “L” width
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC (2)
—
1tCYC (2)
—
tSTAH
Start condition input hold time
3tCYC (2)
—
—
ns
tSTAS
Retransmit start condition input setup time
3tCYC (2)
—
—
ns
tSTOP
Stop condition input setup time
3tCYC (2)
—
—
ns
tSDAS
Data input setup time
—
—
ns
tSDAH
Data input hold time
1tCYC + 40 (2)
10
—
—
ns
5tCYC + 500
—
—
(2)
—
—
—
ns
—
ns
—
ns
300
ns
ns
ns
Notes:
1. VCC = 1.8 V to 3.6 V and Topr = −20°C to 85°C, unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P (2)
S (1)
tSf
Sr (3)
tSCLL
tSr
tSCL
P (2)
tSDAS
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 38 of 47
R8C/3MQ Group
Table 5.13
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (1) [1.8 V ≤ VCC ≤ 3.6 V]
(Topr = −20°C to 85°C, unless otherwise specified)
Parameter
Power supply current
Single-chip mode,
output pins are open,
other pins are VSS
Standard
Min. Typ. Max.
Condition
High-speed clock mode
XIN clock oscillator on
f(XIN) = 16 MHz
XCIN clock oscillator on
f(XCIN) = 32 kHz
Low-speed on-chip
oscillator on
fOCO-S = 125 kHz
System clock = XIN
CPU clock = Divide-by-4,
(f(BCLK) = 4 MHz)
1.8 V ≤ VCC ≤ 3.6 V
CPU clock = Divide-by-2,
(f(BCLK) = 8 MHz)
2.2 V ≤ VCC ≤ 3.6 V
CPU clock = No division
(f(BCLK) = 16 MHz)
2.7 V ≤ VCC ≤ 3.6 V
Unit
RF = off
—
2.5
—
mA
RF = idle
—
4.0
—
mA
RF = Tx
—
18
—
mA
RF = Rx (reception standby)
—
24
—
mA
RF = Rx
(reception in progress)
—
25
—
mA
RF = off
—
3.5
—
mA
RF = idle
—
5.0
—
mA
RF = Tx
—
19
—
mA
RF = Rx
(reception standby)
—
25
—
mA
RF = Rx
(reception in progress)
—
26
—
mA
RF = off
—
6.0
—
mA
RF = idle
—
7.5
—
mA
RF = Tx
—
21.5
—
mA
RF = Rx
(reception standby)
—
27.5
—
mA
RF = Rx
(reception in progress)
—
28.5
—
mA
Low-speed on-chip oscillator mode
XIN clock off, XCIN clock off,
Low-speed on-chip oscillator on: fOCO-S = 125 kHz
System clock = fOCO-S, CPU clock = Divide-by-8
FMR27 = 1, VCA20 = 0
(flash memory low-current-consumption read mode)
RF = off
—
80
—
µA
Low-speed clock mode
XIN clock off
XCIN clock oscillator on
f(XCIN) = 32 kHz
Low-speed on-chip
oscillator off
System clock = XCIN
CPU clock = No division
FMR27 = 1
VCA20 = 0
(flash memory low-currentconsumption read mode)
RF = off
—
95
—
µA
FMSTP = 1
VCA20 = 0
(Flash memory off,
program operation on RAM)
RF = off
—
45
—
µA
RF = Rx
(reception standby)
—
23
—
mA
Wait mode
XIN clock oscillator on: f(XIN) = 16 MHz
XCIN clock oscillator on: f(XCIN) = 32 kHz
Low-speed on-chip oscillator on: fOCO-S = 125 kHz
System clock = XIN
While a WAIT instruction is executed
Wait mode
XIN clock off
XCIN clock oscillator on
f(XCIN) = 32 kHz
Low-speed on-chip
oscillator off
System clock = XCIN
While a WAIT instruction is
executed
Peripheral function clock on
VCA26 = VCA25 = 0
VCA20 = 1
(voltage detection circuit
stopped, internal power
consumption enabled)
RF = off
—
6.0
—
µA
Peripheral function clock off
VCA26 = VCA25 = 0
VCA20 = 1
(voltage detection circuit
stopped, internal power
consumption enabled)
RF = off
—
4.5
—
µA
Wait mode
XIN clock off
XCIN clock oscillator on
Low-speed on-chip
oscillator on
fOCO-S = 125 kHz
System clock = fOCO-S
While a WAIT instruction is
executed
Peripheral function clock on
VCA26 = VCA25 = 0
VCA20 = 1
(voltage detection circuit
stopped, internal low power
consumption enabled)
RF = off
—
13.0
—
µA
Peripheral function clock off
VCA26 = VCA25 = 0
VCA20 = 1
(voltage detection circuit
stopped, internal low power
consumption enabled)
RF = off
—
7.5
—
µA
Stop mode (Topr = 25°C)
RF = off
XIN clock off, XCIN clock off,
Low-speed on-chip oscillator off,
VCA26 = VCA25 = 0 (voltage detection circuit stopped)
—
2.0
—
µA
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 39 of 47
R8C/3MQ Group
Table 5.14
5. Electrical Characteristics
Electrical Characteristics (2) [2.7 V ≤ VCC ≤ 3.6 V]
Symbol
Parameter
VOH
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis
P0_4, P1, P3_0,
P3_1, P3_3 to P3_5,
P3_7, P4_3 to P4_5
P0_4, P1, P3_0,
P3_1, P3_3 to P3_5,
P3_7, P4_3 to P4_5
Condition
Drive capacity High IOH = −5 mA
Drive capacity Low IOH = −1 mA
Max.
VCC
VCC
Unit
V
V
—
—
—
—
0.5
0.5
V
V
0.1
0.4
—
V
0.1
0.5
—
V
Input “H” current
VI = 3 V, VCC = 3.0 V
—
IIH
IIL
Input “L” current
VI = 0 V, VCC = 3.0 V
—
RPULLUP Pull-up resistance
VI = 0 V, VCC = 3.0 V
42
RfXIN
Feedback resistance XIN
—
RfXCIN
Feedback resistance XCIN
—
VRAM
RAM hold voltage
During stop mode
1.8
Note:
1. 2.7 V ≤ VCC ≤ 3.6 V, Topr = −20°C to 85°C, and f(XIN) =16 MHz, unless otherwise specified.
—
—
84
0.3
8
—
4.0
µA
−4.0
µA
kΩ
MΩ
MΩ
V
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Drive capacity High IOL = 5 mA
Drive capacity Low IOL = 1 mA
Standard
Min.
Typ.
VCC − 0.5
—
VCC − 0.5
—
INT0, INT1, INT3, KI0, VCC = 3.0 V
KI1, KI2, KI3, KI4,
KI6, KI7, TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRCTRG, TRCCLK,
RXD0, CLK0, SSI,
SCL, SDA, SSO
VCC = 3.0 V
RESET
168
—
—
3.6
Page 40 of 47
R8C/3MQ Group
5. Electrical Characteristics
Timing requirements
Table 5.15
(VCC = 3 V, Topr = −20°C to 85°C, unless otherwise specified)
TRAIO Input
Symbol
Standard
Min.
Max.
300
—
120
—
120
—
Parameter
tc(TRAIO)
TRAIO input cycle time
tWH(TRAIO) TRAIO input “H” width
tWL(TRAIO) TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
TRAIO Input Timing Diagram when VCC = 3 V
Figure 5.8
Table 5.16
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
—
150
—
150
—
—
120
0
—
30
—
90
—
—
30
120
—
90
—
Parameter
CLK0 input cycle time
CLK0 input “H” width
CLK0 Input “L” width
TXD0 output delay time
TXD0 hold time
RXD0 input setup time
RXD0 input hold time
TXD0 output delay time
RXD0 input setup time
RXD0 input hold time
When an external clock is selected
When an internal clock is selected
tC(CK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 3 V
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXD0
td(C-Q)
tsu(D-C)
th(C-D)
RXD0
Figure 5.9
Serial Interface Timing Diagram when VCC = 3 V
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 41 of 47
R8C/3MQ Group
Table 5.17
5. Electrical Characteristics
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 7)
INTi input “H” width, KIi input “H” width
Standard
Min.
Max.
—
380 (1)
INTi input “L” width, KIi input “L” width
380 (2)
Symbol
tW(INH)
tW(INL)
Parameter
—
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 7)
Figure 5.10
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 3 V
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 42 of 47
R8C/3MQ Group
Table 5.18
5. Electrical Characteristics
Electrical Characteristics (3) [1.8 V ≤ VCC < 2.7 V]
Symbol
VOH
VOL
Parameter
Output “H” voltage
Output “L” voltage
VT+-VT-
Hysteresis
IIH
Input “H” current
IIL
Input “L” current
Standard
Condition
Unit
Min.
Typ.
Max.
Drive capacity High IOH = −2 mA
VCC − 0.5
—
VCC
V
IOH = −1 mA
VCC − 0.5
—
VCC
V
Drive capacity High IOL = 2 mA
—
—
0.5
V
Drive capacity Low
—
—
0.5
V
INT0, INT1, INT3, KI0, VCC = 2.2 V
KI1, KI2, KI3, KI4,
KI6, KI7, TRAIO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRCTRG, TRCCLK,
RXD0, CLK0, SSI,
SCL, SDA, SSO
0.05
0.20
—
V
VCC = 2.2 V
0.05
0.20
—
V
—
—
4.0
µA
P0_4, P1, P3_0,
P3_1, P3_3 to P3_5,
P3_7, P4_3 to P4_5
P0_4, P1, P3_0,
P3_1, P3_3 to P3_5,
P3_7, P4_3 to P4_5
RESET
Drive capacity Low
IOL = 1 mA
VI = 2.2 V, VCC = 2.2 V
RPULLUP Pull-up resistance
VI = 0 V, VCC = 2.2 V
—
—
−4.0
µA
VI = 0 V, VCC = 2.2 V
70
140
300
kΩ
RfXIN
Feedback resistance
XIN
—
0.3
—
MΩ
RfXCIN
Feedback resistance
XCIN
—
8
—
MΩ
VRAM
RAM hold voltage
1.8
—
3.6
V
During stop mode
Note:
1. 1.8 V ≤ VCC < 2.7 V, Topr = −20°C to 85°C, and f(XIN) = 16 MHz, unless otherwise specified.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 43 of 47
R8C/3MQ Group
5. Electrical Characteristics
Timing requirements
Table 5.19
(VCC = 2.2 V, Topr = −20°C to 85°C, unless otherwise specified)
TRAIO Input
Symbol
tc(TRAIO)
Standard
Parameter
TRAIO input cycle time
Min.
Max.
Unit
500
—
tWH(TRAIO) TRAIO input “H” width
200
—
ns
tWL(TRAIO)
200
—
ns
TRAIO input “L” width
tC(TRAIO)
ns
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.11
Table 5.20
TRAIO Input Timing Diagram when VCC = 2.2 V
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLK0 input cycle time
800
—
tW(CKH)
CLK0 input “H” width
400
—
ns
tW(CKL)
CLK0 input “L” width
400
—
ns
td(C-Q)
TXD0 output delay time
—
200
ns
th(C-Q)
TXD0 hold time
0
—
ns
tsu(D-C)
RXD0 input setup time
150
—
ns
th(C-D)
RXD0 input hold time
90
—
ns
th(C-Q)
TXD0 output delay time
—
200
ns
tsu(D-C)
RXD0 input setup time
150
—
ns
th(C-D)
RXD0 input hold time
90
—
ns
When an external clock is selected
When an internal clock is selected
tC(CK)
ns
VCC = 2.2 V
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXD0
td(C-Q)
tsu(D-C)
th(C-D)
RXD0
Figure 5.12
Serial Interface Timing Diagram when VCC = 2.2 V
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 44 of 47
R8C/3MQ Group
Table 5.21
5. Electrical Characteristics
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 7)
Symbol
tW(INH)
tW(INL)
Standard
Parameter
Unit
Min.
Max.
INTi input “H” width, KIi input “H” width
1000 (1)
—
ns
INTi input “L” width, KIi input “L” width
1000 (2)
—
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 7)
Figure 5.13
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 2.2 V
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 45 of 47
R8C/3MQ Group
Table 5.22
5. Electrical Characteristics
Transceiver Transmission Characteristics
(VCC = VCCRF = 3.3 V, Topr = 25°C, unless otherwise specified)
Parameter
Condition
Standard
IEEE802.15.4
standard
Unit
Min.
Typ.
Max.
Internal voltage
—
1.45
—
—
V
Nominal output power
–3
0
3
–3 or more
dBm
Transmit bit rate
—
250
—
250
kbps
Transmit chip rate
—
2000
—
2000
kchips/s
Programmable output power range
32 steps
—
32
—
32 steps
dB
Harmonics
2nd harmonics
External notch filter
—
—
–47.2
–41.2 or less
dBm
—
—
–47.2
—
Spurious emission
30 – 88 MHz
Maximum output power,
Renesas evaluation board
—
—
–55.2
FCC
—
—
–51.7
FCC
3rd harmonics
88 – 216 MHz
216 – 960 MHz
—
—
–49.2
FCC
960 – 1000 MHz
—
—
–41.2
FCC
1 – 12.75 GHz
—
—
–41.2
FCC (1)
1.8 – 1.9 GHz
—
—
–47
ETSI
5.15 – 5.3 GHz
—
—
–47
ETSI
dBm
Error vector magnitude EVM
1000 chips
—
—
35
35 or less
%
Power spectral
density
|f-fc| > 3.5 MHz
—
—
–30
–30 or less
dBm
—
—
–20
–20 or less
dB
–40
—
40
Within ±40
ppm
Absolute limit
Relative limit
Frequency tolerance
|f-fc| > 3.5 MHz
Including crystal ±20 ppm
Note:
1. Notes on FFC certification testing
When using 26 CH (2480 MHz), adjust the transmit power to meet the FCC requirements and standards at 2483.5 MHz.
Table 5.23
Transceiver Reception Characteristics
(VCC = VCCRF = 3.3 V, Topr = 25°C, unless otherwise specified)
Parameter
Condition
Internal voltage
Max.
IEEE802.15.4
standard
Unit
—
1.45
—
—
V
—
2480
Min. 2405/
Max. 2480
MHz
PER = 1%
PSDU
Length = 20 octets
Interframe spacing
12 symbols
(IEEE802.15.4
minimum spacing)
—
–95
–85
–85 or less
dBm
PER = 1%
0
—
—
–20 or more
dBm
PER = 1%
Prf = –82 dBm
0
—
—
0 or more
dB
0
—
—
PER = 1%
Prf= –82 dBm
30
—
—
30 or more
dB
30
—
—
PER = 1%
Prf= –82 dBm
30
—
—
—
dB
< –15 MHz
30
—
—
30 – 1000 MHz
Renesas evaluation board
ETSI EN300/328
dBm
Receiver sensitivity
Maximum input level
Adjacent channel
rejection
+5 MHz
Alternate channel
rejection
+10 MHz
Spurious emission
Typ.
2405
RF input frequency
Rejection
Standard
Min.
–5 MHz
–10 MHz
> +15 MHz
1 – 12.75 GHz
—
—
–57
—
—
–47
–80
—
80
±80 or less
ppm
RSSI range
Prf (min) = –75 dBm
40
75
—
40 or more
dB
RSSI accuracy
Prf = –75 to –35 dBm
–6
—
6
Within ±6
dB
Symbol error tolerance
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 46 of 47
R8C/3MQ Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
R01DS0044EJ0100 Rev.1.00
Aug 11, 2011
Page 47 of 47
REVISION HISTORY
Rev.
Date
0.10
1.00
Nov 19, 2010
Aug 11, 2011
Page
—
All pages
4
5
6
7
9, 10
12
14
16, 17
19
20
24, 25
32
39
46
R8C/3MQ Group Datasheet
Description
Summary
First Edition issued
“Preliminary”, “Under development” deleted
Table 1.2 revised, Note 1 added
Table 1.3 “(D): Under development”, (P): Under planning” deleted
Figure 1.2 revised
Figure 1.3 revised
Table 1.5, Table 1.6 revised
2.4 revised
3.1 revised
Table 4.2, Table 4.3 revised
Table 4.5 Note 2 added
Table 4.6 revised
Table 4.10, Table 4.11 revised
Table 5.6 revised
Table 5.13 revised
Table 5.22, Table 5.23 revised, Table 5.22 Note 1 added
All trademarks and registered trademarks are the property of their respective owners.
C-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
7.
Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Refer to "http://www.renesas.com/" for the latest and detailed information.
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Colophon 1.1