AD REF02HSZ

5 V Precision Voltage
Reference/Temperature Transducer
REF02
FEATURES
PIN CONFIGURATIONS
5 V output, ±0.3% max
Temperature voltage output, 1.96 mV/°C
Adjustment range, ±3% min
Excellent temperature stability, 8.5 ppm/°C max
Low noise, 15 µV p-p max
Low supply current, 1.4 mA max
Wide input voltage range, 7 V to 40 V
High load-driving capability, 10 mA
No external components
Short-circuit proof
NC
8
NC 1
7
NC
VIN 2
VOUT
6
NC 3
5
TRIM
4
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
00375-F-001
GROUND
(CASE)
Figure 1. TO-99 (J-Suffix)
REF02
TOP VIEW
(Not to Scale)
TEMP 3
GND 4
GENERAL DESCRIPTION
8
NC
7
NC
6 VOUT
5 TRIM
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
The REF02 precision voltage reference provides a stable 5 V
output that can be adjusted over a ±6% range with minimal
effect on temperature stability. Single-supply operation over an
input voltage range of 7 V to 40 V, low current drain of 1 mA,
and excellent temperature stability are achieved with an
improved band gap design. Low cost, low noise, and low power
make the REF02 an excellent choice whenever a stable voltage
reference is required. Applications include DACs and ADCs,
portable instrumentation, and digital voltmeters. The versatility
of the REF02 is enhanced by its use as a monolithic temperature
transducer. For new designs, refer to ADR02.
00375-F-002
NC 1
VIN 2
NC
2
1
NC
NC
3
NC
NC
Figure 2. 8-Lead PDIP (P-Suffix), 8-Lease CERDIP (Z-Suffix),
8-Lead SOIC (S-Suffix)
20 19
NC 4
18 NC
VIN 5
17 NC
REF02
NC 6
TOP VIEW
(Not to Scale)
TEMP 7
NC 8
16 NC
15 VOUT
14 NC
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
00375-F-003
NC
TRIM
NC
NC
10 11 12 13
GND
9
Figure 3. REF02RC/883 LCC (RC-Suffix)
INPUT
OUTPUT RESISTORS
REF02 OPTION
Z PACKAGE AND
883C PRODUCT
R9
18kΩ
P, S, RJ PACKAGES
18kΩ
R11
2kΩ
R12
6.1kΩ
4.5kΩ
R7
R8
2
R14
Q15
Q7
Q8
15kΩ
R15
Q13
Q14
Q18
Q9
Q12
Q16
Q11
Q10
R6
R3
Q6
Q19
Q21
C1
Q17
Q5
6
R13
R4
OUTPUT
R12*
Q1
TEMP
3 R1
R5
Q2
Q3
Q20
R9*
≈1.23V
5
TRIM
R11*
R10
R2
4
*SEE OUTPUT RESISTORS
GROUND
00375-F-004
Q4
Figure 4. Simplified Schematic
Rev. F
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
REF02
TABLE OF CONTENTS
Specifications..................................................................................... 3
Output Adjustment ........................................................................ 10
Electrical Specifications............................................................... 3
Temperature Monitoring........................................................... 10
Electrical Specifications............................................................... 4
Reference Stack with Excellent Line Regulation .................... 11
Electrical Specifications............................................................... 5
Precision Current Source .......................................................... 11
Electrical Specifications............................................................... 6
Supply Bypassing ........................................................................ 12
Absolute Maximum Ratings............................................................ 7
Outline Dimensions ....................................................................... 13
ESD Caution.................................................................................. 7
Outline Dimensions ....................................................................... 14
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 15
REVISION HISTORY
7/04—Data Sheet Changed from Rev. E to Rev. F
10/03—Data Sheet Changed from Rev. C to Rev. D.
Updated Format..................................................................Universal
Updated TPCs.....................................................................Universal
Changes to Simplified Schematic ................................................... 1
Changes to Features .........................................................................1
Changes to Specifications ................................................................ 3
Changes to Electrical Specifications ..............................................2
Changes to Specifications ................................................................ 4
Change to Absolute Maximum Ratings ........................................4
Changes to Specifications ................................................................ 5
Changes to Ordering Guide .............................................................4
Changes to Specifications ................................................................ 6
Deleted Typical Electrical Characteristics table ........................... 4
Changes to Figure 18...................................................................... 10
Deleted Wafer Test Limits ................................................................4
Changes to Ordering Guide .......................................................... 15
Deleted Figure 1.................................................................................4
3/04—Data Sheet Changed from Rev. D to Rev. E.
10/02—Data Sheet Changed from Rev. B to Rev. C.
Changes to Features.......................................................................... 1
Changes to Features ..........................................................................1
Changes to Specifications ................................................................ 2
Changes to General Description .....................................................1
Changes to Ordering Guide ............................................................ 4
Changes to Simplified Schematic ....................................................1
Replaced TPCs 3 and 4 .................................................................... 5
Changes to Specifications.................................................................2
Added Temperature Monitoring section ...................................... 7
Changes to Absolute Maximum Ratings .......................................5
Updated Figure 5 ............................................................................. 7
Changes to Package Type ................................................................5
Deleted Table I .................................................................................. 7
Changes to Ordering Guide .............................................................5
Updated Figure 6 ............................................................................. 7
Updated to Outline Dimensions .................................................. 11
Revision 0: Initial Version
Rev. F | Page 2 of 16
REF02
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, TA = +25°C, unless otherwise noted.
Table 1.
Parameter
Output Voltage
Output Adjustment Range
Output Voltage Noise1
Line Regulation2
Load Regulation2
Turn-on Settling Time1
Quiescent Supply Current
Load Current
Sink Current3
Short-Circuit Current
Temperature Voltage Output4
Z Package and 883C Product
P, S, and J Packages
Symbol
VO
∆VTRIM
en p-p
tON
ISY
IL
IS
ISC
Conditions
IL = 0 mA
RP = 10 kΩ
0.1 Hz to 10 Hz
VIN = 8 V to 40 V
IL = 0 mA to 10 mA
To ±0.1% of Final Value
No Load
VO = 0
VT
VT
REF02A/REF02E
Min
Typ
Max
4.985 5.000 5.015
±3
±6
10
15
0.006 0.010
0.005 0.010
5
1.0
1.4
10
–0.5
−0.3
30
630
550
1
Guaranteed by design.
Line and load regulation specifications include the effect of self-heating.
During sink current test the device meets the output voltage specified.
4
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
2
3
Rev. F | Page 3 of 16
REF02/REF02H
Min
Typ
Max
4.975 5.000 5.025
±3
±6
10
15
0.006 0.010
0.006 0.010
5
1.0
1.4
10
–0.3
–0.5
30
630
550
Unit
V
%
µV p-p
%/V
%/mA
µs
mA
mA
mA
mA
mV
mV
REF02
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, −55°C ≤ TA ≤ +125°C for REF02A and REF02, 0°C ≤TA ≤ 70°C for REF02E and REF02H, IL = 0 mA, unless otherwise
noted.
Table 2.
Parameter
Output Voltage Change
with Temperature1, 2
Output Voltage
Temperature Coefficient3
Change in VO Temperature
Coefficient with Output
Adjustment
Line Regulation
(VIN = 8 V to 40 V)4
Load Regulation
(IL = 0 mA to 8 mA)4
Temperature Voltage Output
Temperature Coefficient5
Z Package and 883C Product
P, S, and J Packages
Symbol
Conditions
∆VOT
0°C ≤ TA ≤ 70°C
−55°C ≤TA ≤+125°C
TCVO
RP = 10 kΩ
0°C ≤ TA ≤ 70°C
−55°C ≤ TA ≤ +125°C
0°C ≤ TA ≤ 70°C
−55°C ≤ TA ≤ +125°C
REF02A/REF02E
Min Typ
Max
0.02
0.06
0.06
0.15
REF02/REF02H
Min Typ
Max
0.07
0.17
0.18
0.45
Unit
%
%
3
8.5
10
25
ppm/°C
0.7
0.007
0.009
0.006
0.007
0.012
0.015
0.010
0.012
0.7
0.007
0.009
0.007
0.009
0.012
0.015
0.012
0.015
ppm/%
%/V
%/V
%/mA
%/mA
TCVT
2.10
1.96
2.10
1.96
mV/°C
mV/°C
∆VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as
a percentage of 5 V:
1
∆VOT =
VMAX − VMIN
5V
× 100
∆VOT specification applies trimmed to 5,000 V or untrimmed.
TCVO is defined as ∆VOT divided by the temperature range, i.e.,
2
3
TCVO =
∆VOT
70°C
4
Line and load regulation specifications include the effect of self-heating.
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
5
Rev. F | Page 4 of 16
REF02
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Output Voltage
Output Adjustment Range
Output Voltage Noise1
Line Regulation2
Load Regulation2
Symbol
VO
∆VTRIM
en p-p
Turn-On Settling Time1
Quiescent Supply Current
Load Current
Sink Current3
Short-Circuit Current
Temperature Voltage Output4
Z Package and 883C Product
P, S, and J Packages
tON
ISY
IL
IS
ISC
Conditions
IL = 0 mA
RP = 10 kΩ
0.1 Hz to 10 Hz
VIN= 8 V to 40 V
IL = 0 mA to 8 mA
IL = 0 mA to 4 mA
To ±0.1% of Final Value
No Load
Min
4.950
±2.7
5
1.0
8
−0.3
VO = 0
VT
VT
REF02C
Typ
5.000
±6.0
12
0.009
0.006
−0.5
30
630
550
1
Guaranteed by design.
Line and load regulation specifications include the effect of self-heating.
3
During sink current test the device meets the output voltage specified.
4
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
2
Rev. F | Page 5 of 16
Max
5.050
Min
4.900
±2.0
18
0.015
0.015
REF02D
Typ
Max
5.000 5.100
±6.0
12
0.010 0.04
−0.5
30
Unit
V
%
µV p-p
%/V
%/mA
%/mA
µs
mA
mA
mA
mA
630
550
mV
mV
0.015
5
1.0
1.6
8
−0.3
0.04
2.0
REF02
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, IL = 0 mA, 0°C≤TA ≤ 70°C for REF02CJ, REF02CZ, REF02DP, and −40°C ≤TA ≤+85°C for REF02CP and REF02CS, unless
otherwise noted.
Table 4.
Parameter
Output Voltage Change
with Temperature1, 2
Output Voltage3
Temperature Coefficient
Change in VO Temperature
Coefficient with Output
Adjustment
Line Regulation4
Load Regulation4
Temperature Voltage Output
Temperature Coefficient5
Z Package and 883C Product
P, S, and “J” Packages
Symbol
Conditions
Min
REF02C
Typ
Max
Min
REF02D
Typ
Max
Unit
∆VOT
0.14
0.45
0.49
1.7
%
TCVO
20
65
70
250
ppm/°C
0.7
0.011
0.008
0.018
0.018
0.7
0.012
0.016
0.05
0.05
ppm/%
%/V
%/mA
RP = 10 kΩ
VIN= 8 V to 40 V
IL= 0 mA to 5 mA
TCVT
2.10
1.96
2.10
1.96
mV/°C
mV/°C
∆VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as
a percentage of 5 V:
1
∆VOT =
VMAX − VMIN
5V
× 100
∆VOT specification applies trimmed to 5,000 V or untrimmed.
TCVO is defined as ∆VOT divided by the temperature range, i.e.,
2
3
TCVO =
∆VOT
70°C
4
Line and load regulation specifications include the effect of self-heating.
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
5
Rev. F | Page 6 of 16
REF02
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Input Voltage
Output Short-Circuit Duration
to Ground or VIN
Storage Temperature
J, RC, and Z Packages
P Package
Operating Temperature Range
REF02A, REF02J, REF02RC
REF02CJ, REF02CZ
REF02CP, REF02CS, REF02E,
REF02H
Lead Temperature Range (Soldering 10 sec)
Table 6. Package Thermal Resistance
Rating
40 V
Indefinite
–65°C to +150°C
–65°C to +125°C
Package Type
TO-99 (J)
8-Lead CERDIP (Z)
8-Lead PDIP (P)
20-Terminal Ceramic LCC (RC)
8-Lead SOIC (S)
θJA
170
162
110
120
160
θJC
24
26
50
40
44
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
*θJA is specified for worst-case mounting conditions, i.e. ,θJA is specified for
device in socket for TO, CERDIP, PDIP, and LCC packages; θJA is specified for
device soldered to printed circuit board for SOIC packages.
–55°C to +125°C
0°C to 70°C
–40°C to +85°C
300°C
Absolute maximum ratings apply to both DICE packaged parts,
unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 7 of 16
REF02
TYPICAL PERFORMANCE CHARACTERISTICS
20
VIN = 15V
TA = 25°C
1k
100
100
1k
10k
FREQUENCY (Hz)
100k
18
17
16
15
14
10
1M
56
0.0310
46
0.1000
36
0.3100
26
1.0000
VIN = 15V
3.1000
100
1k
10k
FREQUENCY (Hz)
10.0000
1M
100k
Figure 6. Line Regulation vs. Frequency
1.0
0.9
0.8
0.6
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
Figure 9. Normalized Load Regulation (∆IL = 10 mA) vs. Temperature
1.4
VIN = 15V
0.014
1.3
LINE REG–T/LINE REG (25°C)
0.012
0.010
0.008
0.006
0.004
DEVICE IMMERSED
IN 75°C OIL BATH
25°C
0
10
20
TIME (s)
00375-F-007
0
–10
1.1
0.7
0.016
0.002
1.2
30
40
1.2
1.1
1.0
0.9
0.8
00375-F-010
0
10
40
1.3
LOAD REG–T/LOAD REG (25°C)
0.0100
LINE REGULATION (%/V)
66
VIN = 15V
TA = 25°C
35
1.4
00375-F-006
0.0031
16
20
25
30
INPUT VOLTAGE (V)
Figure 8. Maximum Load Current vs. Input Voltage
76
PERCENT CHANGE IN OUTPUT VOLTAGGE (%)
LINE REGULATION (dB)
Figure 5. Output Wideband Noise vs. Bandwidth (0.1 Hz to
Frequency Indicated)
15
00375-F-009
10
10
19
00375-F-008
MAXIMUM LOAD CURRENT (mA)
TA = 25°C
00375-F-005
OUTPUT NOISE (µV p-p)
10k
0.7
0.6
–60
50
Figure 7. Output Change Due to Thermal Shock
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 10. Normalized Line Regulation vs. Temperature
Rev. F | Page 8 of 16
140
REF02
0.03
30
0.02
0.01
0
5
10
15
20
INPUT VOLTAGE (V)
25
VIN = 15V
1.1
1.0
0.9
0.8
00375-F-026
QUIESCENT CURRENT (mA)
1.2
–20
0
20
40
60
80
TEMPERATURE (°C)
100
15
10
5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 13. Maximum Load Current vs. Temperature
1.3
–40
20
0
–60
30
Figure 11. Line Regulation vs. Input Voltage
0.7
–60
25
00375-F-012
MAXIMUM LOAD CURRENT (mA)
VIN = 15V
00375-F-011
LINE REGULATION (%/V)
TA = 25°C
120
140
Figure 12 Quiescent Current vs. Temperature
Rev. F | Page 9 of 16
140
REF02
OUTPUT ADJUSTMENT
The REF02 trim terminal can be used to adjust the output
voltage over a 5 V ±300 mV range. This feature lets the system
designer trim system errors by setting the reference to a voltage
other than 5 V. The output also can be set to exactly 5.000 V or
to 5.12 V for binary applications.
VO+
+2.5V
+5V
2
R1
5.6kΩ
6
REF02
R2
5.6kΩ
4
15V
2
VIN
V O+ =
6
VO
R1
R2
), VO– =
)
(V
(V
R1 + R2 REF
R1 + R2 REF
OUTPUT
2
+
3
–9V
Figure 17. ±2.5 V Reference
5
TRIM
TEMP
–
OP02
4
+VO
–2.5V
REF02
3
7
6
00375-F-016
VREF
10kΩ
TEMPERATURE MONITORING
00375-F-013
GND
4
Figure 14. Output Adjustment Circuit
Adjustment of the output does not significantly affect the
temperature performance of the device. The temperature
coefficient change is approximately 0.7 ppm/°C for 100 mV of
As described previously, the REF02 provides a TEMP output
(Pin 3) that varies linearly with temperature. This output can be
used to monitor the temperature change in the system. The
voltage at VTEMP is approximately 550 mV at 25°C, and the
temperature coefficient is approximately 1.96 mV/°C (see
Figure 18).
output adjustment.
850
+18V
800
2
VIN = 9V
SAMPLE SIZE = 6
750
TEMP PIN OUTPUT (mV)
VIN
REF02
00375-F-014
GND
–18V
∆VTEMP/∆T = 2.1mV/°C
650
600
∆VTEMP/∆T = 1.96mV/°C
550
J, S, AND P PACKAGES
500
Figure 15. Burn-In Circuit
00375-F-017
4
Z PACKAGE AND 833 PRODUCT
700
450
+15V
400
–50
2
VIN
VO
3
10kΩ
+15V
0.1µF
–5V
OP02
–15V
Figure 16. ±5 V Reference
00375-F-015
5kΩ
100
125
A voltage change of 39.2 mV at the TEMP pin corresponds to a
20°C change in temperature.
5
4
25
50
75
TEMPERATURE (°C)
Figure 18. Voltage at TEMP Pin vs. Temperature
10kΩ
TEMP TRIM
GND
0
+5V
6
REF02
–25
The TEMP function is provided as a convenience rather than a
precise feature. Since the voltage at the TEMP node is acquired
from the band gap core, current pulling from this pin will have
a significant effect on VOUT. Care must be taken to buffer the
TEMP output with a suitable low bias current op amp, such as
the AD8601, AD820, or OP1177 (all of which would result in
less than a 100 V change in ΔVOUT) See Figure 19. Without
buffering, even tens of microamps drawn from the TEMP pin
can cause VOUT to fall out of specification.
Rev. F | Page 10 of 16
REF02
27V TO 55V
U1
REF02
15V
VIN
VIN
TEMP
V+
OP1177
U2
2
VIN
VO
VO
TRIM
V–
15V
6
REF02
GND
00375-F-018
VTEMP
1.9mV/°C
VOUT
TRIM
5
10kΩ
GND
4
2
Figure 19. Temperature Monitoring
VIN
VO
10V
6
REF02
V+ (12V TO 32V)
TRIM
GND
2
R7
27kΩ
VO
HEATING
ELEMENT
REF02
TEMP
GND
(SEE NOTE 1) 4
6
3
R1
(9.2kΩ)
R3
(1.3kΩ)
5V
4
6
REF02
R6
2
VO
10kΩ
8
V+
+
CMP02 V–
3 –
TRIM
7
5
RB
6.8kΩ
10kΩ
GND
4
00375-F-020
2
VIN
VIN
5
4
1
R2
1.5kΩ
Figure 21. Reference Stack
PRECISION CURRENT SOURCE
R4
2.7kΩ
Figure 20. Temperature Controller
REFERENCE STACK WITH EXCELLENT LINE
REGULATION
A current source with 35 V output compliance and excellent
output impedance can be obtained using this circuit. REF02
keeps the line voltage and power dissipation constant in device;
the only important error consideration at room temperature is
the negative supply rejection of the op amp. The typical 3 µV/V
PSRR of the OP02E will create a 20 ppm change (3 µV/V ×
35 V/5 V) in output current over a 25 V range. For example, a
5 mA current source can be built (R = 1 kΩ) with 350 MΩ
output impedance.
Two REF01s and one REF02 can be stacked to yield 5.000 V,
15.000 V, and 25.000 V outputs. An additional advantage is
near-perfect line regulation of the 5.0 V and 15.0 V output. A 27
V to 55 V input change produces an output change that is less
than the noise voltage of the devices. A load bypass resistor
(RB) provides a path for the supply current (ISY) of the 15.000 V
regulator.
+50V
35V
RO =
20 ×10–6 × 5mA
6
VO
REF02
2
GND
2
VIN
In general, any number of REF01s and REF02s can be stacked
this way. For example, 10 devices will yield 10 outputs in 5 V or
10 V steps. The line voltage can change from 100 V to 130 V.
However, care must be taken to ensure that the total load
currents do not exceed the maximum usable current (typically
21 mA).
2
VIN
VO
4
6
REF02
C
1
GND
R
(TRIM FOR
CALIBRATION)
R
4
C
7
6
OP02E
2
VO = 0V
TO 25V
3
4
IO =
–5V
Figure 22. Precision Current Source
Rev. F | Page 11 of 16
5V
R
00375-F-021
NOTES
1. REF02 SHOULD BE THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED.
2. NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF 60°C.
3. R3 = R1 || R2 || R6
00375-F-019
R5
2.2kΩ
REF02
15V
+7.5V (±10%)
2
VIN
VO
VIN
6
TEMP
5
TRIM
VO
REF02HJ
REF02
3
+7.5V
2
IOUT = +
R
5V
+ 1mA
R
GND
4
GND
6
VO(+) = +3V
R1
20kΩ
R2
13.3kΩ
VOLTAGE COMPLIANCE: –25V TO +8V
IOUT
00375-F-022
A1
4
1/2 OP04CK
–7.5V
–7.5V
Figure 23. Current Source
VOLTAGE COMPLIANCE: –9V TO +25V
2
VIN
VO
6
TRIM
TEMP
5
IOUT = +
R
SUPPLY BYPASSING
For best results, it is recommended that the power supply pin be
bypassed with a 0.1 µF disc ceramic capacitor.
00375-F-023
4
–15V
Figure 24. Current Sink
5kΩ
5kΩ
LSB
MSB
+15V
VIN V
O
0.1µF
REF02
GND
4
6
5
5kΩ
B1 B2 B3 B4 B5 B6 B7 B8
lO
DAC08
V+
V–
CC
lO
VLC
4
2
OP02
EO
5kΩ
+15V
–15V
–15V
00375-F-024
2
R3
1kΩ
Figure 26. ±3 V Reference
5V
+ 1mA
R
GND
+15V
VO(–) = –3V
A2
–7.5V (±10%)
REF02
3
R4
2kΩ
00375-F-025
1/2 OP04CK
IOUT
Figure 25. DAC Reference
Rev. F | Page 12 of 16
REF02
OUTLINE DIMENSIONS
0.055 (1.40)
MAX
8
REFERENCE PLANE
0.1850 (4.70)
0.1650 (4.19)
5
0.310 (7.87)
0.220 (5.59)
PIN 1
1
4
0.3700 (9.40)
0.3350 (8.51)
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
15°
0°
0.2000
(5.08)
BSC
0.0190 (0.48)
0.0160 (0.41)
4
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.0340 (0.86)
0.0280 (0.71)
45° BSC
Figure 29. 8-Lead Metal Can [TO-99]
J-Suffix
(H-08)
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
8
BASE & SEATING PLANE
0.100 (2.54)
0.064 (1.63)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.0450 (1.14)
0.0270 (0.69)
1
0.1000
(2.54)
BSC
0.0210 (0.53)
0.0160 (0.41)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
1
7
COMPLIANT TO JEDEC STANDARDS MO-002AK
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 27. 8-Lead Ceramic Dual In-Line Package (CERDIP)
Z-Suffix
(Q-8)-
5
3
2
0.0400 (1.02)
0.0100 (0.25)
0.015 (0.38)
0.008 (0.20)
6
4
0.0400 (1.02) MAX
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8
0.1600 (4.06)
0.1400 (3.56)
5
0.100 (2.54) BSC
0.023 (0.58)
0.014 (0.36)
0.5000 (12.70)
MIN
0.2500 (6.35) MIN 0.1000 (2.54)
BSC
0.0500 (1.27) MAX
0.3350 (8.51)
0.3050 (7.75)
0.005 (0.13)
MIN
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.358 (9.09)
0.342 (8.69)
SQ
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.358
(9.09)
MAX
SQ
0.088 (2.24)
0.054 (1.37)
0.200 (5.08)
REF
0.100 (2.54) REF
0.015 (0.38)
MIN
0.075 (1.91)
REF
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.055 (1.40)
0.045 (1.14)
19
18
3
20
4
0.028 (0.71)
0.022 (0.56)
1
BOTTOM
VIEW
14
13
0.050 (1.27)
BSC
8
9
45° TYP
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 30. 20-Terminal Ceramic Leadless Chip Carrier (LCC)
RC-Suffix
(E-20A)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 28. 8-Lead Plastic Dual In-Line Package (PDIP)
P-Suffix
(N-8)
Rev. F | Page 13 of 16
REF02
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497) 1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 31. 8-Lead Standard Small Outline Package (SOIC)
Narrow Body
S-Suffix
(R-8)
Rev. F | Page 14 of 16
REF02
ORDERING GUIDE
Model
REF02AJ/883C2
REF02EJ
REF02J
REF02HJ
REF02CJ
REF02AZ
REF02AZ/883C2
REF02EZ
REF02Z
REF02HZ
REF02CZ
REF02HP
REF02CP
REF02CS3
REF02CS-REEL
REF02CSZ-REEL4
REF02CS-REEL7
REF02HS
REF02HSZ4
REF02DP
REF02RC/8832
TA = 25°C
∆VOS Max (mV)
±15
±15
±25
±25
±50
±15
±15
±15
±25
±25
±50
±25
±50
±50
±50
±50
±50
±25
±25
±100
±25
Operating Temperature
Range (°C )1
–55°C to +125
–40°C to +85
–55°C to +125
–40°C to +85
0°C to 70
–55°C to +125
–55°C to +125
–40°C to +85
–55°C to +125
–40°C to +85
0°C to 70
–40°C to +85
–40°C to +85
–40°C to +85
–40°C to +85
–40°C to +85
–40°C to +85
–40°C to +85
–40°C to +85
0°C to 70
–55°C to +125
1
Package Description
TO-99
TO-99
TO-99
TO-99
TO-99
CERDIP-8
CERDIP-8
CERDIP-8
CERDIP-8
CERDIP-8
CERDIP-8
PDIP-8
PDIP-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
SOIC-8
PDIP-8
LCC-20
Burn-in is available on commercial and industrial temperature range parts in CERDIP, PDIP, and TO-can packages.
For devices processed in total compliance to MIL-STD-883, add 883 after part number. Consult factory for 883 data sheet.
3
For availability and burn-in information on SOIC package, contact your local sales office.
4
Z = Pb-free part.
2
Rev. F | Page 15 of 16
Package Option
J-8
J-8
J-8
J-8
J-8
Z-8
Z-8
Z-8
Z-8
Z-8
Z-8
P-8
P-8
S-8
S-8
S-8
S-8
S-8
S-8
P-8
RC-20
REF02
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00375-0-7/04(F)
Rev. F | Page 16 of 16