Page No. : 1/10 RS6517 3A, 20V, 400KHz DC/DC Asynchronous Step‐Down Converter General Description The RS6517 is a high‐efficiency asynchronous step‐down DC/DC converter that can deliver up to 3A output current from 4.75V to 20V input supply. The RS6517's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Cycle‐by‐cycle current limit provides protection against shorted outputs and thermal shutdown protection. The RS6517 also provides output under voltage protection and thermal shutdown protection. The low current (<30μA) shutdown mode provides output disconnection, enabling easy power management in battery‐powered systems. Features Applications ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 3A Output Current Up to 93% Efficiency Integrated 100mΩ Power MOSFET Switches Fixed 400KHz Frequency Cycle‐by‐Cycle Over Current Protection Thermal Shutdown function Wide 4.75V to 20V Operating Input Range Output Adjustable from 1.23V to 18V Programmable Under Voltage Lockout Available in an SOP‐8 with Exposed Pad Package RoHS Compliant and 100% Lead (Pb)‐Free and Green (Halogen Free with Commercial Standard) PC Motherboard, Graphic Card LCD Monitor Set‐Top Boxes DVD‐Video Player Telecom Equipment ADSL Modem Printer and other Peripheral Equipment Microprocessor core supply Networking power supply Pre‐Regulator for Linear Regulators Green Electronics/Appliances Application Circuits C1 10uF/35V CERAMIC x2 OFF ON 8 1 5 IN EN NC GND BS 3 INPUT 4.75V to 21V U1 2 C5 L1 SW FB COMP RS6517‐ADSE D1 4 R1 B340A 7 OUTPUT 3.3V/3A 16.9KΩ 1% C2 6 C6 R3 5.6KΩ 15uH 10nF (Optional) C3 8.2nF R2 10KΩ 1% 22uF/6.3V CERAMIC x2 This integrated circuit can be damaged by ESD. Orister Corporation recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 2/10 Pin Assignments SOP‐8(EP) PACKAGE SOP‐8(EP) PIN 1 SYMBOL NC 2 BS 3 IN 4 SW 5, 9 GND 6 FB 7 COMP 8 EN DESCRIPTION No Connect. Bootstrap. This capacitor (C5) is needed to drive the power switch’s gate above the supply voltage. It is connected between the SW and BS pins to form a floating supply across the power switch driver. The voltage across C5 is about 5V and is supplied by the internal +5V supply when the SW pin voltage is low. Supply Voltage. The RS6517 operates from a 4.75V to 20V unregulated input. C1 is needed to prevent large voltage spikes from appearing at the input. Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high‐side switch. Ground. Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage divider from the output voltage to ground. The feedback threshold is 1.23V. See Setting the Output Voltage. Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required. See Compensation. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. For automatic startup, leave EN unconnected. Ordering Information DEVICE RS6517‐XX Y Z DEVICE CODE XX is nominal output voltage : AD : ADJ Y is package & Pin Assignments designator : SE : SOP‐8(EP) Z is Lead Free designator : P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package G: Green (Halogen Free with Commercial Standard) DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 3/10 Block Diagram Absolute Maximum Ratings Symbol VIN VSW VBS VFB VEN VCOMP TJ TOPR TSTG TLEAD DS‐RS6517‐05 February, 2010 Parameter Supply Voltage SW Pin Voltage Boot Strap Voltage Feedback Voltage Enable/UVLO Voltage Comp Voltage Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range ‐0.3 to +21 ‐0.3 to VIN +0.3 VSW ‐0.3 to VSW +6 ‐0.3 to +6 ‐0.3 to +6 ‐0.3 to +6 150 ‐20 to +85 ‐65 to +150 260 Units V V V V V V o C o C o C o C www.Orister.com Page No. : 4/10 Electrical Characteristics (VIN=12V, TA=25°C, unless otherwise specified) Symbol VIN VFB RDS(ON)1 RDS(ON)2 ISw ILIM GCS AVEA GEA FS FOSC1 DMAX tON ‐ ‐ ‐ ‐ ISD IQ TSD Parameter Input Voltage Feedback Voltage Upper Switch On Resistance Lower Switch On Resistance Upper Switch Leakage Current Limit (NOTE 1) Current Sense Transconductance Output Current to Comp Pin Voltage Error Amplifier Voltage Gain Error Amplifier Transconductance Oscillator Frequency Short Circuit Frequency Maximum Duty Cycle Minimum On Time EN Shutdown Threshold Enable Pull Up Current EN UVLO Threshold Rising EN UVLO Threshold Hysteresis Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown Conditions ‐ 4.75V ≤ VIN ≤ 20V ‐ ‐ VEN = 0V, VSW = 0V ‐ Min. 4.75 1.19 ‐ ‐ ‐ ‐ Typ. ‐ 1.23 0.22 10 ‐ 4.5 Max. 20 1.26 ‐ ‐ 10 ‐ Unit V V Ω Ω uA A ‐ ‐ 1.95 ‐ A/V ‐ ‐ ‐ VFB = 0V VFB = 1.0V ‐ ICC>100uA VEN = 0V VIN Rising ‐ VIN ≤0.4V VEN ≥3V ‐ ‐ 550 ‐ ‐ ‐ ‐ 0.7 ‐ 2.35 ‐ ‐ ‐ ‐ 400 830 400 240 90 100 1.0 1.0 2.50 200 23 1.1 160 ‐ 1150 ‐ ‐ ‐ ‐ 1.3 ‐ 2.65 ‐ 36 1.3 ‐ V/V uA/V KHz KHz % ns V uA V mV uA mA o C Notes: 1. 2. 3. 4. 5. Slope compensation changes current limit above 40% duty cycle. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Devices are ESD sensitive. Handling precaution is recommended. The device is not guaranteed to function outside its operating conditions. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51‐7 thermal measurement standard. DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 5/10 Detail Description The RS6517 is a synchronous high voltage buck converter that can support the input voltage range from 4.75V to 20V and the output current can be up to 3A. Output Voltage Setting The resistive divider allows the FB pin to sense the output voltage as shown in Figure 1. Figure 1. Output Voltage Setting The output voltage is set by an external resistive divider according to the following equation： ⎛ VOUT = VFB ⎜ 1 + ⎝ R1 ⎞ ⎟ R2 ⎠ Where VFB is the feedback reference voltage (1.23V typ.). External Bootstrap Diode Connect a 10nF low ESR ceramic capacitor between the BOOT pin and SW pin. This capacitor provides the gate driver voltage for the high side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and the BOOT pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65%. The bootstrap diode can be a low cost one such as 1N4148 or BAT54. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. VOUT ⎡VOUT ⎤ ⎡ ΔIL = ⎢ × ⎢1 − ⎥ VIN ⎣f × L ⎦ ⎣ ⎤ ⎥ ⎦ Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔIL = 0.2375(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation： VOUT VOUT ⎤ ⎡ ⎤ ⎡ L=⎢ × ⎢1 − ⎥ VIN (MAX ) ⎥⎦ ⎣ f × ΔIL (MAX ) ⎦ ⎣ Inductor Core Selection The inductor type must be selected once the value for L is known. Generally speaking, high efficiency converters can not afford the core loss found in low cost powdered iron cores. So, the more expensive ferrite or mollypermalloy cores will be a better choice. DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 6/10 The selected inductance rather than the core size for a fixed inductor value is the key for actual core loss. As the inductance increases, core losses decrease. Unfortunately, increase of the inductance requires more turns of wire and therefore the copper losses will increase. Ferrite designs are preferred at high switching frequency due to the characteristics of very low core losses. So, design goals can focus on the reduction of copper loss and the saturation prevention. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. The previous situation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy. However, they are usually more expensive than the similar powdered iron inductors. The rule for inductor choice mainly depends on the price vs. size requirement and any radiated field/EMI requirements. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by： IRMS = IOUT (MAX ) ⋅ VOUT VIN ⋅ −1 VIN VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst‐case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, a 10μF x 2 low ESR ceramic capacitor is recommended. For the recommended capacitor, please refer to table 3 for more detail. The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT , is determined by： 1 ⎡ ΔVOUT ≤ ΔIL ⋅ ⎢ESR + 8 fCOUT ⎣ ⎤ ⎥ ⎦ The output ripple will be highest at the maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density than other types. Although Tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost‐sensitive applications for ripple current rating and long term reliability considerations. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 7/10 Output Rectifier Diode The output rectifier diode supplies the current to the inductor when the high‐side switch is off. To reduce losses due to the diode forward voltage and recovery times, use a Schottky diode. Choose a diode whose maximum reverse voltage rating is greater than the maximum input voltage, and whose current rating is greater than the maximum load current. Choose a rectifier who’s maximum reverse voltage rating is greater than the maximum input voltage, and who’s current rating is greater than the maximum load current. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR) also begins to charge or discharge COUT generating a feedback error signal for the regulator to return VOUT to its steady‐state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Table 1. Suggested Inductors for Typical Application Circuit Component Supplier MAGLAYERS SUMIDA TOKO Series MSCDRI‐124‐150M CDRH104R D104C Dimensions (mm) 12 x 12 x 5.0 10.1 x 10 x 3.0 10 x 10 x 4.3 Table 2. Suggested Capacitors for CIN and COUT Component Supplier MURATA TDK MURATA TDK Part No. GRM31CR61E106K C3225X5R1E106K GRM32ER71C226M C3225X5R1C226M Capacitance (uF) 10 10 22 22 Case Size 1206 1206 1200 1200 Table 3. Schottky Rectifier Selection Guide VIN (Max.) 20V 26V Part No. B320 SK33 SS32 B330 B340L SK33 MBRD330 SS33 3A Load Current Vendor Diodes, Inc. (www.diodes.com) Pan Jit International (www.panjit.com.tw) General Semiconductor (www.gensemi.com) Diodes, Inc. (www.diodes.com) Diodes, Inc. (www.diodes.com) Diodes, Inc. (www.diodes.com) On Semiconductor (www.onsemi.com) Fairchild Semiconductor (www.fairchildsemi.com) General Semiconductor (www.gensemi.com) DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 8/10 SOP‐8(EP) Dimension NOTES: A. All linear dimensions are in millimeters (inches). B. This drawing is subject to change without notice. C. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0.15) per end. D. Body width dimension does not include inter‐lead flash or protrusions. Inter‐lead flash and protrusions shall not exceed 0.010 (0.25) per side. E. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the cross‐hatched area. F. Lead dimension is the length of terminal for soldering to a substrate. G. The lead width, as measured 0.014 (0.36) or greater above the seating plane, shall not exceed a maximum value of 0.024 (0.61). H. Lead to lead coplanarity shall be less than 0.004 (0.10) form Seating Plane. I. Falls within JEDEC MS‐012 variation AA. DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 9/10 Soldering Methods for Orister’s Products 1. Storage environment: Temperature=10oC~35oC Humidity=65%±15% 2. Reflow soldering of surface‐mount devices Figure 1: Temperature profile tP Critical Zone TL to TP TP Ramp-up TL tL Temperature Tsmax Tsmin tS Preheat 25 Ramp-down t 25oC to Peak Time Profile Feature Average ramp‐up rate (TL to TP) Sn‐Pb Eutectic Assembly o <3 C/sec Preheat Pb‐Free Assembly <3oC/sec ‐ Temperature Min (Tsmin) 100oC 150oC ‐ Temperature Max (Tsmax) 150oC 200oC 60~120 sec 60~180 sec ‐ Time (min to max) (ts) Tsmax to TL ‐ Ramp‐up Rate o <3 C/sec <3 C/sec Time maintained above: ‐ Temperature (TL) ‐ Time (tL) o 207oC 183 C 60~150 sec Peak Temperature (TP) Time within 5oC of actual Peak Temperature (tP) Ramp‐down Rate Time 25oC to Peak Temperature o o o 60~150 sec 240 C +0/‐5 C 260oC +0/‐5oC 10~30 sec 20~40 sec <6oC/sec <6oC/sec <6 minutes <8 minutes Peak temperature Dipping time 3. Flow (wave) soldering (solder dipping) Products Pb devices. Pb‐Free devices. o o 245 C ±5 C o o 260 C +0/‐5 C 5sec ±1sec 5sec ±1sec DS‐RS6517‐05 February, 2010 www.Orister.com Page No. : 10/10 Important Notice: © Orister Corporation Orister cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an Orister product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. Orister reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in Orister’s terms and conditions of sale, Orister assumes no liability whatsoever, and Orister disclaims any express or implied warranty relating to the sale and/or use of Orister products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent Orister deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. Orister and the Orister logo are trademarks of Orister Corporation. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. DS‐RS6517‐05 February, 2010 www.Orister.com