RICHTEK RT8877C

®
RT8877C
Dual-Output PWM Controller for AMD SVI2 CPU Power
Supply
General Description
Features
The RT8877C is a 4 + 2 phases PWM controller. Moreover,
it is compliant with AMD SVI2 Voltage Regulator
Specification to support both CPU core (VDD) and
Northbridge portion of the CPU (VDDNB). The RT8877C
features CCRCOT (Constant Current Ripple Constant OnTime) with G-NAVP (Green-Native AVP), which is a
Richtek's proprietary topology. G-NAVP makes it an easy
setting controller to meet all AMD AVP (Active Voltage
Positioning) VDD/VDDNB requirements. The droop is
easily programmed by setting the DC gain of the error
amplifier. With proper compensation, the load transient
response can achieve optimized AVP performance. The
controller also uses the interface to issue VOTF Complete
and to send digitally encoded voltage and current values
for the VDD and VDDNB domains. It can operate in single
phase and diode emulation mode and reach up to 90%
efficiency in different modes according to different loading
conditions. The RT8877C provides special purpose offset
capabilities by pin setting. The RT8877C also provides
power good indication, over current indication (OCP_L)
and dual OCP mechanism for AMD SVI2 CPU core and
NB. It also features complete fault protection functions
including over voltage, under voltage and negative voltage.
z
z
z
z
z
z
z
z
z
z
z
z
z
z
4/3/2/1-Phase (VDD) + 2/1/0-Phase (VDDNB) PWM
Controller
G-NAVPTM Topology
Support Dynamic Load Line and Zero Load Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply AMD Power Management
Protocol
Build-in ADC for VOUT and IOUT Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over Current Indicator
52-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
z
z
AMD SVI2 CPU
Desktop Computer
Simplified Application Circuit
RT8877C
OCP_L
PWM1
RT9624A
MOSFET
PWM2
RT9624A
MOSFET
PWM3
RT9624A
MOSFET
SVC
To CPU
SVD
SVT
PWM4
RT9624A
MOSFET
PWMA1
RT9624A
MOSFET
PWMA2
RT9624A
MOSFET
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
VVDD
VVDDNB
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8877C
Ordering Information
Pin Configurations
RT8877C
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT8877CZQW : Product Number
RT8877C
ZQW
YMDNN
YMDNN : Date Code
52 51 50 49 48 47 46 45 44 43 42 41 40
PWM4
TONSET
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
ISEN4N
ISEN4P
VSEN
FB
COMP
1
39
2
38
3
37
4
36
5
35
6
7
34
GND
33
8
32
9
10
31
30
53
11
29
12
28
13
27
PGOOD
PGOODA
EN
ISENA1P
ISENA1N
ISENA2N
ISENA2P
VSENA
FBA
COMPA
IBIAS
VCC
OCP_L
14 15 16 17 18 19 20 21 22 23 24 25 26
RGND
IMON
V064
IMONA
VDDIO
PWROK
SVC
SVD
SVT
OFS
OFSA
SET1
SET2
Package Type
QW : WQFN-52L 6x6 (W-Type)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
PWM3
PWM2
PWM1
NC
NC
NC
DVD
NC
NC
NC
PWMA1
PWMA2
TONSETA
(TOP VIEW)
WQFN-52L 6x6
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
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is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Functional Pin Description
Pin No.
Pin Name
1, 52, 51, 50
Pin Function
PWM4 to PWM1
PWM Outputs for Channel 1, 2, 3 and 4 of VDD Controller.
TONSET
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
5, 4, 8, 9
ISEN1N to ISEN4N
Negative Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
6, 3, 7, 10
ISEN1P to ISEN4P
Positive Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
11
VSEN
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
12
FB
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
13
COMP
14
RGND
15
IMON
16
V064
17
IMONA
18
VDDIO
19
PWROK
20
SVC
Serial VID Clock Input from Processor.
21
SVD
Serial VID Data input from Processor. This pin is a serial data line.
22
SVT
Serial VID Telemetry Input from VR. This pin is a push-pull output.
23
OFS
Over Clocking Offset Setting for the VDD Controller.
24
OFSA
Over Clocking Special Purpose Offset Setting for the VDDNB Controller.
25
SET1
OCP_TDC threshold setting individually for VDD and VDDNB controllers
and also the internal ramp slew rate setting (RSET and RSETA)
individually for VDD and VDDNB controllers
26
SET2
Quick response threshold setting individually for VDD and VDDNB
controllers (QRTH and QRTHA) and also the OCP_TDC trigger delay time
setting for both controllers and over clocking offset enable setting.
27
OCP_L
Over Current Indicator for Dual OCP Mechanism. This pin is an open drain
output.
28
VCC
Controller Power Supply Input. Connect this pin to 5V with an 1μF or
greater ceramic capacitor for decoupling.
2
Error Amplifier Output Pin of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
Fixed 0.64V Reference Voltage Output. This voltage is only used to offset
the output voltage of IMON pin and IMONA pin. Connect a 0.47μF
capacitor from this pin to GND.
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8877C
Pin No.
Pin Name
Pin Function
29
IBIAS
Internal Bias Current Setting. Connect only a 100kΩ resistor from this pin to
GND to generate bias current for internal circuit. Place this resistor as close
to IBIAS pin as possible.
30
COMPA
Error Amplifier Output of the VDDNB Controller.
31
FBA
Output Voltage Feedback Input of VDDNB Controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
32
VSENA
VDDNB Controller Voltage Sense Input. This pin is connected to the terminal
of VDDNB controller output voltage.
37
ISENA2P,
ISENA1P
ISENA2N,
ISENA1N
EN
38
PGOODA
Power Good Indicator for the VDDNB Controller. This pin is an open drain
output.
39
PGOOD
Power Good Indicator for the VDD Controller. This pin is an open drain
output.
TONSETA
VDDNB Controller On-Time Setting. Connect this pin to the converter input
voltage, Vin, through a resistor, RTONNB, to set the on-time of
UGATE_VDDNB and also the output voltage ripple of VDDNB controller.
PWMA2,
PWMA1
PWM Output for Channel 1 and 2 of VDDNB Controller.
33, 36
34, 35
40
41, 42
Positive Current Sense Input of Channel 1 and 2 for VDDNB Controller.
Negative Current Sense Input of Channel 1 and 2 for VDDNB Controller.
Controller Enable pin. A logic high signal enables the controller.
43, 44, 45,
47, 48, 49
46
NC
No Internal Connection.
DVD
53 (Exposed Pad)
GND
External Driver Power Supply Input Voltage Detection Pin.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
PGOODA
OCP_L
PGOOD
VCC
DVD
EN
PWROK
VDDIO
SVT
SVD
SVC
VSEN
VSENA
OFSA
IMONI
IMONAI
OFS
SET2
SET1
Function Block Diagram
UVLO
MUX
GND
ADC
OFS/OFSA
SVI2 Interface
Configuration Registers
Control Logic
IBIAS
RSET/RSETA
From Control Logic
RGND
TONSETA
OCP Threshold
DAC
Soft-Start & Slew
Rate Control
VSETA
ERROR
AMP
+
Offset
Cancellation
+
-
+
PWM
CMPA
PWMA1
-
QRA
+
x2
-
ISENA1N
IBA1
V064
+
0.4
-
RSETA
Current mirror
ISENA2P
+
x2
-
ISENA2N
Current Balance
Average
IBA2
IMONAI
IBA1
IMONA
OCP_TDCA,
OCP_SPIKEA
From Control Logic
+
OCA
To Protection Logic
-
VSENA
VSET
FB
OV/UV/NV
TONSET
ERROR
AMP
+
Offset
Cancellation
+
-
+
PWM1
PWM
CMP
QR
Current mirror
ISEN1P
ISEN1N
+
x1
-
ISEN2P
+
x1
-
PWM3
PWM4
TON
IB1
+
0.4
-
RSET
Current mirror
IB2
Current Balance
Average
IMONI
Current mirror
+
x1
-
PWM2
TON
GEN
-
COMP
ISEN3N
IBA2
DAC
Soft-Start & Slew Rate
Control
ISEN3P
PWMA2
Current mirror
ISENA1P
ISEN2N
TON
GENA
TONA
FBA
COMPA
RGND
Loop Control
Protection Logic
Load Line
/Load Line A
IB1
IB2
IB3
IB4
IB3
Current mirror
ISEN4P
ISEN4N
+
x1
-
IB4
OCP_TDC,
OCP_SPIKE
+
OC
-
VSEN
To Protection Logic
OV/UV/NV
IMON V064
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8877C
Operation
MUX and ADC
Error Amp
The MUX supports the inputs from SET1, SET2, OFS,
OFSA, IMON, IMONA, VSEN, or VSENA. The ADC
converts these analog signals to digital codes for reporting
or performance adjustment.
Error amplifier generates COMP/COMPA signal by the
difference between VSET/VSETA and FB/FBA.
SVI2 Interface
The SVI2 interface uses SVC, SVD, and SVT pins to
communicate with CPU. RT8877C's performance and
behavior can be adjusted by commands sent by CPU or
platform.
Offset cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
PWM CMPx
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TONGENx.
UVLO
TONGEN/TONGENA
The UVLO detects DVD and VCC pin voltages for under
voltage lockout protection and power on reset operation.
This block generates an on-time pulse which high interval
is based on the on-time setting and current balance.
Loop Control Protection Logic
Current Balance
Loop control protection logic detects EN and UVLO signals
to initiate soft-start function and control PGOOD,
PGOODA and OCP_L signals after soft-start is finished.
When OCP event is triggered, the OCP_L pin voltage will
be pulled low.
Per-phase current is sensed and adjusted by adjusting
on-time of each phase to achieve current balance for each
phase.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSETA)
for controller.
Soft-Start and Slew-Rate Control
OC/OV/UV/NV
VSEN/VSENA and output current are sensed for over
current, over voltage, under voltage, and negative voltage
protection.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
This block controls the slew rate of the internal reference
voltage when output voltage changes.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Table 1. Serial VID Codes
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
0000_0000
1.55000
0010_0111
1.30625
0100_1110
1.06250
0111_0101
0.81875
0000_0001
1.54375
0010_1000
1.30000
0100_1111
1.05625
0111_0110
0.81250
0000_0010
1.53750
0010_1001
1.29375
0101_0000
1.05000
0111_0111
0.80625
0000_0011
1.53125
0010_1010
1.28750
0101_0001
1.04375
0111_1000
0.80000
0000_0100
1.52500
0010_1011
1.28125
0101_0010
1.03750
0111_1001
0.79375
0000_0101
1.51875
0010_1100
1.27500
0101_0011
1.03125
0111_1010
0.78750
0000_0110
1.51250
0010_1101
1.26875
0101_0100
1.02500
0111_1011
0.78125
0000_0111
1.50625
0010_1110
1.26250
0101_0101
1.01875
0111_1100
0.77500
0000_1000
1.50000
0010_1111
1.25625
0101_0110
1.01250
0111_1101
0.76875
0000_1001
1.49375
0011_0000
1.25000
0101_0111
1.00625
0111_1110
0.76250
0000_1010
1.48750
0011_0001
1.24375
0101_1000
1.00000
0111_1111
0.75625
0000_1011
1.48125
0011_0010
1.23750
0101_1001
0.99375
1000_0000
0.75000
0000_1100
1.47500
0011_0011
1.23125
0101_1010
0.98750
1000_0001
0.74375
0000_1101
1.46875
0011_0100
1.22500
0101_1011
0.98125
1000_0010
0.73750
0000_1110
1.46250
0011_0101
1.21875
0101_1100
0.97500
1000_0011
0.73125
0000_1111
1.45625
0011_0110
1.21250
0101_1101
0.96875
1000_0100
0.72500
0001_0000
1.45000
0011_0111
1.20625
0101_1110
0.96250
1000_0101
0.71875
0001_0001
1.44375
0011_1000
1.20000
0101_1111
0.95625
1000_0110
0.71250
0001_0010
1.43750
0011_1001
1.19375
0110_0000
0.95000
1000_0111
0.70625
0001_0011
1.43125
0011_1010
1.18750
0110_0001
0.94375
1000_1000
0.70000
0001_0100
1.42500
0011_1011
1.18125
0110_0010
0.93750
1000_1001
0.69375
0001_0101
1.41875
0011_1100
1.17500
0110_0011
0.93125
1000_1010
0.68750
0001_0110
1.41250
0011_1101
1.16875
0110_0100
0.92500
1000_1011
0.68125
0001_0111
1.40625
0011_1110
1.16250
0110_0101
0.91875
1000_1100
0.67500
0001_1000
1.40000
0011_1111
1.15625
0110_0110
0.91250
1000_1101
0.66875
0001_1001
1.39375
0100_0000
1.15000
0110_0111
0.90625
1000_1110
0.66250
0001_1010
1.38750
0100_0001
1.14375
0110_1000
0.90000
1000_1111
0.65625
0001_1011
1.38125
0100_0010
1.13750
0110_1001
0.89375
1001_0000
0.65000
0001_1100
1.37500
0100_0011
1.13125
0110_1010
0.88750
1001_0001
0.64375
0001_1101
1.36875
0100_0100
1.12500
0110_1011
0.88125
1001_0010
0.63750
0001_1110
1.36250
0100_0101
1.11875
0110_1100
0.87500
1001_0011
0.63125
0001_1111
1.35625
0010_0110
1.11250
0110_1101
0.86875
1001_0100
0.62500
0010_0000
1.35000
0100_0111
1.10625
0110_1110
0.86250
1001_0101
0.61875
0010_0001
1.34375
0100_1000
1.10000
0110_1111
0.85625
1001_0110
0.61250
0010_0010
1.33750
0100_1001
1.09375
0111_0000
0.85000
1001_0111
0.60625
0010_0011
1.33125
0100_1010
1.08750
0111_0001
0.84375
1001_1000
0.60000
0010_0100
1.32500
0100_1011
1.08125
0111_0010
0.83750
1001_1001
0.59375
0010_0101
1.31875
0100_1100
1.07500
0111_0011
0.83125
1001_1010
0.58750
0010_0110
1.31250
0100_1101
1.06875
0111_0100
0.82500
1001_1011
0.58125
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8877C
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
1001_1100
0.57500
1011_0101 *
0.41875
1100_1110 *
0.26250
1110_0111*
0.10625
1001_1101
0.56875
1011_0110 *
0.41250
1100_1111 *
0.25625
1110_1000*
0.10000
1001_1110
0.56250
1011_0111 *
0.40625
1101_0000 *
0.25000
1110_1001*
0.09375
1001_1111
0.55625
1011_1000 *
0.40000
1101_0001 *
0.24375
1110_1010*
0.08750
1010_0000
0.55000
1011_1001 *
0.39375
1101_0010 *
0.23750
1110_1011*
0.08125
1010_0001
0.54375
1011_1010 *
0.38750
1101_0011 *
0.23125
1110_1100*
0.07500
1010_0010
0.53750
1011_1011 *
0.38125
1101_0100 *
0.22500
1110_1101*
0.06875
1010_0011
0.53125
1011_1100 *
0.37500
1101_0101 *
0.21875
1110_1110*
0.06250
1010_0100
0.52500
1011_1101 *
0.36875
1101_0110 *
0.21250
1110_1111*
0.05625
1010_0101
0.51875
1011_1110 *
0.36250
1101_0111 *
0.20625
1111_0000*
0.05000
1010_0110
0.51250
1011_1111 *
0.35625
1101_1000 *
0.20000
1111_0001*
0.04375
1010_0111
0.50625
1100_0000 *
0.35000
1101_1001 *
0.19375
1111_0010*
0.03750
1010_1000 *
0.50000
1100_0001 *
0.34375
1101_1010 *
0.18750
1111_0011*
0.03125
1010_1001 *
0.49375
1100_0010 *
0.33750
1101_1011 *
0.18125
1111_0100*
0.02500
1010_1010 *
0.48750
1100_0011 *
0.33125
1101_1100 *
0.17500
1111_0101*
0.01875
1010_1011 *
0.48125
1100_0100 *
0.32500
1101_1101 *
0.16875
1111_0110*
0.01250
1010_1100 *
0.47500
1100_0101 *
0.31875
1101_1110 *
0.16250
1111_0111*
0.00625
1010_1101 *
0.46875
1100_0110 *
0.31250
1101_1111 *
0.15625
1111_1000*
0.00000
1010_1110 *
0.46250
1100_0111 *
0.30625
1110_0000*
0.15000
1111_1001*
OFF
1010_1111 *
0.45625
1100_1000 *
0.30000
1110_0001*
0.14375
1111_1010*
OFF
1011_0000 *
0.45000
1100_1001 *
0.29375
1110_0010*
0.13750
1111_1011*
OFF
1011_0001 *
0.44375
1100_1010 *
0.28750
1110_0011*
0.13125
1111_1100*
OFF
1011_0010 *
0.43750
1100_1011 *
0.28125
1110_0100*
0.12500
1111_1101*
OFF
1011_0011 *
0.43125
1100_1100 *
0.27500
1110_0101*
0.11875
1111_1110*
OFF
1011_0100 *
0.42500
1100_1101 *
0.26875
1110_0110*
0.11250
1111_1111*
OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
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November 2012
RT8877C
Table 2. SET1 Pin Setting for VDD Controller
RSET
SET1 Pin Voltage
Before Current
Injection VSET1 (mV)
34
145%
836
145%
59
130%
861
130%
115%
886
100%
911
135
85%
936
85%
160
70%
961
70%
235
145%
1036
145%
260
130%
1061
130%
115%
1086
100%
1112
335
85%
1137
85%
360
70%
1162
70%
435
145%
1237
145%
460
130%
1262
130%
115%
1287
100%
1312
535
85%
1337
85%
560
70%
1362
70%
636
145%
1437
145%
661
130%
1462
130%
115%
1487
100%
1512
736
85%
1537
85%
761
70%
1562
70%
SET1 Pin Voltage
Before Current
Injection VSET1 (mV)
OCP_TDC
(Respect to
OCP_SPIKE)
85
110
285
310
485
510
686
711
45%
50%
55%
60%
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
OCP_TDC
(Respect to
OCP_SPIKE)
65%
70%
75%
Disable
RSET
115%
100%
115%
100%
115%
100%
115%
100%
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RT8877C
Table 3. SET1 Pin Setting for VDDNB Controller
SET1 Pin Voltage
OCP_TDCA
Difference ΔVSET1
(Respect to
(Before and After
OCP_SPIKEA)
Current Injection) (mV)
RSETA
SET1 Pin Voltage
OCP_TDCA
Difference ΔVSET1
(Respect to
(Before and After
OCP_SPIKEA)
Current Injection) (mV)
RSETA
34
145%
836
145%
59
130%
861
130%
115%
886
100%
911
135
85%
936
85%
160
70%
961
70%
235
145%
1036
145%
260
130%
1061
130%
115%
1086
100%
1112
335
85%
1137
85%
360
70%
1162
70%
435
145%
1237
145%
460
130%
1262
130%
115%
1287
100%
1312
535
85%
1337
85%
560
70%
1362
70%
636
145%
1437
145%
661
130%
1462
130%
115%
1487
100%
1512
736
85%
1537
85%
761
70%
1562
70%
85
110
285
310
485
510
686
711
45%
50%
55%
60%
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
65%
70%
75%
Disable
115%
100%
115%
100%
115%
100%
115%
100%
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Table 4. SET2 Pin Setting
SET2 Pin Voltage
Before Current Injection VSET2 (mV)
QRTH
(for VDD)
OCPTRGDELAY
[1:0]
OCPTRGDELAY
(for VDD/VDDNB)
00
10ms
01
20ms
10
30ms
172
11
40ms
222
00
10ms
01
20ms
10
30ms
373
11
40ms
423
00
10ms
01
20ms
10
30ms
573
11
40ms
623
00
10ms
01
20ms
10
30ms
773
11
40ms
823
00
10ms
01
20ms
10
30ms
974
11
40ms
1024
00
10ms
01
20ms
10
30ms
1174
11
40ms
1224
00
10ms
01
20ms
10
30ms
1375
11
40ms
1425
00
10ms
01
20ms
10
30ms
11
40ms
19
72
122
272
323
473
523
673
723
874
924
1074
1124
1274
1324
1475
1525
1575
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
Disable
35mV
39mV
43mV
47mV
51mV
55mV
60mV
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8877C
Table 5. Quick Response Threshold for VDDNB Controller
SET2 Pin Voltage Difference ΔVSET2
(Before and After Current Injection) (mV)
QRTH [2:0]
QRTHA (for
VDDNB)
19
000
Disable
72
001
35mV
122
010
39mV
011
43mV
100
47mV
272
101
51mV
323
110
55mV
111
59mV
000
Disable
473
001
35mV
523
010
39mV
011
43mV
100
47mV
673
101
51mV
723
110
55mV
773
111
59mV
823
000
Disable
874
001
35mV
924
010
39mV
011
43mV
100
47mV
1074
101
51mV
1124
110
55mV
111
59mV
000
Disable
1274
001
35mV
1324
010
39mV
011
43mV
100
47mV
1475
101
51mV
1525
110
55mV
1575
111
59mV
OFSENABLE
172
0
222
373
423
0
573
1
623
974
0
1024
1174
1224
1375
1425
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
OFSAENABLE
1
1
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
(Note 1)
VCC to GND --------------------------------------------------------------------------------------------------------RGND to GND ------------------------------------------------------------------------------------------------------TONSET to GND ---------------------------------------------------------------------------------------------------Other Pins -----------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WQFN-52L 6x6 ----------------------------------------------------------------------------------------------------- 3.77W
Package Thermal Resistance (Note 2)
WQFN-52L 6x6, θJA ------------------------------------------------------------------------------------------------ 26.5°C/W
WQFN-52L 6x6, θJC ----------------------------------------------------------------------------------------------- 6.5°C/W
Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
z
z
z
−0.3V to 6.5V
−0.3V to 0.3V
−0.3V to 28V
−0.3V to (VCC + 0.3V)
(Note 4)
Supply Voltage, VCC ---------------------------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Input Power Supply
Supply Current
Shutdown Current
Reference and DAC
DC Accuracy
Symbol
Test Conditions
IVCC
ISHDN
EN = 3V, Not Switching
EN = 0V
VFB
VFB = 1.0000 − 1.5500
(No Load, CCM Mode)
VFB = 0.8000 − 1.0000
VFB = 0.3000 − 0.8000
VFB = 0.2500 − 0.3000
RGND Current
RGND Current
Slew Rate
Dynamic VID Slew Rate
Error Amplifier
Input Offset
DC Gain
VEAOFS
ADC
Gain-Bandwidth Product
Output Voltage Range
Maximum Source Current
GBW
CLOAD = 5pF
VCOMP
IEA, SRC
Maximum Sink Current
IEA, SNK
November 2012
Typ
Max
Unit
---
---
12
5
mA
μA
−0.5
0
0.5
%SVID
−5
−8
−80
0
0
0
5
8
80
mV
--
--
200
μA
IRGND
EN = 3V, Not Switching
SR
SetVID Fast
7.5
12
--
mV/μs
RL = 47kΩ
-70
-80
2
--
mV
dB
-0.3
1
10
---
-3.6
--
MHz
V
mA
1
--
--
mA
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
Min
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8877C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
−0.2
--
0.2
mV
Current Mirror Gain for CORE AMIRROR, VDD
97
--
103
%
Current Mirror Gain for NB
AMIRROR, VDDNB
194
--
206
%
Impedance at Negative Input
RISENxN
1
--
--
MΩ
Impedance at Positive Input
Internal Sum Current Sense
DC Gain for CORE
Internal Sum Current Sense
DC Gain for NB
Maximum Source Current
RISENxP
1
--
--
MΩ
Current Sense Amplifier
Input Offset Voltage
VOSCS
Ai, VDD
VDD Controller
--
0.4
--
V/V
Ai, VDDNB
VDDNB Controller
--
0.8
--
V/V
ICS, SRC
0 < VFB < 2.35
100
--
--
μA
Maximum Sink Current
ICS, SNK
0 < VFB < 2.35
12
--
--
μA
Zero Current Detection
Zero Current Detection
Threshold
Ton Setting
VZCD_TH
VZCD_TH = GND − VPHASEx
--
1
--
mV
TONSETx Pin Minimum
Voltage
VTON, MIN
--
0.5
--
V
TONSETx Ton
TON
IRTON = 80μA, VFB = 1.1V
270
305
340
ns
TONSETx Input Current
Range
IRTON
VFB = 1.1V
25
--
280
μA
Minimum TOFF
TOFF
--
250
--
ns
1.97
2
2.03
V
0.61
0.64
0.67
V
800
--
--
μA
IBIAS
IBIAS Pin Voltage
VIBIAS
RIBIAS = 100k
V064
Reference Voltage Output
V064
Sink Current Capability
IV064, SNK
Source Current Capability
IV064, SRC
--
--
100
μA
VFB Limit
VFB, LIMIT
0
--
2.35
V
OFS Update Rate
FOFS
--
50
--
kHz
Board Offset Resolution
ΔVOFS
--
6.25
--
mV
Logic-High
VIH_EN
2
--
--
Logic-Low
VIL_EN
--
--
0.8
Leakage Current of EN
ILEK_EN
−1
--
1
Logic-High
SVC, SVD,
SVT, PWROK Logic-Low
VIH_SVI
Respect to VDDIO
70
--
100
VIL_SVI
Respect to VDDIO
0
--
35
Hysteresis of SVC, SVD,
SVT, PWROK
VHYS_SVI
Respect to VDDIO
10
--
--
V064 = 0.64V
Board OFSx
Logic Inputs
EN Input
Voltage
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
V
μA
%
%
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4
4.2
4.4
V
--
100
--
mV
--
3
--
μs
275
325
375
mV
--
1
--
μs
−375
−325
−275
mV
--
3
--
μs
--
0
--
mV
--
10
--
μA
--
1
--
μs
162
180
198
A
6
--
12
μs
12
--
24
μs
0
--
0.2
V
2
--
--
μs
Protection
Under Voltage Lockout
Threshold
VUVLO
Under Voltage Lockout
Hysteresis
ΔVUVLO
Under Voltage Lockout
Delay
T UVLO
Over Voltage Protection
Threshold
VOVP
Over Voltage Protection
Delay
T OVP
Under Voltage Protection
Threshold
VUVP
Under Voltage Protection
Delay
T UVP
Negative Voltage
Protection Threshold
VNV
Per Phase OCP
Threshold
IOCP_PERPHASE
Delay of Per Phase OCP
T PHOCP
OCP_SPIKE Threshold
IOCP_SPIKE
OCP_SPIKE Action Delay
OCP_TDC Action Delay
VCC Falling edge
VCC Rising above UVLO
Threshold
VSEN Rising above Threshold
VSEN Falling below Threshold
IISENxN Per-Phase OCP
Threshold.
DCR = 0.95mΩ, RSENSE = 680Ω,
RIMON = 10kΩ
T OCPSPIKE
_ACTION_DLY
T OCPTDC
_ACTION_DLY
OCP_L, PGOOD and PGOODA
Output Low Voltage at
OCP_L
VOCP_L
OCP_L Assertion Time
T OCP_L
Output Low Voltage at
PGOOD, PGOODA
VPGOOD,
VPGOODA ,
IPGOOD = 4mA, IPGOODA = 4mA
0
--
0.2
V
PGOOD and PGOODA
Threshold Voltage
VTH_PGOOD
VTH_PGOODA
Respect to VBOOT
--
−300
--
mV
PGOOD and PGOODA
Delay Time
Current Report
Maximum Reported
Current (FFh = OCP)
T PGOOD
T PGOODA
VSEN = VBOOT to
PGOOD/PGOODA High
70
100
130
μs
--
100
--
%IDD_SP
IKE_OCP
Minimum Reported
Current (00h)
--
0
--
%IDD_SP
IKE_OCP
IDDSpike Current
Accuracy
--
--
3
%
IOCP_L = 4mA
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8877C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Maximum Reported Voltage
(0_00h)
--
3.15
--
V
Minimum Reported Voltage
(1_F8h)
--
0
--
V
Voltage Accuracy
−2
--
2
LSB
QRTHx [2:0] = [001]
--
35
--
mV
VQRTH, MAXx QRTHx [2:0] = [111]
--
60
--
mV
PWMx Source Resistance
R PWM_SRC
--
20
--
Ω
PWMx Sink Resistance
R PWM_SNK
--
10
--
Ω
Voltage Report
QR Setting of VDD and VDDNB
Quick Response Threshold
Voltage Setting Range
Minimum Value
Quick Response Threshold
Voltage Setting Range
Maximum Value
VQRTH, MINx
PWM Driving Capability
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Typical Application Circuit
510k
12V
46
300k
0.1µF
DVD
VCC5
1µF
2.2
5V
VDDIO
28
VCC
0.1µF
20k
VCC5
VCC5
VCC5
VCC5
23 OFS
24 OFSA
20k
124k
124k
1k
25 SET1
1.27k
1k
26 SET2
43.2k
470
6.32k
0.1µF
6.32k
VIN
2 TONSET
0.1µF
1
VIN
RTONNB
147k 40
IBIAS
Chip Enable
37
82pF
39pF
10k
32.32k
100
100
270µF
0
0.36μH / 0.72mΩ
VVDDNB
LOAD
2.2
820µF
x3
1µF
510
UGATE PGND
PHASE
0
1
16
11.5k
15
RIMON
2.34k
RNTC
100k
17
RIMONA
2.84k
RNTC
100k
COMPA
31 FBA
14 RGND
COMP
13
42
0
PWMA1
5V
PWM1 50
0.36μH / 0.72mΩ
1µF
510
UGATE PGND
PHASE
0
1
ISENA1P
35 ISENA1N
ISEN1N 5
PWM2
51
5V
VIN
ISENA2P
34 ISENA2N
ISEN2P
ISEN2N
PGND UGATE
PWM
2.2
270µF
0
0.36μH / 0.72mΩ
BOOT
510
1µF
VVDD
820µF
x8
LOAD
0.1µF
2.2
VIN
270µF
0
0.36μH / 0.72mΩ
PHASE
0
1
510
1µF
RSENSE2
560
0
VIN
12V
VCC
UGATE PGND
PHASE
VCC
1µF
PWM
LGATE
EN
RT9624A
1µF
1 PWM4
PWM3 52
5V
PWM
5V
BOOT
PGND UGATE
0.1µF
2.2
270µF
0
0.36μH / 0.72mΩ
PHASE
LGATE
EN
RT9624A
0
1
510
1µF
3.3nF
3.3nF
10
RSENSE4
560
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
November 2012
1
3
4
12V
0.1µF
DS8877C-00
BOOT
LGATE
EN
RT9624A
5V
33
1
0
3.3nF
RSENSEA2
560
510
100
0.36μH / 0.72mΩ
PHASE
12V
3.3nF
1µF
100
270µF
0
RSENSE1
560
VCC
PWMA2
0.1µF
2.2
3.3nF
ISEN1P 6
1µF
41
BOOT
PGND UGATE
PWM
1µF
PWM
LGATE
EN
RT9624A
VSS_SENSE
LGATE
EN
RT9624A
5V
VCC
BOOT
VVDD_SENSE
VIN
1µF
12V
270µF
10k
VCC
36
2.2
82pF
12V
RSENSEA1
560
0.1µF
27pF
FB 12
3.3nF
VIN
13.739k
50.65k
1µF
PWM
LGATE
EN
RT9624A
0.47µF
15.82k
GND 53 (Exposed Pad)
VCC
BOOT
To CPU
30
12V
0.1µF
10k
RIBIAS
29 100k
VSEN 11
VSS_SENSE
VIN
3.3V
10.94k
IMONA
EN
32 VSENA
VVDDNB_SENSE
IMON
TONSETA
0.1µF
4.7k
10k
20
SVC
21
SVD
22
SVT
0.1µF
RTON
150k
1
4.7k
OCP_L 27
19
PWROK
PGOOD 39
PGOODA 38
V064
0
2.2
RT8877C VDDIO 18
9
ISEN4P
ISEN3P 7
ISEN4N
ISEN3N 8
RSENSE3
560
is a registered trademark of Richtek Technology Corporation.
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17
RT8877C
Typical Operating Characteristics
CORE VR Power Off from EN
CORE VR Power On from EN
VVDD
(500mV/Div)
EN
(5V/Div)
VVDD
(500mV/Div)
EN
(5V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
Boot VID = 0.8V
Time (200μs/Div)
Time (200μs/Div)
CORE VR OCP_TDC
CORE VR OCP_SPIKE
I LOAD
(200A/Div)
I LOAD
(250A/Div)
PGOOD
(5V/Div)
OCP_L
(2V/Div)
PGOOD
(5V/Div)
OCP_L
(2V/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
ILOAD = 80A to 160A
ILOAD = 50A to 200A
Time (4ms/Div)
Time (8μs/Div)
CORE VR OVP and NVP
CORE VR UVP
VVDD
(500mV/Div)
PGOOD
(5V/Div)
UGATE1
(50V/Div)
LGATE1
(20V/Div)
VID = 1.1V
Time (20μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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18
Boot VID = 0.8V
VVDD
(500mV/Div)
PGOOD
(5V/Div)
UGATE1
(50V/Div)
LGATE1
(20V/Div)
VID = 1.1V
Time (10μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
VVDD
(500mV/Div)
VVDD
(500mV/Div)
I LOAD
(22A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 0.4V to 1V, ILOAD = 11A
Time (20μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Up
VVDD
(500mV/Div)
VVDD
(500mV/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.1V, ILOAD = 55A
VID = 1V to 1.2V, ILOAD = 55A
Time (20μs/Div)
Time (20μs/Div)
CORE VR Dynamic VID Up
CORE VR Load Transient
VVDD
(500mV/Div)
VVDD
(100mV/Div)
I LOAD
(55A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
I LOAD
(120A/Div)
VID = 1V to 1.4V, ILOAD = 55A
Time (20μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
VID = 1V to 1.06875V, ILOAD = 55A
November 2012
fLOAD = 10kHz, ILOAD = 55A to 150A
Time (4μs/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
19
RT8877C
NB VR Power On from EN
CORE VR Load Transient
V VDDNB
(500mV/Div)
EN
(5V/Div)
VVDD
(100mV/Div)
PGOODA
(5V/Div)
I LOAD
(120A/Div)
fLOAD = 10kHz, ILOAD = 150A to 55A
UGATEA1
(20V/Div)
Boot VID = 0.8V
Time (4μs/Div)
Time (200μs/Div)
NB VR Power Off from EN
NB VR OCP_TDC
I LOAD
(100A/Div)
V VDDNB
(500mV/Div)
EN
(5V/Div)
PGOODA
(5V/Div)
PGOODA
(5V/Div)
OCP_L
(2V/Div)
UGATEA1
(20V/Div)
UGATEA1
(20V/Div)
Boot VID = 0.8V
ILOAD = 30A to 60A
Time (200μs/Div)
Time (4ms/Div)
NB VR OCP_SPIKE
NB VR OVP and NVP
I LOAD
(100A/Div)
PGOODA
(5V/Div)
OCP_L
(2V/Div)
UGATEA1
(20V/Div)
ILOAD = 20A to 80A
Time (8μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
20
V VDDNB
(500mV/Div)
PGOODA
(5V/Div)
UGATEA1
(50V/Div)
LGATEA1
(20V/Div)
VID = 1.1V
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
NB VR Dynamic VID Up
NB VR UVP
V VDDNB
(500mV/Div)
V VDDNB
(500mV/Div)
PGOODA
(5V/Div)
UGATEA1
(50V/Div)
LGATEA1
(20V/Div)
VID = 1.1V
I LOAD
(9A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
Time (10μs/Div)
Time (20μs/Div)
NB VR Dynamic VID Up
NB VR Dynamic VID Up
V VDDNB
(500mV/Div)
V VDDNB
(500mV/Div)
I LOAD
(21A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
I LOAD
(21A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.06875V, ILOAD = 20.5A
VID = 1V to 1.1V, ILOAD = 20.5A
Time (20μs/Div)
Time (20μs/Div)
NB VR Dynamic VID Up
NB VR Dynamic VID Up
V VDDNB
(500mV/Div)
V VDDNB
(500mV/Div)
I LOAD
(21A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
I LOAD
(21A/Div)
SVD
(2V/Div)
SVT
(2V/Div)
VID = 1V to 1.2V, ILOAD = 20.5A
Time (20μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
VID = 0.4V to 1V, ILOAD = 4.1A
November 2012
VID = 1V to 1.4V, ILOAD = 20.5A
Time (20μs/Div)
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21
RT8877C
NB VR Load Transient
NB VR Load Transient
V VDDNB
(100mV/Div)
V VDDNB
(100mV/Div)
I LOAD
(45A/Div)
I LOAD
(45A/Div)
fLOAD = 10kHz, ILOAD = 20A to 60A
fLOAD = 10kHz, ILOAD = 60A to 20A
Time (4μs/Div)
Time (4μs/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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22
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Application Information
Power Ready (POR) Detection
During start-up, the RT8877C will detect the voltage at
the voltage input pins : VCC, EN and DVD. When VCC >
VCC
+
4.2V
DVD
+
2.2V
EN
CMP
POR
+
2V
CMP
CMP
Chip EN
-
higher.
Current
Mirror
2V
+
-
4.2V and VDVD > 2.2V, the IC will recognize the power
state of system to be ready (POR = high) and wait for
enable command at the EN pin. After POR = high and VEN
>2V, the IC will enter start-up sequence for both VDD rail
and VDDNB rail. If the voltage at any voltage input pin
drops below low threshold (POR = low), the IC will enter
power down sequence and all the functions will be
disabled. Normally, connecting system power to the EN
pin and power stage VIN (12V, through a voltage divider)
to the DVD pin is recommended. The SVID will be ready
in 2ms (max) after the chip has been enabled. All the
protection latches (OVP, OCP, UVP) will be cleared only
after POR = low. The condition of VEN = low will not clear
these latches. While VDD and VDDNB regulate, DVD falls
lower than 1.5V. Then IC will shut down immediately until
POR recycle.
accuracy, etc. In other words, the IBIAS pin can only be
connected with a 100kΩ resistor to GND. The resistance
accuracy of this resistor is recommended to be 1% or
+
-
IBIAS
100k
Figure 2. IBIAS Setting
Boot VID
When EN goes high, both VDD and VDDNB output begin
to soft-start to the boot VID in CCM. Table 6 shows the
Boot VID setting. The Boot VID is determined by the SVC
and SVD input states at EN rising edge and it is stored in
the internal register. The digital soft-start circuit ramps up
the reference voltage at a controlled slew rate to reduce
inrush current during start up. When all the output voltages
are above power good threshold (300mV below Boot VID)
at the end of soft-start, the controller asserts power good
after a time delay.
Figure 1. Power Ready (POR) Detection
Table 6. 2-Bit Boot VID Code
Initial Startup VID (Boot VID)
Precise Reference Current Generation
The RT8877C includes complicated analog circuits inside
the controller. The IC needs very precise reference voltage/
current to drive these analog circuits. The IC will auto
generate a 2V voltage source at IBIAS pin, and a 100kΩ
resistor is required to be connected between IBIAS and
analog ground, as shown in Figure 2. Through this
connection, the IC will generate a 20μA current from the
IBIAS pin to analog ground, and this 20μA current will be
mirrored for internal use. Note that other type of connection
or other values of resistance applied at the IBIAS pin may
cause functional failure, such as slew rate control, OFS
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
SVC
SVD
VDD/VDDNB Output Voltage (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
Start-Up Sequence
After EN goes high, the RT8877C starts up and operates
according to the initial settings. Figure 3 shows the
simplified sequence timing diagram. The detailed operation
is described in the following.
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23
RT8877C
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
VCC
SVID
Send
Byte
SVC
SVID
Send
Byte
SVD
VOTF
Complete
VOTF
Complete
SVT
EN
PWROK
CCM
VVDD/
Boot VID
CCM
VID
CCM
Boot VID
CCM CCM
VID
CCM
CCM
VVDDNB
PGOOD/
PGOODA
Figure 3. Simplified Sequence Timing Diagram
Description of Figure 3 :
T0 : The RT8877C waits for VCC POR.
T1 : The SVC pin and SVD pin set the Boot VID. Boot VID
is latched at EN rising edge. SVT is driven high by the
RT8877C.
T2 : The enable signal goes high and all output voltages
ramp up to the Boot VID in CCM. The soft-start slew rate
is 3mV/μs.
T3 : All output voltages are within the regulation limits and
the PGOOD and PGOODA signal goes high.
T4 : The PWROK pin goes high and the SVI2 interface
starts running. The RT8877C waits for SVID command
from processor.
T5 : A valid SVID command transaction occurs between
the processor and the RT8877C.
T7 : The PWROK pin goes low and the SVI2 interface
stops running. All output voltages go back to the boot VID
in CCM.
T8 : The PWROK pin goes high again and the SVI2
interface starts running. The RT8877C waits for SVID
command from processor.
T9 : A valid SVID command transaction occurs between
the processor and the RT8877C.
T10 : The RT8877C starts VID-on-the-fly transition
according to the received SVID command and send a
VOTF Complete if the VID reaches target VID.
T11 : The enable signal goes low and all output voltages
enter soft-shutdown mode.
T6 : The RT8877C starts VOTF (VID-on-the-fly) transition
according to the received SVID command and send a
VOTF Complete if the VID reaches target VID.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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24
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Power Down Sequence
SVI2 Wire Protocol
If the voltage at EN pin falls below the enable falling
threshold, the controller is disabled. The voltage at the
PGOOD and PGOODA pin will immediately go low at the
loss of enable signal at the EN pin and the controller
executes soft-shutdown operation. The internal digital
circuit ramps down the reference voltage at the same slew
rate as that of in soft-start, making VDD and VDDNB output
voltages gradually decrease in CCM. Each of the controller
channels stops switching when the voltage at the voltage
sense pin VSEN/VSENA, cross about 0.2V. The Boot VID
information stored in the internal register is cleared at
POR. This event forces the RT8877C to check the SVC
and SVD inputs for a new boot VID when the EN voltage
goes high again.
The RT8877C complies with AMD's Voltage Regulator
Specification, which defines the Serial VID Interface 2
(SVI2) protocol. With SVI2 protocol, the processor directly
controls the reference voltage level of each individual
controller channel and determines which controller
operates in power saving mode. The SVI2 interface is a
three wire bus that connects a single master to one or
above slaves. The master initiates and terminates SVI2
transactions and drives the clock, SVC, and the data, SVD,
during a transaction. The slave drives the telemetry, SVT
during a transaction. The AMD processor is always the
master. The voltage regulator controller (RT8877C) is
always the slave. The RT8877C receives the SVID code
and acts accordingly. The SVI protocol supports 20MHz
high speed mode I2C, which is based on SVD data packet.
Table 7 shows the SVD data packet. A SVD packet
consists of a “Start” signal, three data bytes after each
byte, and a “Stop” signal. The 8-bit serial VID codes are
listed in Table1. After the RT8877C has received the stop
sequence, it decodes the received serial VID code and
executes the command. The controller has the ability to
sample and report voltage and current for the VDD and
VDDNB domains. The controller reports this telemetry
serially over the SVT wire which is clocked by the
processor driven SVC. A bit TFN at SVD packet along
with the VDD and VDDNB domain selector bits are used
by the processor to change the telemetry functionality.
The telemetry bit definition is listed in Figure 4. The detailed
SVI2 specification is outlined in the AMD Voltage Regulator
and Voltage Regulator Module (VRM) and Serial VID
Interface 2.0 (SVI2) Specification.
PGOOD and PGOODA
The PGOOD and PGOODA are open-drain logic outputs.
The 2 pins provide the power good signal when VDD and
VDDNB output voltage are within the regulation limits and
no protection is triggered. These pins are typically tied to
3.3V or 5V power source through a pull-high resistor. During
shutdown state (EN = low) and the soft-start period, the
PGOOD and PGOODA voltages are pulled low. After a
successful soft-start and VDD and VDDNB output voltages
are within the regulation limits, the PGOOD and PGOODA
are released high individually.
The voltages at the PGOOD pin and PGOODA pin are
pulled low individually during normal operation when any
of the following events occurs: over voltage protection,
under voltage protection, over current protection, and logic
low EN voltage. If one rail triggers protection, another rail's
PGOOD will be pull low after 5μs delay.
Table 7. SVD Data Packet
Bit Time
Description
1:5
8
Always 11000b
VDD domain selector bit, if set then the following two data bytes contain the VID for VDD, the
PSI state for VDD, and the load line slope trim and offset trim state for VDD.
VDDNB domain selector bit, if set then the following two data bytes contain the VID for VDDNB,
the PSI state for VDDNB, and the load line slope trim and offset trim state for VDDNB.
Always 0b
10
PSI0_L
6
7
11 : 17
19
VID Code bits [7:1]
VID Code bit [0]
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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November 2012
is a registered trademark of Richtek Technology Corporation.
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25
RT8877C
Bit Time
Description
20
PSI1_L
21
TFN (Telemetry Functionality)
22 : 24
Load Line Slope Trim [2:0]
25 : 26
Offset Trim [1:0]
Voltage and Current
Mode Selection
Bit Time…… START
1
2
3
VDDNB Voltage Bit in Voltage Only Mode;
Current Bit in Voltage and Current Mode
VDD Voltage Bits
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
STOP
SVC
SVT
Figure 4. Telemetry Bit Definition
PWROK and SVI2 Operation
VID-on-the-Fly Transition
The PWROK pin is an input pin, which is connected to
the global power good signal from the platform. Logic high
at this pin enables the SVI2 interface, allowing data
transaction between processor and the RT8877C. Once
the RT8877C receives a valid SVID code, it decodes the
information from processor to determine which output
plane is going to move to the target VID. The internal DAC
then steps the reference voltage in a controlled slew rate,
making the output voltage shift to the required new VID.
Depending on the SVID code, more than one controller
channels can be targeted simultaneously in the VID
transition. For example, VDD and VDDNB voltages can
ramp up/down at the same time.
After the RT8877C has received a valid SVID code, it enters
CCM mode and executes the VID-on-the-fly transition by
stepping up/down the reference voltage of the required
controller channel(s) in a controlled slew rate, hence
allowing the output voltage(s) to ramp up/down to the target
VID. The output voltage slew rate during the VID-on-thefly transition is faster than that in a soft-start/soft-shutdown
operation. If the new VID level is higher than the current
VID level, the controller begins stepping up the reference
voltage with a typical slew rate of 12.5mV/μs upward to
the target VID level. If the new level is lower than the current
VID level, the controller begins stepping down the reference
voltage with a typical slew rate of −12.5mV/μs downward
to the target VID level.
If the PWROK input goes low during normal operation,
the SVI2 protocol stops running. The RT8877C
immediately drives SVT high and modifies all output
voltages back to the boot VID, which is stored in the internal
register right after the controller is enabled. The controller
does not read SVD and SVC inputs after the loss of
PWROK. If the PWROK input goes high again, the SVI2
protocol resumes running. The RT8877C then waits to
decode the SVID command from processor for a new VID
and acts as previously described. The SVI2 protocol is
only running when the PWROK input goes high after the
voltage at the EN pin goes high; otherwise, the RT8877C
will not soft-start due to incorrect signal sequence.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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26
During the VID-on-the-fly transition, the RT8877C will force
the controller channel to operate in CCM mode. If the
controller channel operates in the power-saving mode prior
to the VID-on-the-fly transition, it will be in CCM mode
during the transition and then back to the power saving
mode at the end of the transition. The voltage at the
PGOOD pin and PGOODA pin will keep high during the
VID-on-the-fly transition. The RT8877C checks the output
voltage for voltage-related protections and send a VOTF
complete at the end of VID-on-the-fly transition. In the
event of receiving a VID off code, the RT8877C steps the
reference voltage of required controller channel down to
zero, hence making the required output voltage decrease
to zero. The voltage at the PGOOD pin and PGOODA pin
will remain high since the VID code is valid.
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
Operation Mode Transition
SET1 and SET2 Pin Setting
The RT8877C supports operation mode transition function
in VDD and VDDNB controller for the PSI[x]_L and
command from AMD processor. Referring to Table 7, the
PSI[x]_L bit in the SVI2 protocol controls the operating
mode of the RT8877C controller channels. The default
operation mode of VDD and VDDNB controller is CCM.
When the VDD controller is in full-phase configuration and
receives PSI0_L = 0 and PSI1_L = 1, the VDD controller
will keep full-phase operation. When the VDD controller
receives PSI0_L = 0 and PSI1_L = 0, the VDD controller
takes phase shedding operation and enters diode
emulation mode. In reverse, the VDD controller goes back
to full-phase operation in CCM upon receiving PSI0_L = 1
and PSI1_L = 0 or 1, or PSI0_L = 0 and PSI1_L = 1.
When the VDDNB controller receives PSI0_L = 0 and
PSI1_L = 1, it enters single-phase CCM, when the VDDNB
controller receives PSI0_L = 0 and PSI1_L = 0, it enters
single-phase diode emulation mode. When the VDDNB
controller goes back to full-phase CCM operation after
receiving PSI0_L = 1 and PSI1_L = 0 or 1.
The RT8877C provides SET1 pin for platform users to set
the VDD and VDDNB controller OCP_TDC threshold and
internal ramp amplitude (RSET & RSETA), SET2 pin to
set VDD and VDDNB controller OCP trigger delay
(OCPTRGDELAY) and quick response threshold (QRTH
& QRTHA). To set these pin, platform designers should
use resistive voltage divider on these pins, refer to Figure
6 and Figure 7. The voltage at SET1 and SET2 pin is
ΔVSET1 = 40μA ×
ROCPTDC,U × ROCPTDC,D
ROCPTDC,U + ROCPTDC,D
(3)
Differential Remote Sense Setting
ΔVSET2 = 40μA ×
RQRTH,U × RQRTH,D
RQRTH,U + RQRTH,D
(4)
The VDD and VDDNB controllers have differential, remotesense inputs to eliminate the effects of voltage drops along
the PC board traces, processor internal power routes and
socket contacts. The processor contains on-die sense
pins, VDD_SENSE, VDDNB_SENSE and VSS_SENSE.
Connect RGND to VSS_SENSE. For VDD controller,
connect FB to VDD_SENSE with a resistor to build the
negative input path of the error amplifier. Connect FB_NB
to VDDNB_SENSE with a resistor using the same way in
VDD controller. Connect VSS_SENSE to RGND using
separate trace as shown in Figure 5. The precision
reference voltages refer to RGND for accurate remote
sensing.
Processor
VDD_SENSE VDDNB_SENSE
VDD
Controller
FB
FB_NB
RGND
RGND_NB
VSET1 = VCC ×
ROCPTDC,D
ROCPTDC,U + ROCPTDC,D
(1)
VSET2 = VCC ×
RQRTH,D
RQRTH,U + RQRTH,D
(2)
The ADC monitors and decodes the voltage at this pin
only once after power up. After ADC decoding (only once),
a 40μA current (when VCC = 5V) will be generated at the
SET1 and SET2 pin for internal use. That is the voltage at
SET1 and SET2 pin is
From equation (1) to equation (4) and Table 2 to Table 5,
platform users can set the OCP_TDC threshold, OCP
trigger delay, internal ramp amplitude and quick response
threshold for VDD and VDDNB controller.
RSET = VOCPTDC,DIV
OCPTDC
= VOCPTDC,DIV
40µA
(VCC = 5V)
VCC
ADC
2.24V
VOCPTDC,DIV VOCPTDC,DIV
VOCPTDC
Register
VOCPTDC,2
ROCPTDC,U
SET1
ROCPTDC,D
RT8877C
Figure 6. OCP_TDC/RSET Setting
VDD NB
Controller
VSS_SENSE
Figure 5. Differential Remote Voltage Sense Connection
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November 2012
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27
RT8877C
OCPTRGDELAY = VQRTH,DIV
QRTH = VQRTH,DIV
AVP. A near-DC offset canceling is added to the output of
EA to eliminate the inherent output offset of finite gain
peak current mode controller.
40µA
(VCC = 5V)
VIN
VCC
VQRTH,DIV
VQRTH
Register
VQRTH,2
SET2
CCRCOT
PWM
Logic
RQRTH,U
RQRTH,D
RT8877C
Figure 7. QRTH/OCPTRGDELAY Setting
+
CMP
-
VQRTH,DIV
2.24V
COMP2
ADC
0.4
x1
VCS
+
-
Loop Control
The VDD controller adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The output voltage, VVDD will decrease
with increasing output load current. The control loop
consists of PWM modulators with power stages, current
sense amplifiers and an error amplifier as shown in Figure
8.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMP voltage also
increases and induces VVDD to decrease, thus achieving
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28
RX
EA
+
CX
RC
C
ISENxP
ISENxN
RCSx
RIMON
IMON
+
PWM controller. Pulling ISEN4N to VCC programs a 3phase operation, pulling ISEN3N to VCC programs a 2phase operation, and pulling ISEN2N to VCC programs a
1-phase operation. At EN rising edge, VDD controller
detects whether the voltages of ISEN2N, ISEN3N and
ISEN4N are higher than “VCC − 0.5V” respectively to
decide how many phases should be active. Phase
selection is only active during POR. When POR = high,
the number of active phases is determined and latched.
The unused ISENxP pins are recommended to be
connected to VCC and unused PWM pins can be left
floating.
Driver
VREF
VDD Controller
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Normally, the VDD controller operates as a 4-phase
HS_FET
VVDD
L RSENSE
LS_FET
Offset
Canceling
Active Phase Determination : Before POR
PWMx
C2
R2
COMP
FB
RGND
C1
R1
VVDD_SENSE
VSS_SENSE
VDAC,VDD
Figure 8. VDD Controller : Simplified Schematic for
Droop and Remote Sense in CCM
Droop Setting
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 9. This target is
to have
VVDD = VDAC, VDD − ILOAD x RDROOP
(5)
Then solving the switching condition VCOMP2 = VCS in
Figure 8 yields the desired error amplifier gain as
GI
(6)
A V = R2 =
R1 RDROOP
GI =
RSENSE
× RIMON × 4
RCSx
10
(7)
where GI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RDROOP is the equivalent load line resistance as well as
the desired static output impedance.
VVDD
AV2 > AV1
AV2
AV1
0
Load Current
Figure 9. VDD Controller : Error Amplifier gain (AV)
Influence on VVDD Accuracy
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DS8877C-00
November 2012
RT8877C
Loop Compensation
Optimized compensation of the VDD controller allows for
best possible load step response of the regulator's output.
A type-I compensator with one pole and one zero is
adequate for proper compensation. Figure 10 shows the
compensation circuit. Previous design procedure shows
how to select the resistive feedback components for the
error amplifier gain. Next, C1 and C2 must be calculated
for compensation. The target is to achieve constant
resistive output impedance over the widest possible
frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP =
1
2 π × C × RC
(8)
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C x RC
(9)
C2 =
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
1
C1 =
(10)
R1× π × fSW
COMP
C1
R2
R1
FB
+
EA
+
C2
RGND
VVDD_SENSE
VSS_SENSE
VDAC
Figure 10. VDD Controller : Compensation Circuit
TON Setting
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
11 shows the On-Time setting Circuit. Connect a resistor
(RTON) between VIN and TONSET to set the on-time of
UGATE :
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
−12
24.4 × 10
× RTON (11)
VIN − VDAC
where tON is the UGATE turn on period, VIN is Input voltage
of the VDD controller, and VDAC is the DAC voltage.
tON (0.5V ≤ VDAC < 1.8V) =
When VDAC is larger than 1.8V, the equivalent switching
frequency may be over 500kHz, and this too fast switching
frequency is unacceptable. Therefore, the VDD controller
implements a pseudo constant frequency technology to
avoid this disadvantage of CCRCOT topology. When VDAC
is larger than 1.8V, the on-time equation will be modified
to :
−12
13.55 × 10
× RTON × VDAC (12)
tON (VDAC ≥ 1.8V) =
VIN − VDAC
On-time translates only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in external HS-FET.
Also, the dead-time effect increases the effective on-time,
which in turn reduces the switching frequency. It occurs
only in CCM and during dynamic output voltage transitions.
When the inductor current reverses at light or negative
load currents, with reversed inductor current, the phase
goes high earlier than normal, extending the on-time by a
period equal to the HS-FET rising dead time.
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
1
fS(MAX) (kHz) =
x
TON − THS−Delay
VDAC(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS −FET + DCRL − RDROOP ⎤⎦
VIN(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦
(13)
Where fS(MAX) is the maximum switching frequency, tHSDELAY is the turn-on delay of HS-FET, VDAC(MAX) is the
Maximum VDAC of application, VIN(MAX) is the Maximum
application Input voltage, ILOAD(MAX) is the maximum load
of application, RON_LS-FET is the Low side FET RDS(ON),
RON_HS-FET is the High side FET RDS(ON) , DCRL is the
equivalent resistance of the inductor, and RDROOP is the
load line setting.
CCRCOT
On-Time
Computer
TONSET
VDAC
RTON
R1
VIN
C1
On-Time
Figure 11. VDD Controller : On-Time Setting with RC filter
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RT8877C
Current Sense Setting
Per-Phase Over Current Protection
The current sense topology of the VDD controller is
continuous inductor current sensing. Therefore, the
controller has less noise sensitive. Low offset amplifiers
are used for current balance, loop control and over current
detection. The ISENxP and ISENxN pins denote the
positive and negative input of the current sense amplifier
of each phase.
The VDD controller provides over current protection in each
phase. For VDD controller in four-phase configuration, either
phase can trigger Per-Phase Over Current Protection
(PHOCP).
Users can either use a current sense resistor or the
inductor's DCRL for current sensing. Using the inductor's
DCRL allows higher efficiency as shown in Figure 12.
IL
L
RX
ISENxN
+
-
10µA
Current Mirror
ISENAxN
DCRL
CX
RCSx
Figure 12. VDD Controller : Lossless Inductor Sensing
In order to optimize transient performance, RX and CX must
be set according to the equation below :
L = R ×C
(14)
X
X
DCRL
Then the proportion between the phase current, IL, and
the sensed current, ISENxN, is driven by the value of the
effective sense resistance, RCSx, and the DCRL of the
inductor. The resistance value of RCSx is limited by the
internal circuitry. The recommended value is from 500Ω
to 1.2kΩ.
DCRL
(15)
ISENxN = IL ×
RCSx
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement and the recovery is too
fast causing a ring back. Vice versa, with a resistance too
large the output voltage transient has only a small initial
dip with a slow recovery.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductor equivalent resistance sensing method.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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30
1 ×I
8 SENAxN
PHOCP trigger
VVDD
ISENxP
ISENxN
The VDD controller senses each phase inductor current
IL, and PHOCP comparator compares sensed current with
PHOCP threshold current, as shown in Figure 13.
Figure 13. VDD Controller : Per-Phase OCP Setting
The resistor RCSx determines PHOCP threshold.
DCRL 1
× = 10μA
RCSx 8
IL,PERPHASE(MAX) × DCRL
RCSx =
8 × 10μA
(16)
IL,PERPHASE(MAX) ×
(17)
The controller will turn off all high side/low side MOSFETs
to protect CPU if the per-phase over current protection is
triggered.
Current Balance
The VDD controller implements internal current balance
mechanism in the current loop. The VDD controller senses
and compares per-phase current signal with average
current. If the sensed current of any particular phase is
larger than average current, the on-time of this phase will
be adjusted to be shorter.
Initial Offset and External Offset (Over Clocking
Offset Function)
The VDD controller features over clocking offset function
which provides the possibility of wide range off set of output
voltage. The initial offset function can be implemented
through the SVI interface. When the OFS pin voltage
< 0.3V at EN rising edge, the initial offset is disabled. The
external offset function can be implemented by SET2 pin
setting. For example, referring to Table 8, when the both
rail external offset functions are enabled, the output voltage
is :
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DS8877C-00
November 2012
RT8877C
VVDD = VDAC − ILOAD x RDROOP + VExternal _ OFS
+ VInitial _ OFS
Current Monitoring and Current Reporting
(18)
VInitial_OFS is the initial offset voltage set by SVI interface,
and the external offset voltage, VExternal_OFS is set by
supplying a voltage into OFS pin.
It can be calculated as below :
VExternal _ OFS = VOFS − 1.2V
(19)
If supplying 1.3V at OFS pin , it will achieve 100mV offset
at the output. Connecting a filter capacitor between the
OFS pin and GND is necessary. Designers can design
the offset slew rate by properly setting the filter bandwidth.
Table 8. External Offset Function Setting for VDD
and VDDNB Controller
Core_
NB_
OFFSET_ OFFSET_
Description
EN
EN
0
0
Disable external offset function.
NB rail external offset is set by
0
1
OFS pin voltage.
1
1
0
Core rail external offset is set
by OFSA pin voltage.
1
Core rail external offset is set
by OFS pin voltage, and NB rail
external offset is set by OFSA
pin voltage.
Dynamic VID Enhancement
DCRL
VIMON = IL,SUM ×
× RIMON + 0.64
RCSx
(20)
Where IL is the phase current, RCSx is the effective sense
resistance, and RIMON is the current monitor current setting
resistor. Note that the IMON pin cannot be monitored.
The ADC circuit of the VDD controller monitors the voltage
variation at the IMON pin from 0V to 3.19375V, and this
voltage is decoded into digital format and stored into
Output_Current register. The ADC divides 3.19375V into
511 levels, so LSB = 3.19375V / 511 = 6.25mV.
Quick Response
The VDD controller utilizes a quick response feature to
support heavy load current demand during instantaneous
load transient. The VDD controller monitors the current of
the VVDD_SENSE, and this current is mirrored to internal
quick response circuit. At steady state, this mirrored
current will not trigger a quick response. When the
VVDD_SENSE voltage drops abruptly due to load apply
transient, the mirrored current flowing into quick response
circuit will also increase instantaneously.
The QR threshold setting for VDD controller refers to Table
4.
QRTH
QR Pulse
Generation
Circuit
+
CMP
-
+
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The RT8877C will hold the inductor current
to hold the load-line during a dynamic VID event. The VDD
controller will always enter four-phase configuration when
VDD controller receives dynamic VID up and VDD controller
will hold the operating state when VDD controller receives
dynamic VID down.
The VDD controller provides current monitoring function
via inductor current sensing. In G-NAVPTM technology,
the output voltage is dependent on output current, and
the current monitoring function is achieved by this
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and
mirrored to IMON pin. The resistor connected to IMON
pin determines voltage of the IMON output.
VVDD_SENSE
Ramp Amplitude Adjust
When the VDD controller takes phase shedding operation
and enters diode emulation mode, the internal ramp of
VDD controller will be modified for the reason of stability.
In case of smooth transition into DEM, the CCM ramp
amplitude should be designed properly. The RT8877C
provides SET1 pin for platform users to set the ramp
amplitude of the VDD controller in CCM.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
Figure 14. VDD Controller : Quick Response Triggering
Circuit
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The pulse
width of quick response is almost the same with tON.
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RT8877C
After generating a quick response pulse, the pulse is then
applied to the on-time generating circuit, and all the active
phases' on-time will be overridden by the quick response
pulse.
Over Current Protection
The RT8877C has dual OCP mechanism. The dual OCP
mechanism has two types of thresholds. The first type,
referred to as OCP-TDC, is a time and current based
threshold. OCP-TDC should trip when the average output
current exceeds TDC by some percentage and for a period
of time. This period of time is referred to as the trigger
delay. The second type, referred to as OCP-SPIKE, is a
current based threshold. OCP-SPIKE should trip when
the cycle-by-cycle output current exceeds IDDSPIKE by
some percentage. If either mechanism trips, then the VDD
controller asserts OCP_L and delays any further action.
This delay is called an action delay. Refer to action delay
time. After the action delay has expired and the VDD
controller has allowed its current sense filter to settle out
and the current has not decreased below the threshold,
then the VDD controller will turn off both high side
MOSFETs and low side MOSFETs of all channels.
Users can set OCP-SPIKE threshold, IL,SUM (SPIKE), by the
current monitor resistor RIMON of the following equation :
R
IL,SUM (SPIKE) = 3.19375 − 0.64 × CSx
(21)
DCRL
RIMON
And set the OCP-TDC threshold, IL(TDC), refer to some
percentage of OCP-SPIKE through Table 2.
Over Voltage Protection (OVP)
The over voltage protection circuit of the VDD controller
monitors the output voltage via the VSEN pin after POR.
When VID is lower than 0.9V, once VSEN exceeds “0.9V
+ 325mV”, OVP is triggered and latched. When VID is
larger than 0.9V, once VSEN exceeds the internal reference
by 325mV, OVP is triggered and latched. The VDD
controller will try to turn on low side MOSFETs and turn
off high side MOSFETs of all active phases of the VDD
controller to protect the CPU. When OVP is triggered by
one rail, the other rail will also enter soft shut down
sequence. A 1μs delay is used in OVP detection circuit
to prevent false trigger.
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32
Negative Voltage Protection (NVP)
During OVP latch state, the VDD controller also monitors
the VSEN pin for negative voltage protection. Since the
OVP latch continuously turns on all low side MOSFETs
of the VDD controller, the VDD controller may suffer
negative output voltage. As a consequence, when the VSEN
voltage drops below 0V after triggering OVP, the VDD
controller will trigger NVP to turn off all low side MOSFETs
of the VDD controller while the high side MOSFETs
remains off. After triggering NVP, if the output voltage rises
above 0V, the OVP latch will restart to turn on all low side
MOSFETs. The NVP function will be active only after OVP
is triggered.
Under Voltage Protection (UVP)
The VDD controller implements under voltage protection
of VOUT,VDD. If VSEN is less than the internal reference by
325mV, the VDD controller will trigger UVP latch. The UVP
latch will turn off both high side and low side MOSFETs.
When UVP is triggered by one rail, the other rail will also
enter soft shut down sequence. A 3μs delay is used in
UVP detection circuit to prevent false trigger.
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC or DVD
pin drops below POR threshold, the VDD controller will
trigger UVLO. The UVLO protection forces all high side
MOSFETs and low side MOSFETs off by shutting down
internal PWM logic drivers. A 3μs delay is used in UVLO
detection circuit to prevent false trigger.
VDDNB Controller
VDDNB Controller Disable
The VDDNB controller can be disabled by connecting
ISENA1N to a voltage higher than VCC. If not in use,
ISENAxP is recommended to be connected to VCC, while
PWMAx is left floating. When VDDNB controller is disabled,
all SVID commands related to VDDNB controller will be
rejected.
Loop Control
The VDDNB controller adopts Richtek's proprietary GNAVPTM topology. G-NAVPTM is based on the finite gain
peak current mode with CCRCOT (Constant Current Ripple
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DS8877C-00
November 2012
RT8877C
Constant On-Time) topology. The output voltage, VVDDNB
will decrease with increasing output load current. The
control loop consists of PWM modulators with power
stages, current sense amplifiers and an error amplifier as
shown in Figure 15.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMPA voltage also
increases and induces VVDDNB to decrease, thus achieving
AVP. A near-DC offset canceling is added to the output of
EA to eliminate the inherent output offset of finite gain
peak current mode controller.
VIN
COMP2
+
CMP
-
CCRCOT
PWMAx
PWM
Logic
HS_FET
VVDDNB
L RSENSE
Driver
RX
LS_FET
0.4
x2
VCS
+
-
CX
RC
C
ISENAxP
ISENAxN
RCSx
IMONA RIMONA
Offset
Canceling
VREF
+
COMPA
FBA
EA
RGND
+
VDAC, VDDNB
C2
R2
C1
R1
VVDDNB_SENSE
VSS_SENSE
Figure 15. VDDNB Controller : Simplified Schematic for
Droop and Remote Sense in CCM
Droop Setting
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 16. This target
is to have
VVDDNB = VDAC,VDDNB − ILOAD x RDROOP
(22)
Then solving the switching condition VCOMP2 = VCS in
Figure 17 yields the desired error amplifier gain as
GI
A V = R2 =
R1 RDROOP
VVDDNB
AV2
AV1
0
Loop Compensation
Optimized compensation of the VDDNB controller allows
for best possible load step response of the regulator’s
output. A type-I compensator with one pole and one zero
is adequate for proper compensation. Figure 17 shows
the compensation circuit. Previous design procedure
shows how to select the resistive feedback components
for the error amplifier gain. Next, C1 and C2 must be
calculated for compensation. The target is to achieve
constant resistive output impedance over the widest
possible frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP =
1
2 π × C × RC
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C x RC
(26)
C2 =
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
1
C1 =
(27)
R1× π × fSW
COMPA
EA
+
C2
C1
R2
R1
FBA
+
November 2012
(25)
(23)
RSENSE
(24)
× RIMON × 8
RCSx
10
where GI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RDROOP is the equivalent load line resistance as well as
the desired static output impedance.
DS8877C-00
Load Current
Figure 16. VDDNB Controller : Error Amplifier gain (AV)
Influence on VVDDNB Accuracy
where GI =
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
AV2 > AV1
RGND
VVDDNB_SENSE
VSS_SENSE
VDAC,VDDNB
Figure 17. VDDNB Controller : Compensation Circuit
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33
RT8877C
TON Setting
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
18 shows the On-Time setting Circuit. Connect a resistor
(RTON) between VIN and TONSETA to set the on-time of
UGATE :
24.4 × 10−12 × RTON
(28)
tON (0.5V ≤ VDAC < 1.8V) =
VIN − VDAC,VDDNB
where tON is the UGATE turn on period, VIN is Input voltage
of the VDDNB controller, and VDAC,VDDNB is the DAC
voltage.
When VDAC,VDDNB is larger than 1.8V, the equivalent
switching frequency may be over 500kHz, and this too
fast switching frequency is unacceptable. Therefore, the
VDDNB controller implements a pseudo constant
frequency technology to avoid this disadvantage of
CCRCOT topology. When VDAC,VDDNB is larger than 1.8V,
the on-time equation will be modified to :
tON (VDAC ≥ 1.8V)
−12
13.55 × 10
× RTON × VDAC,VDDNB
(29)
VIN − VDAC,VDDNB
On-time translates only roughly to switching frequencies.
=
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in external HS-FET.
Also, the dead-time effect increases the effective on-time,
which in turn reduces the switching frequency. It occurs
only in CCM and during dynamic output voltage transitions
When the inductor current reverses at light or negative
load currents, with reversed inductor current, the phase
goes high earlier than normal, extending the on-time by a
period equal to the HS-FET rising dead time.
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
fS(MAX) (kHz) =
1
x
TON − THS−Delay
VDAC(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET + DCRL − RDROOP ⎤⎦
VIN(MAX) + ILOAD(MAX) x ⎡⎣RON _ LS−FET − RON _ HS−FET ⎤⎦
(30)
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34
Where fS(MAX) is the maximum switching frequency, tHSDELAY is the turn-on delay of HS-FET, VDAC(MAX) is the
Maximum V DAC,VDDNB of application, V IN(MAX) is the
Maximum application Input voltage, I LOAD(MAX) is the
maximum load of application, RON_LS-FET is the Low side
FET RDS(ON) , RON_HS-FET is the High side FET RDS(ON) ,
DCRL is the equivalent resistance of the inductor, and
RDROOP is the load line setting.
CCRCOT
On-Time
Computer
TONSETA
RTON
R1
VIN
C1
VDAC,VDDNB
On-Time
Figure 18. VDDNB Controller : On-Time Setting with RC
Filter
Current Sense Setting
The current sense topology of the VDDNB controller is
continuous inductor current sensing. Therefore, the
controller has less sensitive noise. Low offset amplifiers
are used for current balance, loop control and over current
detection. The ISENAxP and ISENAxN pins denote the
positive and negative input of the current sense amplifier
of each phase.
Users can either use a current sense resistor or the
inductor's DCRL for current sensing. Using the inductor's
DCRL allows higher efficiency as shown in Figure 19.
VVDDNB
IL
L
DCRL
RX
ISENAxN
+
-
CX
ISENAxP
ISENAxN
RCSx
Figure 19. VDDNB Controller : Lossless Inductor
Sensing
In order to optimize transient performance, RX and CX must
be set according to the equation below :
L = R ×C
(31)
X
X
DCRL
Then the proportion between the phase current, IL, and
the sensed current, ISENAxN, is driven by the value of the
effective sense resistance, RCSx, and the DCRL of the
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DS8877C-00
November 2012
RT8877C
inductor. The resistance value of RCSx is limited by the
internal circuitry. The recommended value is from 500Ω
to 1.2kΩ.
DCRL
(32)
ISENAxN = IL ×
RCSx
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement and the recovery is too
fast causing a ring back. Vice versa, with a resistance too
large the output voltage transient has only a small initial
dip with a slow recovery.
Initial Offset and External Offset (Over Clocking
Offset Function)
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductor equivalent resistance sensing method.
VVDDNB = VDAC,VDDNB − ILOAD × RDROOP
The VDDNB controller features over clocking offset function
which provides the possibility of wide range offset of output
voltage. The initial offset function can be implemented
through the SVI interface. When the OFSA pin voltage
< 0.3V at EN rising edge, the initial offset is disabled.
The external offset function can be implemented by SET2
pin setting. For example, referring to Table 8, when the
both rail external offset functions are enabled, the output
voltage is :
+ VExternal _ OFSA + VInitial _ OFSA
(35)
VInitial_OFSA is the initial offset voltage set by SVI interface,
and the external offset voltage, VExternal_OFSA is set by
supplying a voltage into OFSA pin.
It can be calculated as below :
Per-Phase Over Current Protection
VExternal _ OFSA = VOFSA − 1.2V
The VDDNB controller provides over current protection in
each phase. For VDDNB controller in two-phase
configuration, either phase can trigger Per-Phase Over
Current Protection (PHOCP).
If supplying 1.3V at OFSA pin, it will achieve 100mV offset
at the output. Connecting a filter capacitor between the
OFSA pin and GND is necessary. Designers can design
the offset slew rate by properly setting the filter bandwidth.
The VDDNB controller senses each phase inductor current
IL, and PHOCP comparator compares sensed current with
PHOCP threshold current, as shown in Figure 20.
Dynamic VID Enhancement
Current Mirror
1 ×I
8 SENAxN
PHOCP trigger
10µA
ISENAxN
(36)
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The RT8877C will hold the inductor current
to hold the load-line during a dynamic VID event. The
VDDNB controller will always enter two-phase configuration
when VDDNB controller receives dynamic VID up and
VDDNB controller will hold the operating state when
VDDNB controller receives dynamic VID down.
Figure 20. VDDNB Controller : Per-Phase OCP Setting
Ramp Amplitude Adjust
The resistor RCSx determines PHOCP threshold.
DCRL 1
IL,PERPHASE(MAX) ×
× = 10μA
RCSx 8
When the VDDNB controller takes phase shedding
(33)
IL,PERPHASE(MAX) × DCRL
(34)
8 × 10μA
The controller will turn off all high side/low side MOSFETs
to protect CPU if the per-phase over current protection is
triggered.
RCSx =
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
operation and enters diode emulation mode, the internal
ramp of VDDNB controller will be modified for the reason
of stability. In case of smooth transition into DEM, the
CCM ramp amplitude should be designed properly. The
RT8877C provides SET1 pin for platform users to set the
ramp amplitude of the VDDNB controller in CCM.
is a registered trademark of Richtek Technology Corporation.
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35
RT8877C
Current Monitoring and Current Reporting
The VDDNB controller provides current monitoring function
via inductor current sensing. In G-NAVPTM technology,
the output voltage is dependent on output current, and
the current monitoring function is achieved by this
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and
mirrored to IMONA pin. The resistor connected to IMONA
pin determines voltage of the IMONA output.
DCRL
(37)
× RIMONA + 0.64
RCSx
Where IL is the phase current, RCSx is the effective sense
resistance, and RIMONA is the current monitor current setting
resistor. Note that the IMONA pin cannot be monitored.
VIMONA = IL,SUM × 2 ×
The ADC circuit of the VDDNB controller monitors the
voltage variation at the IMONA pin from 0V to 3.19375V,
and this voltage is decoded into digital format and stored
into Output_Current register. The ADC divides 3.19375V
into 511 levels, so LSB = 3.19375V / 511 = 6.25mV.
Quick Response
The VDDNB controller utilizes a quick response feature
to support heavy load current demand during instantaneous
load transient. The VDDNB controller monitors the current
of the VVDDNB_SENSE, and this current is mirrored to internal
quick response circuit. At steady state, this mirrored
current will not trigger a quick response. When the
VVDDNB_SENSE voltage drops abruptly due to load apply
transient, the mirrored current flowing into quick response
circuit will also increase instantaneously.
The QR threshold setting for VDDNB controller refers to
Table 5.
QRTHA
+
CMP
-
+
QR Pulse
Generation
Circuit
VVDDNB_SENSE
Figure 21. VDDNB Controller : Quick Response
Triggering Circuit
When quick response is triggered, the quick response
circuit will generate a quick response pulse. The pulse
width of quick response is almost the same with tON.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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36
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit, and all the active
phases' on-times will be overridden by the quick response
pulse.
Over Current Protection
The RT8877C has dual OCP mechanism. The dual OCP
mechanism has two types of thresholds. The first type,
referred to as OCP-TDCA, is a time and current based
threshold. OCP-TDCA should trip when the average output
current exceeds TDCA by some percentage and for a
period of time. This period of time is referred to as the
trigger delay. The second type, referred to as OCPSPIKEA, is a current based threshold. OCP-SPIKEA
should trip when the cycle-by-cycle output current
exceeds IDDSPIKEA by some percentage. If either
mechanism trips, then the VDDNB controller asserts
OCP_L and delays any further action. This delay is called
an action delay. Refer to action delay time. After the action
delay has expired and the VDDNB controller has allowed
its current sense filter to settle out and the current has
not decreased below the threshold, then the VDDNB
controller will turn off both high side MOSFETs and low
side MOSFETs of all channels.
Users can set OCP-SPIKEA threshold, IL,SUM (SPIKEA), by
the current monitor resistor R IMONA of the following
equation :
R
IL,SUM (SPIKEA) = 3.19375 − 0.64 × CSx
(38)
2 × DCRL
RIMONA
And set the OCP-TDCA threshold, IL(TDCA), refer to some
percentage of OCP-SPIKEA through Table 3.
Over Voltage Protection (OVP)
The over voltage protection circuit of the VDDNB controller
monitors the output voltage via the VSENA pin after POR.
When VID is lower than 0.9V, once VSENA exceeds “0.9V
+ 325mV”, OVP is triggered and latched. When VID is
larger than 0.9V, once V SENA exceeds the internal
reference by 325mV, OVP is triggered and latched. The
VDDNB controller will try to turn on low side MOSFETs
and turn off high side MOSFETs of all active phases of the
VDDNB controller to protect the CPU. When OVP is
triggered by one rail, the other rail will also enter soft shut
down sequence. A 1μs delay is used in OVP detection
circuit to prevent false trigger.
is a registered trademark of Richtek Technology Corporation.
DS8877C-00
November 2012
RT8877C
During OVP latch state, the VDDNB controller also
monitors the VSENA pin for negative voltage protection.
Since the OVP latch continuously turns on all low side
MOSFETs of the VDDNB controller, the VDDNB controller
may suffer negative output voltage. As a consequence,
when the VSENA voltage drops below 0V after triggering
OVP, the VDDNB controller will trigger NVP to turn off all
low side MOSFETs of the VDDNB controller while the
high side MOSFETs remains off. After triggering NVP, if
the output voltage rises above 0V, the OVP latch will restart
to turn on all low side MOSFETs. The NVP function will
be active only after OVP is triggered.
Under Voltage Protection (UVP)
The VDDNB controller implements under voltage protection
of VOUT,VDDNB. If VSENA is less than the internal reference
by 325mV, the VDDNB controller will trigger UVP latch.
The UVP latch will turn off both high side and low side
MOSFETs. When UVP is triggered by one rail, the other
rail will also enter soft shut down sequence. A 3μs delay
is used in UVP detection circuit to prevent false trigger.
Under Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC or DVD
pin drops below POR threshold, the VDDNB controller
will trigger UVLO. The UVLO protection forces all high
side MOSFETs and low side MOSFETs off by shutting
down internal PWM logic drivers. A 3μs delay is used in
UVLO detection circuit to prevent false trigger.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-52L 6x6 package, the thermal resistance, θJA, is
26.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (26.5°C/W) = 3.77W for
WQFN-52L 6x6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 22 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Maximum Power Dissipation (W)1
Negative Voltage Protection (NVP)
Four-Layer PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 22. Derating Curve of Maximum Power
Dissipation
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS8877C-00
November 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
37
RT8877C
Outline Dimension
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
5.900
6.100
0.232
0.240
D2
4.650
4.750
0.183
0.187
E
5.900
6.100
0.232
0.240
E2
4.650
4.750
0.183
0.187
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 52L QFN 6x6 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
38
DS8877C-00
November 2012