RT8889D

®
RT8889D
3-Phase PWM Controller with Triple Integrated Drivers for
VR12.5 CPU Core Power Supply
General Description
Features
The RT8889D is a three phase CPU power controller with
triple integrated drivers for VR12.5 compliant. The
RT8889D adopts G-NAVPTM (Green Native AVP) which is
Richtek's proprietary topology derived from finite DC gain
of EA amplifier with current mode control, making it an
easy setting the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning). Based on the GNAVPTM topology, the RT8889D also features a quick
response mechanism for optimized AVP performance
during load transient. The RT8889D supports mode
transition function with various operating states. A Serial
VID (SVID) interface is built in the RT8889D to
communicate with Intel VR12.5 compliant CPU. The
RT8889D supports VID on-the-fly function with three
different slew rates : Fast, Slow and Decay. By utilizing
the G-NAVPTM topology, the operating frequency of the

RT8889D varies with VID, load current and input voltage
to further enhance the efficiency even in CCM. Besides
G-NAVP TM, the CCRCOT (Constant Current Ripple
Constant On Time) technology provides superior output
voltage ripple over the entire input/output range. The builtin high accuracy DAC converts the SVID code ranging
from 0.5V to 3.04V with 10mV per step. The RT8889D
integrates a high accuracy ADC for platform setting
functions, such as no-load offset and over current
protection level. It also features complete fault protection
functions including Over Voltage (OV), Under Voltage (UV),
Negative Voltage (NV), Over Current (OC) and Under
Voltage Lockout (UVLO). The RT8889D is available in a
WQFN-40L 5x5 small foot print package.

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

Intel VR12.5 Serial VID Interface Compatible Power
Management States
3/2/1 Phase PWM Controller with Triple Integrated
Driver
G-NAVPTM Topology
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Single Phase
Fast transient Response
VR Ready Indicator
Thermal Throttling
Current Monitor Output
OVP, UVP, OCP, UVLO
External No-Load Offset Setting
DVID Enhancement
Small 40-Lead WQFN Package
Applications



VR12.5 Intel Core Supply
Notebook/Desktop Computer/Servers Multi-phase CPU
Core Supply
AVP Step-Down Converters
Simplified Application Circuit
To PCH
To CPU
RT8889D
VR_RDY PHASE1
VR_HOT
VCLK
PHASE2
VDIO
PHASE3
ALERT
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
MOSFET
MOSFET
VCORE
MOSFET
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8889D
Ordering Information
Pin Configurations
RT8889D
(TOP VIEW)
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
PVCC
LGATE3
PHASE3
UGATE3
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT8889DGQW : Product Number
RT8889D
GQW
YMDNN
YMDNN : Date Code
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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2
40 39 38 37 36 35 34 33 32 31
UGATE2
BOOT2
EN
ISEN2P
ISEN2N
ISEN1N
ISEN1P
ISEN3P
ISEN3N
IMON
1
30
2
29
3
28
4
27
5
26
GND
25
6
24
7
8
41
23
22
9
21
10
BOOT3
VR_RDY
TONSET
VCLK
ALERT
VDIO
VR_HOT
TSEN
IBIAS
SET3
11 12 13 14 15 16 17 18 19 20
VREF
NC
NC
COMP
FB
VSEN
RGND
VCC
SET1
SET2
Note :
WQFN-40L 5x5
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Functional Pin Description
Pin No.
3
Pin Name
Pin Function
EN
VR Enable Control Input.
6, 5, 9
ISEN [1:3] N
Negative Current Sense Inputs of Channel 1, 2 and 3.
7, 4, 8
ISEN [1:3] P
Positive Current Sense Inputs of Channel 1, 2 and 3.
10
IMON
CPU CORE Current Monitor Output. This pin outputs a voltage proportional to
the output current. Don’t connect a bypass capacitor from this pin to GND or
VREF pin.
11
VREF
Fixed 0.6V Reference Voltage Output. This voltage is only used to offset the
output voltage of IMON pin. Connect a 0.47F decoupling capacitor between
this pin and GND.
NC
No Internal Connection.
12, 13
14
COMP
Compensation Node for VR. This pin is error amplifier output pin.
15
FB
Negative Input of the Error Amplifier. This pin is for output voltage feedback to
controller.
16
VSEN
17
RGND
18
VCC
Power Supply Input for Controller. Connect this pin to a 5V power supply and
place a minimum 2.2F decoupling capacitor. The decoupling capacitor should
be place to PWM controller as close as possible.
19
SET1
1 Platform Setting. Platform can use this pin to set DVID compensation
threshold, RSET, DVID compensation width and OCS.
20
SET2
2 Platform Setting. Platform can use this pin to set ICCMAX, QRTH and
QRSET.
21
SET3
3
22
IBIAS
Internal Bias Current Setting. Connect a 100k resistor from this pin tied to
GND to set the internal current. Don’t connect a bypass pass capacitor from this
pin to GND.
23
TSEN
Thermal Sense Input for VR.
24
VR_HOT
Thermal Monitor Output. (Active Low)
25
VDIO
VR and CPU Data Transmission Interface.
26
ALERT
SVID Alert. (Active low)
27
VCLK
Synchronous Clock Input from the CPU.
28
TONSET
On-time Setting. An on-time setting resistor is connected from this pin to input
voltage.
29
VR_RDY
VR Ready Indicator.
34
PVCC
Driver Power. Connect this pin to GND by a minimum ceramic capacitor.
35, 39, 33
LGATE [1:3]
Low Side Drive Output. This pin drives the Gate of low side MOSFET.
36, 40, 32
PHASE [1:3]
Switch Node of High Side Driver. Connect the pin to high side MOSFET source
together with the low side MOSFET Drain and the inductor.
37, 1, 31
UGATE [1:3]
High Side Drive Output. Connect the pin to the Gate of high side MOSFET.
38, 2, 30
BOOT [1:3]
Bootstrap Supply for High Side Gate Driver.
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Voltage Sense Input for VR. This pin is connected to the terminal of VR output
voltage.
Return Ground for VR. This pin is the negative node of the differential remote
voltage sensing.
st
nd
41
(Exposed Pad)
rd
Platform Setting. Platform can use this to set output offset voltage.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8889D
VR_RDY
VCC
PVCC
VSEN
EN
VR_HOT
ALERT
VDIO
IMONI
VCLK
TSEN
SET3
SET2
SET1
Function Block Diagram
UVLO
MUX
GND
IBIAS
ADC
SVID Interface
Configuration
Registers Control
Logic
From Control Logic
RGND
DVID_TH,
DVID_WTH
DAC
Soft-Start & Slew
Rate Control
VSET
FB
Loop Control
Protection Logic
QR_TH,
QRWIDTH
DVID_TH,
DVID_WTH
ERROR
AMP
+
-
OCS
TONSET
RSET
Offset
Cancellation
+
+
COMP
+
-
1/2
IB1
+
ISEN2N
-
-
TON
GEN
PWM2
Triple
Phase
Driver
Ai
PWM3
Current mirror
ISEN2P
PWM1
QR_TH
QRWIDTH
Current mirror
ISEN1P
ISEN1N
PWM
CMP
RSET
IB2
IMON Filter
IMONI
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
BOOT3
UGATE3
PHASE3
LGATE3
Current Balance
Current mirror
ISEN3P
+
ISEN3N
-
IB1
IB3
IB2
IB3
OCP
+
OCS
OC
To Protection Logic
-
To Protection Logic
VSEN
OVP/UVP/NVP
IMON VREF
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Operation
The RT8889D adopts the G-NAVPTM (Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
Loop Control Protection Logic
The RT8889D adopts the G-NAVPTM controller, which is
one type of current mode constant on-time control with
DC offset cancellation. The approach can not only improve
DC offset problem for increasing system accuracy but also
can have fast transient response. For the RT8889D, when
current feedback signal reaches COMP signal to generate
an on-time width to achieve PWM modulation.
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
TON GEN
Generate the PWM1 to PWM3 sequentially according to
the phase control signal from the Loop Control Protection
Logic.
It controls the power on sequence, the protection behavior,
and the operational phase number.
Current Balance
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the PVCC and VCC voltage and issue POR signal
as they are high enough.
DAC
SVID Interface/Configuration Registers/Control
Logic
Generate an analog signal according to the digital code
generated by Control Logic.
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU. The registers save the pin
setting data from ADC output.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSET according to
the SetVID fast or SetVID slow.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8889D
Table 1. VR12.5 VID Code Table
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
0
0
0
0
0
0
1
01
0.500
0
0
0
0
0
0
1
0
02
0.510
0
0
0
0
0
0
1
1
03
0.520
0
0
0
0
0
1
0
0
04
0.530
0
0
0
0
0
1
0
1
05
0.540
0
0
0
0
0
1
1
0
06
0.550
0
0
0
0
0
1
1
1
07
0.560
0
0
0
0
1
0
0
0
08
0.570
0
0
0
0
1
0
0
1
09
0.580
0
0
0
0
1
0
1
0
0A
0.590
0
0
0
0
1
0
1
1
0B
0.600
0
0
0
0
1
1
0
0
0C
0.610
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0D
0E
0.620
0.630
0
0
0
0
1
1
1
1
0F
0.640
0
0
0
1
0
0
0
0
10
0.650
0
0
0
1
0
0
0
1
11
0.660
0
0
0
1
0
0
1
0
12
0.670
0
0
0
1
0
0
1
1
13
0.680
0
0
0
1
0
1
0
0
14
0.690
0
0
0
1
0
1
0
1
15
0.700
0
0
0
1
0
1
1
0
16
0.710
0
0
0
1
0
1
1
1
17
0.720
0
0
0
1
1
0
0
0
18
0.730
0
0
0
1
1
0
0
1
19
0.740
0
0
0
1
1
0
1
0
1A
0.750
0
0
0
1
1
0
1
1
1B
0.760
0
0
0
1
1
1
0
0
1C
0.770
0
0
0
1
1
1
0
1
1D
0.780
0
0
0
1
1
1
1
0
1E
0.790
0
0
0
1
1
1
1
1
1F
0.800
0
0
1
0
0
0
0
0
20
0.810
0
0
1
0
0
0
0
1
21
0.820
0
0
1
0
0
0
1
0
22
0.830
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
23
24
0.840
0.850
0
0
1
0
0
1
0
1
25
0.860
0
0
1
0
0
1
1
0
26
0.870
0
0
1
0
0
1
1
1
27
0.880
0
0
1
0
1
0
0
0
28
0.890
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
0
1
0
1
0
0
1
29
0.900
0
0
1
0
1
0
1
0
2A
0.910
0
0
1
0
1
0
1
1
2B
0.920
0
0
1
0
1
1
0
0
2C
0.930
0
0
1
0
1
1
0
1
2D
0.940
0
0
1
0
1
1
1
0
2E
0.950
0
0
1
0
1
1
1
1
2F
0.960
0
0
1
1
0
0
0
0
30
0.970
0
0
1
1
0
0
0
1
31
0.980
0
0
1
1
0
0
1
0
32
0.990
0
0
1
1
0
0
1
1
33
1.000
0
0
1
1
0
1
0
0
34
1.010
0
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
35
36
1.020
1.030
0
0
1
1
0
1
1
1
37
1.040
0
0
1
1
1
0
0
0
38
1.050
0
0
1
1
1
0
0
1
39
1.060
0
0
1
1
1
0
1
0
3A
1.070
0
0
1
1
1
0
1
1
3B
1.080
0
0
1
1
1
1
0
0
3C
1.090
0
0
1
1
1
1
0
1
3D
1.100
0
0
1
1
1
1
1
0
3E
1.110
0
0
1
1
1
1
1
1
3F
1.120
0
1
0
0
0
0
0
0
40
1.130
0
1
0
0
0
0
0
1
41
1.140
0
1
0
0
0
0
1
0
42
1.150
0
1
0
0
0
0
1
1
43
1.160
0
1
0
0
0
1
0
0
44
1.170
0
1
0
0
0
1
0
1
45
1.180
0
1
0
0
0
1
1
0
46
1.190
0
1
0
0
0
1
1
1
47
1.200
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
48
49
1.210
1.220
0
1
0
0
1
0
1
0
4A
1.230
0
0
1
1
0
0
0
0
1
1
0
1
1
0
1
0
4B
4C
1.240
1.250
0
1
0
0
1
1
0
1
4D
1.260
0
1
0
0
1
1
1
0
4E
1.270
0
1
0
0
1
1
1
1
4F
1.280
0
1
0
1
0
0
0
0
50
1.290
0
1
0
1
0
0
0
1
51
1.300
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8889D
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
1
0
1
0
0
1
0
52
1.310
0
1
0
1
0
0
1
1
53
1.320
0
1
0
1
0
1
0
0
54
1.330
0
1
0
1
0
1
0
1
55
1.340
0
1
0
1
0
1
1
0
56
1.350
0
1
0
1
0
1
1
1
57
1.360
0
1
0
1
1
0
0
0
58
1.370
0
1
0
1
1
0
0
1
59
1.380
0
1
0
1
1
0
1
0
5A
1.390
0
1
0
1
1
0
1
1
5B
1.400
0
1
0
1
1
1
0
0
5C
1.410
0
1
0
1
1
1
0
1
5D
1.420
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
5E
5F
1.430
1.440
0
1
1
0
0
0
0
0
60
1.450
0
1
1
0
0
0
0
1
61
1.460
0
1
1
0
0
0
1
0
62
1.470
0
1
1
0
0
0
1
1
63
1.480
0
1
1
0
0
1
0
0
64
1.490
0
1
1
0
0
1
0
1
65
1.500
0
1
1
0
0
1
1
0
66
1.510
0
1
1
0
0
1
1
1
67
1.520
0
1
1
0
1
0
0
0
68
1.530
0
1
1
0
1
0
0
1
69
1.540
0
1
1
0
1
0
1
0
6A
1.550
0
1
1
0
1
0
1
1
6B
1.560
0
1
1
0
1
1
0
0
6C
1.570
0
1
1
0
1
1
0
1
6D
1.580
0
1
1
0
1
1
1
0
6E
1.590
0
1
1
0
1
1
1
1
6F
1.600
0
1
1
1
0
0
0
0
70
1.610
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
71
72
1.620
1.630
0
1
1
1
0
0
1
1
73
1.640
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
74
75
1.650
1.660
0
1
1
1
0
1
1
0
76
1.670
0
1
1
1
0
1
1
1
77
1.680
0
1
1
1
1
0
0
0
78
1.690
0
1
1
1
1
0
0
1
79
1.700
0
1
1
1
1
0
1
0
7A
1.710
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is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
0
1
1
1
1
0
1
1
7B
1.720
0
1
1
1
1
1
0
0
7C
1.730
0
1
1
1
1
1
0
1
7D
1.740
0
1
1
1
1
1
1
0
7E
1.750
0
1
1
1
1
1
1
1
7F
1.760
1
0
0
0
0
0
0
0
80
1.770
1
0
0
0
0
0
0
1
81
1.780
1
0
0
0
0
0
1
0
82
1.790
1
0
0
0
0
0
1
1
83
1.800
1
0
0
0
0
1
0
0
84
1.810
1
0
0
0
0
1
0
1
85
1.820
1
0
0
0
0
1
1
0
86
1.830
1
0
0
0
0
1
1
1
87
1.840
1
0
0
0
1
0
0
0
88
1.850
1
0
0
0
1
0
0
1
89
1.860
1
0
0
0
1
0
1
0
8A
1.870
1
0
0
0
1
0
1
1
8B
1.880
1
0
0
0
1
1
0
0
8C
1.890
1
0
0
0
1
1
0
1
8D
1.900
1
0
0
0
1
1
1
0
8E
1.910
1
0
0
0
1
1
1
1
8F
1.920
1
0
0
1
0
0
0
0
90
1.930
1
0
0
1
0
0
0
1
91
1.940
1
0
0
1
0
0
1
0
92
1.950
1
0
0
1
0
0
1
1
93
1.960
1
0
0
1
0
1
0
0
94
1.970
1
0
0
1
0
1
0
1
95
1.980
1
0
0
1
0
1
1
0
96
1.990
1
0
0
1
0
1
1
1
97
2.000
1
0
0
1
1
0
0
0
98
2.010
1
0
0
1
1
0
0
1
99
2.020
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
9A
9B
2.030
2.040
1
0
0
1
1
1
0
0
9C
2.050
1
0
0
1
1
1
0
1
9D
2.060
1
0
0
1
1
1
1
0
9E
2.070
1
0
0
1
1
1
1
1
9F
2.080
1
0
1
0
0
0
0
0
A0
2.090
1
0
1
0
0
0
0
1
A1
2.100
1
0
1
0
0
0
1
0
A2
2.110
1
0
1
0
0
0
1
1
A3
2.120
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8889D
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
0
1
0
0
1
0
0
A4
2.130
1
0
1
0
0
1
0
1
A5
2.140
1
0
1
0
0
1
1
0
A6
2.150
1
0
1
0
0
1
1
1
A7
2.160
1
0
1
0
1
0
0
0
A8
2.170
1
0
1
0
1
0
0
1
A9
2.180
1
0
1
0
1
0
1
0
AA
2.190
1
0
1
0
1
0
1
1
AB
2.200
1
0
1
0
1
1
0
0
AC
2.210
1
0
1
0
1
1
0
1
AD
2.220
1
0
1
0
1
1
1
0
AE
2.230
1
0
1
0
1
1
1
1
AF
2.240
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
1
B0
B1
2.250
2.260
1
0
1
1
0
0
1
0
B2
2.270
1
0
1
1
0
0
1
1
B3
2.280
1
0
1
1
0
1
0
0
B4
2.290
1
0
1
1
0
1
0
1
B5
2.300
1
0
1
1
0
1
1
0
B6
2.310
1
0
1
1
0
1
1
1
B7
2.320
1
0
1
1
1
0
0
0
B8
2.330
1
0
1
1
1
0
0
1
B9
2.340
1
0
1
1
1
0
1
0
BA
2.350
1
0
1
1
1
0
1
1
BB
2.360
1
0
1
1
1
1
0
0
BC
2.370
1
0
1
1
1
1
0
1
BD
2.380
1
0
1
1
1
1
1
0
BE
2.390
1
0
1
1
1
1
1
1
BF
2.400
1
1
0
0
0
0
0
0
C0
2.410
1
1
0
0
0
0
0
1
C1
2.420
1
1
0
0
0
0
1
0
C2
2.430
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
C3
C4
2.440
2.450
1
1
0
0
0
1
0
1
C5
2.460
1
1
0
0
0
1
1
0
C6
2.470
1
1
0
0
0
1
1
1
C7
2.480
1
1
0
0
1
0
0
0
C8
2.490
1
1
0
0
1
0
0
1
C9
2.500
1
1
0
0
1
0
1
0
CA
2.510
1
1
0
0
1
0
1
1
CB
2.520
1
1
0
0
1
1
0
0
CC
2.530
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10
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
1
0
0
1
1
0
1
CD
2.540
1
1
0
0
1
1
1
0
CE
2.550
1
1
0
0
1
1
1
1
CF
2.560
1
1
0
1
0
0
0
0
D0
2.570
1
1
0
1
0
0
0
1
D1
2.580
1
1
0
1
0
0
1
0
D2
2.590
1
1
0
1
0
0
1
1
D3
2.600
1
1
0
1
0
1
0
0
D4
2.610
1
1
0
1
0
1
0
1
D5
2.620
1
1
0
1
0
1
1
0
D6
2.630
1
1
0
1
0
1
1
1
D7
2.640
1
1
0
1
1
0
0
0
D8
2.650
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
D9
DA
2.660
2.670
1
1
0
1
1
0
1
1
DB
2.680
1
1
0
1
1
1
0
0
DC
2.690
1
1
0
1
1
1
0
1
DD
2.700
1
1
0
1
1
1
1
0
DE
2.710
1
1
0
1
1
1
1
1
DF
2.720
1
1
1
0
0
0
0
0
E0
2.730
1
1
1
0
0
0
0
1
E1
2.740
1
1
1
0
0
0
1
0
E2
2.750
1
1
1
0
0
0
1
1
E3
2.760
1
1
1
0
0
1
0
0
E4
2.770
1
1
1
0
0
1
0
1
E5
2.780
1
1
1
0
0
1
1
0
E6
2.790
1
1
1
0
0
1
1
1
E7
2.800
1
1
1
0
1
0
0
0
E8
2.810
1
1
1
0
1
0
0
1
E9
2.820
1
1
1
0
1
0
1
0
EA
2.830
1
1
1
0
1
0
1
1
EB
2.840
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
EC
ED
2.850
2.860
1
1
1
0
1
1
1
0
EE
2.870
1
1
1
1
1
1
0
1
1
0
1
0
1
0
1
0
EF
F0
2.880
2.890
1
1
1
1
0
0
0
1
F1
2.900
1
1
1
1
0
0
1
0
F2
2.910
1
1
1
1
0
0
1
1
F3
2.920
1
1
1
1
0
1
0
0
F4
2.930
1
1
1
1
0
1
0
1
F5
2.940
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8889D
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
Voltage (V)
1
1
1
1
0
1
1
0
F6
2.950
1
1
1
1
0
1
1
1
F7
2.960
1
1
1
1
1
0
0
0
F8
2.970
1
1
1
1
1
0
0
1
F9
2.980
1
1
1
1
1
0
1
0
FA
2.990
1
1
1
1
1
0
1
1
FB
3.000
1
1
1
1
1
1
0
0
FC
3.010
1
1
1
1
1
1
0
1
FD
3.020
1
1
1
1
1
1
1
0
FE
3.030
1
1
1
1
1
1
1
1
FF
3.040
Code
Commands
00h
not supported
Table 2. Standard Serial VID Commands
Master
Slave
Payload
Payload
Description
Contents
Contents
N/A
N/A
N/A
01h
SetVID_Fast
VID code
N/A
1. Set new target VID code, VR jumps to new VID target
with controlled default “fast” slew rate 12.5mV/s.
2. Set VR_Settled when VR reaches target VID voltage.
02h
SetVID_Slow
VID code
N/A
1. Set new target VID code, VR jumps to new VID target
with controlled default “slow” slew rate 3.125mV/s.
2. Set VR_Settled when VR reaches target VID voltage.
N/A
1. Set new target VID code, VR jumps to new VID target,
but doest not control the slew rate. The output voltage
decays at a rate proportional to the load current.
2. Low side MOSFET is not allowed to sync current.
3. ACK 11b when target higher than current VOUT voltage.
4. ACK 10b when target lower than current VOUT voltage.
N/A
1. Set power state.
2. ACK 11b when not support.
3. ACK 10b even slave not change configuration.
4. ACK 11b for still running SetVID command.
5. VR remains in lower state when receiving SetVID
(decay).
N/A
1. Set the pointer of the data register.
2. ACK 11b for address outside of support.
3. NAK 01b for SetADR (all call).
N/A
1. Write the contents to the data register.
2. NAK 01b for SetReg (all call).
03h
SetVID_Decay
04h
SetPS
05h
SetRegADR
06h
SetReg DAT
07h
GetReg
08h to
1Fh
not supported
VID code
Byte
indicating
power states
Pointer of
registers in
data table
New data
register
content
Specified
Register
Contents
N/A
N/A
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12
1. Slave returns the contents of the specified register as
the payload.
2. ACK 11b for non support address.
3. NAK 01b for GetReg (all call).
N/A
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Table3. SVID Data and Configuration Register
Index
Register Name
Description
Access
Default
00h
Vendor ID
Vendor ID
RO, Vendor
1Eh
01h
Product ID
Product ID
RO, Vendor
89
02h
Product Revision
Product Revision
RO, Vendor
00h
05h
Protocol ID
SVID Protocol ID
RO, Vendor
02h
06h
Capability
Bit mapped register, identifies the SVID VR Capabilities
and which of the optional telemetry register is
supported.
RO, Vendor
81h
10h
Status_1
Data register containing the status of VR.
R-M, W-PWM
00h
11h
Status-2
Data register containing the status of transmission.
R-M, W-PWM
00h
12h
Temperature Zone
Data register showing temperature zone that has been
entered.
R-M, W-PWM
00h
15h
IOUT
The default value is 00h. When power state is PS0/1/2,
the IOUT value depends on IMON voltage. When
power state is PS3, the IOUT value is fixed to 04h.
R-M, W-PWM
00h
1Ch
Status_2_lastread
The register contains a copy of the status_2.
R-M, W-PWM
00h
21h
ICC Max
Data register containing the ICC max the platform
supports. Binary format in A IE 64h = 100A.
RO, Platform
7Dh
22h
Temp Max
RO, Platform
64h
24h
SR-fast
RO
0A
25h
SR-slow
RO
02h
30h
VOUT Max
The register is programmed by master and sets the
maximum VID.
RW, Master
B5h
31h
VID Setting
Data register containing currently programmed VID.
RW, Master
00h
32h
Power State
Register containing the current programmed power
state.
RW, Master
00h
33h
Offset
Set offset in VID steps.
RW, Master
00h
34h
Multi VR
Configuration
Bit mapped data register which configures multiple VRs
behavior on the same bus.
RW, Master
00h
35h
Pointer
Scratch pad register for temporary storage of the
SetRegADR pointer register.
RW, Master
30h
Data register containing the temperature max the
platform supports.
Binary format in C IE 64h = 100C.
Data register containing the capability of fast slew rate
the platform can sustain. Binary format in mV/s IE 0Ah
= 10 mV/s.
Data register containing the capability of slow slew
rate. Binary format in mV/s IE 03h = 3mV/s.
Notes :
RO = Read Only
RW = Read/Write
R-M = Read by Master
W-PWM = Write by PWM Only
Vendor = Hard Coded by VR Vendor
Platform = Programmed by the Master
PWM = Programmed by the VR Control IC
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8889D
Absolute Maximum Ratings















(Note 1)
VCC to GND ------------------------------------------------------------------------------------------ −0.3V to 6V
PVCC to GND ---------------------------------------------------------------------------------------- −0.3V to 15V
RGND to GND ---------------------------------------------------------------------------------------- −0.3V to 0.3V
TONSET to GND ------------------------------------------------------------------------------------- −0.3V to 28V
BOOTx to PHASEx --------------------------------------------------------------------------------- −0.3V to 15V
PHASEx to GND
DC ------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 20ns ------------------------------------------------------------------------------------------------- −10V to 35V
LGATEx to GND
DC ------------------------------------------------------------------------------------------------------- −0.3V to (PVCC + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------- −2V to (PVCC + 0.3V)
UGATEx to GND
DC ------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
Other Pins --------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
Power Dissipation, PD @ TA = 25°C
WQFN 40L 5x5 --------------------------------------------------------------------------------------- 3.64W
Package Thermal Resistance (Note 2)
WQFN 40L 5x5, θJA --------------------------------------------------------------------------------- 27.5°C/W
WQFN 40L 5x5, θJC -------------------------------------------------------------------------------- 6°C/W
Junction Temperature ------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------- 260°C
Storage Temperature Range ---------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------ 2kV
Recommended Operating Conditions




(Note 4)
Supply Voltage, PVCC ----------------------------------------------------------------------------- 4.5V to 13.5V
Supply Voltage, VCC ------------------------------------------------------------------------------- 4.5V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
5
5.5
V
Supply Input
Supply Voltage
VCC
Supply Current
IVCC
VEN = H, No switching
--
4.1
--
mA
Supply Current at PS3
IVCC_PS3
VEN = H, No switching
--
2.7
--
mA
Shutdown Current
ISHDN
VEN = 0V
--
--
5
A
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14
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Power Supply Voltage
PVCC
4.5
--
13.2
V
Power Supply Current
IPVCC
--
250
--
A
VDAC = 1.5V 2.3V
0.5
0
0.5
% of
VID
VDAC = 1V 1.49V
8
0
8
VDAC = 0.5V 0.99V
10
0
10
Reference and DAC
DAC Accuracy
VFB
mV
PVCC Power On Reset (POR)
POR Threshold
POR Hysteresis
VPOR_r
PVCC Rising
--
4
4.4
VPOR_f
PVCC Falling
3
3.5
--
--
0.5
--
Set VID slow
2.5
3.125
3.75
Set VID fast
10
12.5
15
VPOR_HYS
V
V
Slew Rate
Dynamic VID Slew Rate
SR_VID
mV/s
EA Amplifier
DC Gain
ADC
RL = 47k
70
--
--
dB
Gain-Bandwidth Product
GBW
CLOAD = 5pF
4
5
--
MHz
Slew Rate
SR
CLOAD = 10pF (Gain = 4, RF = 47k,
VOUT = 0.5V to 3V)
5
--
--
V/s
Output Voltage Range
VCOMP
RL = 47k
0.5
--
3.6
V
Maximum Source/Sink
Current
IOUTEA
VCOMP = 2V
--
5
--
mA
Load-Line Current Gain Amplifier
Input Offset Voltage
VILOFS
VIMON = 1V
5
--
5
mV
Current Gain
AILGAIN
VIMON VVREF = 1V
VFB = VCOMP = 1.7V
--
1/2
--
A/A
0.8
--
0.8
mV
1
--
--
M
Current Sensing Amplifier
Input Offset Voltage
VOSCS
Impedance at Positive Input RISENxP
Current Mirror Gain
AMIRROR
IIMON / ISENxN
0.97
1
1.03
A/A
TON Pin Voltage
VTON
IRTON = 80A, VDAC = 1.7V
1.6
1.7
1.8
V
On-Time Setting
TON
IRTON = 80A, VDAC = 1.7V
450
500
550
ns
Input Current Range
IRTON
VDAC = 1.7V
25
--
280
A
Minimum Off time
TOFF
VDAC = 1.7V
--
400
--
ns
VIBIAS
RIBIAS = 100k
1.85
2
--
V
1
--
--
M
Enable OFS function and offset 600mV
1.95
2.4
2.44
Enable OFS function and offset 300mV
1.76
1.8
1.84
TON Setting
IBIAS
IBIAS Pin Voltage
OFS Setting
Impedance
ROFS
Set OFS Voltage
VOFS
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15
RT8889D
Parameter
Set OFS Voltage
Symbol
VOFS
Test Conditions
Min
Typ
Max
Enable OFS function and offset 0V
1.16
1.2
1.24
Enable OFS function and offset 50mV
1.06
1.1
1.14
Enable OFS function and offset 250mV 0.66
0.7
0.74
--
--
0.55
4.1
4.3
4.45
V
200
VID
+ 350
1850
-VID
+ 400
1900
mV
VID lower than 1.5V
-VID
+ 300
1800
with respect to VID voltage
400
350
300
mV
100
70
--
mV
Disable
Unit
V
Protections
Under Voltage Lockout
Threshold
Over Voltage Protection
Threshold
VUVLO
VUVLO
VOV
Under Voltage Protection
VUV
Threshold
Negative Voltage Protection
VNV
Threshold
EN and VR_READY
EN Input
Voltage
Falling edge hysteresis
VID higher than 1.5V
mV
Logic-High
VEN_H
0.7
--
--
Logic-Low
VEN_L
--
--
0.3
1
--
1
A
3
4.5
6
s
--
--
0.13
V
0.65
--
--
--
--
0.45
1
--
1
A
--
--
0.13
V
0.55
0.6
0.65
V
VBOOT Voltage set to 1.7V
1.692
1.7
1.708
V
VIMON VIMON_INI = 1.6V
252
255
258
VIMON VIMON_INI = 0.8V
125
128
131
0
0
3
320
400
480
s
--
1.887
--
V
Leakage Current of EN
VR_READY Delay
TVR_RD
VSEN = VBOOT to VR_READY High
VR_READY Pull Low
Voltage
VPGOOD IVR_READY = 10mA
V
Serial VID and VR_HOT
VCLK, VDIO
Input Voltage
Logic-High
VIH
Logic-Low
VIL
With Respect to INTEL Spec. with
50mV hysteresis
Leakage Current of VCLK,
ILEAK_IN
VDIO, ALERT and VR_HOT
V
IVDIO = 10mA
VDIO, ALERT and VR_HOT
Pull Low Voltage
IALERT = 10mA
IVR_HOT = 10mAs
VREF and VBOOT
VREF Voltage
VREF
VBOOT Voltage
VBOOT
ADC
Digital IMON Set
VIMON
VIMON VIMON_INI = 0V
Update Period of IMON
TIMON
TSEN Threshold for
Tmp_Zone [7] transition
VTSEN
100C
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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16
Decimal
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
TSEN Threshold for
Tmp_Zone [6] transition
VTSEN
97C
--
1.837
--
V
TSEN Threshold for
Tmp_Zone [5] transition
VTSEN
94C
--
1.784
--
V
TSEN Threshold for
Tmp_Zone [4] transition
VTSEN
91C
--
1.729
--
V
TSEN Threshold for
Tmp_Zone [3] transition
VTSEN
88C
--
1.672
--
V
TSEN Threshold for
Tmp_Zone [2] transition
VTSEN
85C
--
1.612
--
V
TSEN Threshold for
Tmp_Zone [1] transition
VTSEN
82C
--
1.551
--
V
TSEN Threshold for
Tmp_Zone [0] transition
VTSEN
75C
--
1.402
--
V
Update Period of TSEN
t TSEN
40
50
60
s
CICCMAX1
VICCMAX = 0.403V
58
64
70
CICCMAX2
VICCMAX = 0.806V
122
128
134
CICCMAX3
VICCMAX = 1.6V
248
256
260
UGATEx Rising Time
t UGATEr
3nF load
--
25
--
ns
UGATEx Falling Time
t UGATEf
3nF load
--
12
--
ns
LGATEx Rising Time
t LGATEr
3nF load
--
24
--
ns
LGATEx Falling Time
t LGATEf
3nF load
VBOOTx VPHASEx = 12V
See Timing Diagram
--
10
--
ns
--
60
--
--
22
--
--
30
--
--
8
--
Digital Code of ICCMAX
Decimal
Timing
t UGATEpgh
Propagation Delay
t UGATEpdl
t LGATEpdh
See Timing Diagram
t LGATEpdl
ns
ns
Output
UGATEx Drive Source
RUGATEsr
VBOOT  VPHASE = 12V,
ISource = 100mA
--
1.7
--

UGATEx Drive Sink
RUGATEsk
VBOOT  VPHASE = 12V,
ISink = 100mA
--
1.4
--

LGATEx Drive Source
RLGATEsr
I Source = 100mA
--
1.6
--

LGATEx Drive Sink
RLGATEsk
I Sink = 100mA
--
1.1
--

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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17
www.richtek.com
18
VCC
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
VSS_SENSE
VCC_SENSE
To CPU
R9
6.86k
C9
Optional
C7
C8
Optional
R25
59.2k
R24
10k
R20
75
C6
90pF
R21
130
VCC
24
29
10
11
22
ALERT
COMP
15
FB
17 RGND
14
16 VSEN
3 EN
26
VR_RDY
VR_HOT
VCLK
VDIO
IMON
VREF
IBIAS
37
2
R33 0
R32 2.2
R27 0
R43 680
Q6 x 2
R35
510
C29
R40
R41
510
Optional
R42
C30 1µF
360nH / 0.72m
L3
C28
390µF
Optional
R36
C21 1µF
L2
C19
390µF
Optional
R30
C15 1µF
R37
VCC_SENSE
C22 C23
560µF/7m C22
22µFx19
x4
360nH / 0.72m Optional
C27
22µF
C20
R34
Optional
12V
C26
0.1µF
Q5
R37 680
Q4 x 2
Optional
C18
22µF
C14
R28
L1
C13
390µF
360nH / 0.72m
R29
510
C12
22µF
Optional
12V
C17
0.1µF
Q3
R31 680
Q2 x 2
VIN
12V
C11
0.1µF
Q1
R1
1
GND 41 (Exposed Pad)
ISEN3P 8
9
ISEN3N
PHASE3 32
LGATE3 33
R39 0
30 R38 2.2
UGATE3 31
BOOT3
4
ISEN2P
ISEN2N 5
LGATE2 39
PHASE2 40
UGATE2 1
BOOT2
ISEN1P 7
6
ISEN1N
PHASE1 36
35
LGATE1
UGATE1
C1
2.2µF
38 R26 2.2
PVCC 34
BOOT1
RT8889D
28 TONSET
23 TSEN
19 SET1
20 SET2
21 SET3
18
27
25
R19
10k
R18
5.43k
C5
390pF
R22
130
Enable
R23
150
ß = 4485
RNTC2
100k
VCCIO
R17
13.9k
R5
C2
2.2µF
R15
100k
R7
1.833k
R16 12.6k
C3
0.1µF
R14
130k
R12
6.2k
Optional
R13 1
R11 5.6k
R8 53.7k
C4
0.47µF
VIN
RNTC1
100k
ß = 4485
R10 100k
Optional for OFS
R6 30k
R4
5V
R3
2.2
LOAD
VCORE_OUT
R38
VSS_SENSE
RT8889D
Typical Application Circuit
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Typical Operating Characteristics
CORE VR Power On from EN
CORE VR Power Off from EN
V CORE
(2V/Div)
V CORE
(2V/Div)
EN
(2V/Div)
VR_RDY
(2V/Div)
EN
(2V/Div)
VR_RDY
(2V/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
VIN = 12V, No Load, Boot VID 1.7V
VIN = 12V, No Load, Boot VID 1.7V
Time (200μs/Div)
Time (200μs/Div)
CORE VR OCP
CORE VR OVP
V CORE
(2V/Div)
V CORE
(2V/Div)
I LOAD
(150A/Div)
VR_RDY
(1V/Div)
VR_RDY
(2V/Div)
UGATE1
(50V/Div)
UGATE1
(20V/Div)
LGATE1
(20V/Div)
VIN = 12V, Boot VID 1.7V
VIN = 12V, Boot VID 1.7V
Time (100μs/Div)
Time (40μs/Div)
CORE VR Dynamic VID Up
CORE VR Dynamic VID Down
V CORE
(1V/Div)
V CORE
(1V/Div)
VCLK
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VIN = 12V, VID = 1.6V to 1.85V, Slew Rate = Slow
Time (20μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
VIN = 12V, VID = 1.85V to 1.6V, Slew Rate = Slow
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
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19
RT8889D
CORE VR Dynamic VID Up
CORE VR Dynamic VID Down
V CORE
(1V/Div)
V CORE
(1V/Div)
VCLK
(2V/Div)
VCLK
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VDIO
(2V/Div)
ALERT
(2V/Div)
VIN = 12V, VID = 1.6V to 1.85V, Slew Rate = Fast
VIN = 12V, VID = 1.85V to 1.6V, Slew Rate = Fast
Time (10μs/Div)
Time (10μs/Div)
CORE VR Mode Transient
CORE VR Mode Transient
V CORE
(50mV/Div)
V CORE
(50mV/Div)
VCLK
(1V/Div)
VCLK
(1V/Div)
UGATE1
(20V/Div)
UGATE1
(20V/Div)
LGATE1
(10V/Div)
LGATE1
(10V/Div)
VIN = 12V, VID = 1.7V, PS0 to PS2, ILOAD = 0.6A
VIN = 12V, VID = 1.7V, PS2 to PS0, ILOAD = 0.6A
Time (100μs/Div)
Time (100μs/Div)
CORE VR Thermal Monitoring
VIMON vs. Load Current
2.5
VIMON (V)
2.0
TSEN
(1V/Div)
VR_HOT
(1V/Div)
1.5
1.0
0.5
VIN = 12V, TSEN Sweep from 1.7V to 2.1V
0.0
Time (10ms/Div)
0
25
50
75
100
125
Load Current (A)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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20
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Applications information
The RT8889D is a 3/2/1 multiphase synchronous Buck
controller designed to meet Intel VR12.5 compatible CPU
specification with a serial SVID control interface. The
controller uses an ADC to implement all kinds of settings
to save a total number of pins for easily using and
increasing PCB space utilization. RT8889D is suitable for
the applications of notebook, desktop computer and server.
G-NAVPTM Control Mode
The RT8889D adopts the G-NAVPTM control topology, which
is a current mode constant on-time control with DC offset
cancellation. The approach can not only improve DC offset
problem for increasing system accuracy but also provide
fast transient response. Figure 1 shows the basic GNAVPTM behavior waveforms in Continuous Conduct Mode
(CCM).
When the current feedback signal reaches Comp signal,
an on-time pulse will be generated to achieve PWM
modulation.
Current feedback signal
Diode Emulation Mode (DEM)
As well-known, the dominate power loss is switching
related loss during light load, hence VR needs to be
operated in asynchronous mode (or called discontinuous
conduct mode, DCM) to reduce switching related loss.
Since switching frequency is dependent on loading in the
asynchronous mode, the RT8889D can operate in Diode
Emulation Mode (DEM) to improve light load efficiency. In
DEM operation, the behavior of the low side MOSFET(s)
needs to work like a diode, that is, the low side MOSFET(s)
will be turned on when the phase voltage is a negative
value, i.e. the inductor current follows from source to drain
in the low side MOSFET(s). The low side MOSFET(s) will
be turned off when phase voltage is a positive value, i.e.
reversed current is not allowed. Figure 2 shows the control
behavior in DEM. Figure 3 shows the G-NAVPTM operation
in DEM to illustrate the control behaviors. When the load
decreases, the discharge time of output capacitors
increases during UGATE and LGATE are turned off. Hence,
the switching frequency and switch loss will be reduced
to improve the efficiency in light load condition.
Inductor current
Comp signal
PWM1
Phase node
PWM2
PWM3
Figure 1 (a). G-NAVPTM Behavior Waveforms in CCM in
Steady State
UGATE
LGATE
Current feedback signal
Figure 2. Diode Emulation Mode (DEM) in Steady State
Comp signal
PWM1
PWM2
PWM3
Figure 1 (b). G-NAVPTM Behavior Waveforms in CCM in
Load Transient
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21
RT8889D
Inductor
current signal
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(a). Lighter Load Condition
Capacitor discharge slope is lower than Figure 3 (b).
Inductor
current signal
Output capacitor
discharge slope
COMP signal
UGATE
LGATE
(b). Load Increased Condition
Capacitor discharge slope is higher than Figure 3 (a).
Figure 3. G-NAVPTM Operation in DEM.
VR Power State
Phase Interleaving Function
The RT8889D supports power state change by CPU
command through SVID protocol. As RT8889D receives a
set PSx command, the VR changes the power state to
meet the operation current. In RT8889D, PS0 means the
full phase CCM operation; PS1 means the one phase CCM
operation; PS2 means the one phase DEM operation; PS3
means the one phase DEM operation with low quiescent
current, as shown in Table 4.
The RT8889D is a multiphase controller, which has a phase
interleaving function, 120 degree phase shift for 3-phase
operation and 180 degree phase shift for 2-phase operation
which can reduce output voltage ripple and EMI problem.
Table 4 : Set PSx Command and Operation Mode
Set PSx
Command
PS0
Operation
Mode
CCM
Operation
Phase Number
3
PS1
CCM
1
PS2
DEM
1
PS3
DEM
1
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Switching Frequency (TON) Setting
The RT8889D is one kind of constant on-time control. The
patented CCRCOT (Constant Current Ripple COT)
technology can generate an adaptive on-time with input
voltage and VID code to obtain a constant current ripple.
So that the output voltage ripple can be controlled nearly
like a constant as different input and output voltage change.
Connect a resistor RTON between input terminal and
TONSET pin to set the on-time width.
TON =
RTON  C  2.2
VIN  VDAC
TON =
RTON  C  VDAC
VIN  VDAC
 VDAC
< 2.2V 
 VDAC
 2.2V 
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Where C = 18.2pF, VREF = 2.2V. By using the relationship
between TON and fSW, the switching frequency fSW is :

1
fSW(MAX) = 
T
ON(MAX)

VCORE
ILx
  VDAC(MAX) 
   VIN(MAX) 
 

ISENxN
fSW(MAX) is the maximum switching frequency.
+
-
VDAC(MAX) is the maximum VDAC of application.
LX
DCR
RX
CX
ISENxP
RCSx
ISENxN
VIN(MAX) is the maximum application input voltage.
Figure 4. Lossless Current Sense Method
TON(MAX) is derived from TON equation with maximum
parameters (VIN(MAX), VDAC(MAX)).
When load increases, on-time keeps constant. The
off-time width will be reduced so that loading can load
more power from input terminal to regulate output voltage.
Hence the loading current increases in case the switching
frequency also increases. Higher switching frequency
operation can reduce power components' size and PCB
space, trading off the whole efficiency since switching
related loss increases, vice versa.
Per Phase Current Sense
In the RT8889D, the current signal is used for load-line
setting and OC (Over Current) protections. The inductor
current sense method adopts the lossless current sensing
for allowing high efficiency as illustrated in the Figure 4.
When inductance and DCR time constant is equal to RXCX
Total Current Sense
Total current sense method is a patented topology, unlike
conventional current sense method requiring a NTC resistor
in per phase current loop for thermal compensation.
RT8889D adopts the total current sense method requiring
only one NTC resistor for thermal compensation, and NTC
resistor cost can be saved by using this method. Figure 5
shows the total current sense method which connects
the resistor network between the IMON and VREF pins to
set a part of current loop gain for load-line (droop) setting
and set accurate over current protection.
VIMON  VREF = DCR  REQ  (IL1 + IL2 + IL3 )
RCS
REQ includes a NTC resistor to compensate DCR thermal
drifting for high accuracy load-line (droop).
filter network time constant, a voltage ILX x DCR will drop
on CX to generate inductor current signal. According to
the Figure 4, the ISENxN is as follows :
ISENxN =
IMON
ISEN1N
ILX  DCR
RCSx
Where LX / DCR = RXCX is held. The method can get high
efficiency performance, but DCR value will be drifted by
temperature, a NTC resistor should add in the resistor
network in the IMON pin to achieve DCR thermal
compensation.
In RT8889D design, the resistance of the RCSx is restricted
to 680Ω; moreover, the accuracy of RCS is recommended
to be 1% or higher.
VCORE
IL1
+
-
L
DCR
R
C
ISEN1P
RCS
ISEN1N
IL2
L
DCR
R
C
RNTC
REQ
ISEN2N
+
-
ISEN2P
RCS
ISEN2N
IL3
L
DCR
R
C
VREF
ISEN3N
+
-
ISEN3P
ISEN3N
RCS
Figure 5. Total Current Sense Method
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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23
RT8889D
Load-Line (Droop) Setting
Compensator Design
The G-NAVPTM topology can set load-line (droop) via the
current loop and the voltage loop, the load-line is a slope
between load current ICC and output voltage VCORE as
shown in Figure 6. Figure 7 shows the voltage control and
current loop. By using both loops, the load-line (droop)
can easily be set. The load-line set equation is :
The compensator of RT8889D doesn't need a complex
type II or type III compensator to optimize control loop
performance. It can adopt a simple type I compensator
(one pole, one zero) in G-NAVPTM topology to achieve
constant output impedance design for Intel VR12.5 ACLL
specification. The one pole one zero compensator is
showed as Figure 8, the transfer function of compensator
should be designed as the following transfer function to
achieve constant output impedance, i.e. Zo(s) = load-line
slope in the entire frequency range :
RLL =
AI
AV
1 DCR

 REQ
2 RCS
=
(m )
R2
R1
VCORE
GCON
s
1+
AI
  fsw
(s) 

RLL 1 + s
ESR
Load-line slope = -RLL
RLL x ICC
ICC
Figure 6. Load-Line (Droop)
VCORE
R2
Voltage Loop
Where AI is current loop gain, RLL is load-line, fSW is
switching frequency and ωESR is a pole that should be
located at 1 / (COUT x ESR). Then the C1 and C2 should
be designed as follows :
C1 =
1
R1   fSW
C2 =
COUT  ESR
R2
C2
TON Generator
-
R1
+
+
R2
-
IL1.2.3
VID
-
1/2
R1
-
L
+
DCR
C1
+
R
C
RCS
ISEN[1:3]P
+
-
ISEN1N + ISEN2N
+ ISEN3N
RNTC
IMON
VID
VREF
ISEN[1:3]N
Figure 8. Type I Compensator
REQ
Figure 7. Voltage Loop and Current Loop
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is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Multi-Function Pin Setting Mechanism
For reducing total pin number of package, the SET[1:2]
pins adopt the multi-function pin setting mechanism in
RT8889D. Figure 9 illustrates this operating mechanism.
First, external voltage divider is to set the Function 1 and
then internal current source 80μA is to set the Function
2. The setting voltage of Function 1 and Function 2 can
be represented as follows :
R2
VFunction 1 =
 VCC
R1 + R2
R1 R2
VFunction 2 = 80 A 
R1 + R2
All function setting will be done within 500μs after power
ready (POR).
If VFunction 1 and VFunction 2 are determined, R1 and R2 can
be calculated as follows :
V V
R1 = CC Function 2
80 A  VFunction 1
R2 =
R1 VFunction 1
VCC  VFunction 1
In addition, Richtek provides a Microsoft Excel-based
spreadsheet to help design the SETx resistor network for
RT8889D.
Function 2 Function 1
<5:0>
<5:0>
Connecting a R3 resistor from the SET[1:2] pin to the
middle node of voltage divider can help to fine tune the set
voltage of Function 1, which does not affect the set voltage
of Function 1. The Figure 10 shows the setting method
and the set voltage of Function 1 and Function 2 can be
represented as :
R2
 VCC
R1 + R2
R1 R2 

= 80 A   R3 +

R1
+ R2 

VFunction 1 =
VFunction 2
Function 2 Function 1
<5:0>
<5:0>
80µA
ADC
VCC
Function 1
Register
R1
SET[1:2]
R2
Function 2
Register
Function 2 Function 1
<5:0>
<5:0>
80µA
ADC
VCC
Function 1
Register
80µA
R1
SET[1:2]
ADC
VCC
Function 1
Register
R3
R3
R2
Function 2
Register
R1
SET[1:2]
R2
Function 2
Register
Function 2 Function 1
<5:0>
<5:0>
Figure 10. Multi-Function Pin Setting Mechanism with a
R3 resistor to fine tune the set voltage of Function 2
80µA
ADC
VCC
Function 1
Register
R1
SET[1:2]
Function 2
Register
R2
Figure 9. Multi-Function Pin Setting Mechanism
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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25
RT8889D
Quick Response (QR) Mechanism
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, that output voltage generate undershoot to fail
specification. The RT8889D has Quick Response (QR)
mechanism being able to improve this issue. It adopts a
nonlinear control mechanism which can disable
interleaving function and simultaneously to turn on one all
UGATE pulse at instantaneous step-up transient load to
restrain the output voltage drooping, Figure 11 shows the
QR behavior.
The output voltage signal behavior needs to be detected
so that QR mechanism can be trigged. The output voltage
signal is via a remote sense line to connect at the VSEN
pin that is shown in Figure 12. The QR mechanism needs
to set QR width and QR threshold. Both definitions are
shown in Figure 9. A proper QR mechanism set can meet
different applications. The SET2 pin is a multi-function
pin which can set QR threshold, QR width and ICCMAX.
Current Mirror
QR trigger
QR Width
IMirror
VCORE
VID
VCC_SENSE
+
-
RQR VSEN
QR Threshold
Figure 12. Simplified QR Trigger Schematic
PWM1
PWM2
PWM3
Load
Figure 11. Quick Response Mechanism
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
26
An internal current source 80μA is used in multi-function
pin setting mechanism. For example, 35mV QR threshold
and 1.3 x TON QR width are set. According to the Table
5, the set voltage should be between 0.4504V and 0.4723V.
Please note that a high accuracy resistor is needed for
this setting accuracy, <1% error tolerance is
recommended.
In the Table 5, there are some “No Use” marks in
QRWIDTH section. It means that user should not use it
to avoid the possibility of shift digital code due to tolerance
concern.
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Table 5 : SET2 Pin Setting for QR Threshold and QR Width
VQR_SET = 80 A 
R1 R2
R1 R2
QR_TH
<2:0>
QRWIDTH
<2:0>
QR
Threshold
QR Width
(%TON)
Min
Typical
Max
unit
0.000
10.948
21.896
mV
000
No Use
25.024
35.973
46.921
mV
001
155%
50.049
60.997
71.945
mV
010
133%
75.073
100.098
86.022
111.046
96.970
121.994
mV
mV
125.122
150.147
136.070
161.095
147.019
172.043
mV
mV
101
110
67%
44%
175.171
200.196
225.220
186.119
211.144
236.168
197.067
222.092
247.116
mV
mV
mV
111
000
001
No Use
No Use
155%
250.244
275.269
261.193
286.217
272.141
297.165
mV
mV
010
011
133%
111%
300.293
311.241
322.190
mV
325.318
336.266
347.214
mV
101
67%
350.342
375.367
361.290
386.315
372.239
397.263
mV
mV
110
111
44%
No Use
400.391
411.339
422.287
mV
000
No Use
425.415
450.440
436.364
461.388
447.312
472.336
mV
mV
001
010
155%
133%
475.464
486.413
497.361
mV
500.489
525.513
511.437
536.461
522.385
547.410
mV
mV
550.538
561.486
572.434
mV
110
44%
575.562
600.587
625.611
586.510
611.535
636.559
597.458
622.483
647.507
mV
mV
mV
111
000
001
No Use
No Use
155%
650.635
675.660
661.584
686.608
672.532
697.556
mV
mV
010
011
133%
111%
700.684
725.709
711.632
736.657
722.581
747.605
mV
mV
750.733
761.681
772.630
mV
110
44%
775.758
800.782
786.706
811.730
797.654
822.678
mV
mV
111
000
No Use
No Use
825.806
836.755
847.703
mV
001
155%
850.831
875.855
861.779
886.804
872.727
897.752
mV
mV
010
011
133%
111%
900.880
911.828
922.776
mV
000
001
010
011
100
011
100
100
011
100
101
100
101
100
Disable
30mV
35mV
40mV
45mV
111%
89%
89%
111%
89%
67%
89%
67%
89%
925.904
936.852
947.801
mV
101
67%
950.929
975.953
961.877
986.901
972.825
997.849
mV
mV
110
111
44%
No Use
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
27
RT8889D
VQR_SET = 80 A 
R1 R2
R1 R2
QR_TH
<2:0>
QRWIDTH
<2:0>
QR
Threshold
QR Width
(%TON)
Min
Typical
Max
unit
1000.978
1011.926
1022.874
mV
000
No Use
1026.002
1036.950
1047.898
mV
001
155%
1051.026
1061.975
1072.923
mV
010
133%
1076.051
1101.075
1086.999
1112.023
1097.947
1122.972
mV
mV
1126.100
1137.048
1147.996
mV
101
67%
1151.124
1162.072
1173.021
mV
110
44%
1176.149
1201.173
1187.097
1212.121
1198.045
1223.069
mV
mV
111
000
No Use
No Use
1226.197
1237.146
1248.094
mV
001
155%
1251.222
1276.246
1262.170
1287.195
1273.118
1298.143
mV
mV
010
011
133%
111%
1301.271
1312.219
1323.167
mV
1326.295
1337.243
1348.192
mV
101
67%
1351.320
1376.344
1362.268
1387.292
1373.216
1398.240
mV
mV
110
111
44%
No Use
1401.369
1412.317
1423.265
mV
000
No Use
1426.393
1451.417
1437.341
1462.366
1448.289
1473.314
mV
mV
001
010
155%
133%
1476.442
1487.390
1498.338
mV
1501.466
1526.491
1512.414
1537.439
1523.363
1548.387
mV
mV
1551.515
1562.463
1573.412
mV
110
44%
1576.540
1587.488
1598.436
mV
111
No Use
Dynamic VID (DVID) Compensation
When VID transition event occurs, a charge current will
be generated in the loop to cause that DVID performance
is deteriorated by this induced charge current, the
phenomenon is called droop effect. The droop effect is
shown in Figure 13. When VID up transition occurs, the
output capacitor will be charged by inductor current. Since
current signal is sensed in inductor, an induced charge
current will appear in control loop. The induced charge
current will produce a voltage drop in R1 to cause output
voltage to have a droop effect. Due to this, VID transition
performance will be deteriorated.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
28
101
110
111
011
100
100
011
100
101
50mV
55mV
60mV
111%
89%
89%
111%
89%
67%
The RT8889D provides a DVID compensation function. A
virtual charge current signal can be established by the
SET1 pin to cancel the real induced charge current signal
and the virtual charge current signal is defined in Figure
15. Figure 14 shows the operation of canceling droop
effect. A virtual charge current signal is established first
and then VID signal plus virtual charge current signal is
generated in FB pin. Hence, an induced charge current
signal flows to R1 and is cancelled to reduce droop effect.
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Charge current
L
VIN
Q1
Gate
Driver
CO1
Q2
CO2
RESR
CPU
Ai
Induced charge
current signal
C2
C1
R2
CCRCOT
VIN
COMP -
VID
+
tON
DVID_Width
Output voltage
DVID_Threshold
R1
EA
+
IDROOP
Figure 15. Definition of Virtual Charge Current Signal
VID
VID Transition
Figure 13. Droop Effect in VID Transition
Charge current
L
VIN
Q1
Gate
Driver
CO1
Q2
CO2
RESR
Ai
Induced charge
current signal
Output voltage
CPU
C2
C1
R2
CCRCOT
VIN
COMP -
VID
+
tON
IDROOP
R1
EA
+
Virtual Charge Current
+
Slew Rate
Control
VID
VID Transition
DVID Event
Virtual Charge
Current
Generator
SET1
Figure 14. DVID Compensation
Table 6 and Table 7 show the DVID_Threshold and
DVID_Width settings in SET1 pin. For example, 25mV
DVID_Threshold and 72μs DVID_Width are designed (OCP
sets as 100% ICCMAX, and RSET sets as 100% Ramp
current). The DVID_Width is set by an external voltage
divider to set and the DVID_Threshold is set by an internal
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
current source 80μA by the multi-function pin setting
mechanism. According to the Table 6 and Table 7, the
DVID_Threshold set voltage should be between 0.225V
and 0.247V and the DVID_Width set voltage should be
between 0.275V and 0.297V. Please note that a high
accuracy resistor is needed for this setting, <1% error
tolerance is recommended.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
29
RT8889D
Table 6 : SET1 Pin Setting for DVID_Threshold
VDVID_T hreshold = 80 A 
R1 R2
R1 R2
DVID_TH
<2:0>
DVID_Threshold
OCP = %ICCMAX
Min
Typical
Max
unit
0.000
10.948
21.896
mV
OCS
<2:0>
000
25.024
50.049
75.073
35.973
60.997
86.022
46.921
71.945
96.970
mV
mV
mV
001
010
011
100.098
125.122
111.046
136.070
121.994
147.019
mV
mV
150.147
175.171
200.196
161.095
186.119
211.144
172.043
197.067
222.092
mV
mV
mV
110
111
000
150%
No Use
No Use
225.220
250.244
236.168
261.193
247.116
272.141
mV
mV
001
010
100%
110%
275.269
300.293
325.318
286.217
311.241
336.266
297.165
322.190
347.214
mV
mV
mV
350.342
375.367
361.290
386.315
372.239
397.263
mV
mV
110
111
150%
No Use
400.391
425.415
411.339
436.364
422.287
447.312
mV
mV
000
001
No Use
100%
450.440
475.464
500.489
461.388
486.413
511.437
472.336
497.361
522.385
mV
mV
mV
010
011
100
110%
120%
130%
525.513
550.538
575.562
536.461
561.486
586.510
547.410
572.434
597.458
mV
mV
mV
101
110
111
140%
150%
No Use
600.587
625.611
650.635
611.535
636.559
661.584
622.483
647.507
672.532
mV
mV
mV
000
001
010
No Use
100%
110%
675.660
700.684
725.709
750.733
686.608
711.632
736.657
761.681
697.556
722.581
747.605
772.630
mV
mV
mV
mV
775.758
800.782
825.806
786.706
811.730
836.755
797.654
822.678
847.703
mV
mV
mV
111
000
001
No Use
No Use
100%
850.831
875.855
900.880
861.779
886.804
911.828
872.727
897.752
922.776
mV
mV
mV
010
011
100
110%
120%
130%
925.904
950.929
936.852
961.877
947.801
972.825
mV
mV
101
110
140%
150%
975.953
986.901
997.849
mV
111
No Use
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
30
000
001
010
011
100
100
101
011
100
101
011
100
101
110
No Use
15mV
25mV
35mV
45mV
55mV
100%
110%
120%
130%
140%
120%
130%
140%
120%
130%
140%
150%
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Min
Typical
1000.978
1011.926
1022.874
R1 R2
R1 R2
DVID_TH
unit
<2:0>
mV
1026.002
1051.026
1076.051
1036.950
1061.975
1086.999
1047.898
1072.923
1097.947
mV
mV
mV
1101.075
1126.100
1151.124
1112.023
1137.048
1162.072
1122.972
1147.996
1173.021
mV
mV
mV
1176.149
1201.173
1226.197
1187.097
1212.121
1237.146
1198.045
1223.069
1248.094
mV
mV
mV
111
000
001
No Use
No Use
100%
1251.222
1276.246
1301.271
1262.170
1287.195
1312.219
1273.118
1298.143
1323.167
mV
mV
mV
010
011
100
110%
120%
130%
1326.295
1351.320
1376.344
1337.243
1362.268
1387.292
1348.192
1373.216
1398.240
mV
mV
mV
101
110
111
140%
150%
No Use
1401.369
1426.393
1412.317
1437.341
1423.265
1448.289
mV
mV
000
001
No Use
100%
1451.417
1476.442
1501.466
1462.366
1487.390
1512.414
1473.314
1498.338
1523.363
mV
mV
mV
010
011
100
110%
120%
130%
1526.491
1551.515
1576.540
1537.439
1562.463
1587.488
1548.387
1573.412
1598.436
mV
mV
mV
VDVID_Threshold = 80 A 
Max
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
101
110
111
OCS
<2:0>
000
001
010
011
100
101
110
101
110
111
DVID_Threshold OCP = %ICCMAX
No Use
65mV
75mV
85mV
100%
110%
120%
130%
140%
150%
140%
150%
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
31
RT8889D
Min
Typical
0.000
25.024
10.948
35.973
50.049
75.073
100.098
60.997
86.022
111.046
125.122
136.070
150.147
161.095
175.171
200.196
225.220
186.119
211.144
236.168
250.244
275.269
261.193
286.217
300.293
311.241
325.318
336.266
350.342
375.367
400.391
361.290
386.315
411.339
425.415
450.440
436.364
461.388
475.464
486.413
500.489
511.437
525.513
550.538
575.562
536.461
561.486
586.510
600.587
625.611
611.535
636.559
650.635
661.584
675.660
700.684
686.608
711.632
725.709
750.733
736.657
761.681
775.758
800.782
786.706
811.730
825.806
836.755
850.831
875.855
900.880
925.904
861.779
886.804
911.828
936.852
950.929
975.953
961.877
986.901
Table 7 : SET1 Pin Setting for DVID_Width
R2
VDVID_Width =
 VCC
R1 R2
DVID_Width
DVID_WTH
RSET
Max
unit
<2:0>
<2:0>
21.896
mV
000
46.921
mV
001
71.945
mV
010
96.970
mV
011
000
48s
121.994
mV
100
147.019
mV
101
172.043
mV
110
197.067
mV
111
222.092
mV
000
247.116
mV
001
272.141
mV
010
297.165
mV
011
001
72s
322.190
mV
100
347.214
mV
101
372.239
mV
110
397.263
mV
111
422.287
mV
000
447.312
mV
001
472.336
mV
010
497.361
mV
011
010
96s
522.385
mV
100
547.410
mV
101
572.434
mV
110
597.458
mV
111
622.483
mV
000
647.507
mV
001
672.532
mV
010
697.556
mV
011
011
120s
722.581
mV
100
747.605
mV
101
772.630
mV
110
797.654
mV
111
822.678
mV
000
847.703
mV
001
872.727
mV
010
897.752
mV
011
100
144s
922.776
mV
100
947.801
mV
101
972.825
mV
110
997.849
mV
111
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
32
RSET % 130k RTON
No Use
75%
87.5%
100%
112.5%
125%
137.5%
No Use
No Use
75%
87.5%
100%
112.5%
125%
137.5%
No Use
No Use
75%
87.50%
100%
112.5%
125%
137.5%
No Use
No Use
75%
87.50%
100%
112.50%
125%
137.5%
No Use
No Use
75%
87.5%
100%
112.50%
125%
137.5%
No Use
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
VDVID_Width =
R2
 VCC
R1 R2
DVID_WTH
unit
<2:0>
mV
mV
mV
RSET
<2:0>
000
001
010
DVID_Width
RSET % 130k RTON
Min
Typical
Max
1000.978
1026.002
1051.026
1011.926
1036.950
1061.975
1022.874
1047.898
1072.923
1076.051
1101.075
1126.100
1086.999
1112.023
1137.048
1097.947
1122.972
1147.996
mV
mV
mV
1151.124
1176.149
1201.173
1162.072
1187.097
1212.121
1173.021
1198.045
1223.069
mV
mV
mV
110
111
000
137.5%
No Use
No Use
1226.197
1251.222
1276.246
1237.146
1262.170
1287.195
1248.094
1273.118
1298.143
mV
mV
mV
001
010
011
75%
87.5%
100%
1301.271
1312.219
1323.167
mV
1326.295
1351.320
1376.344
1337.243
1362.268
1387.292
1348.192
1373.216
1398.240
mV
mV
mV
101
110
111
125%
137.5%
No Use
1401.369
1426.393
1451.417
1412.317
1437.341
1462.366
1423.265
1448.289
1473.314
mV
mV
mV
000
001
010
No Use
75%
87.50%
1476.442
1501.466
1487.390
1512.414
1498.338
1523.363
mV
mV
1526.491
1551.515
1576.540
1537.439
1562.463
1587.488
1548.387
1573.412
1598.436
mV
mV
mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
101
110
111
011
100
101
100
011
100
101
110
111
No Use
75%
87.5%
168s
192s
216s
100%
112.5%
125%
112.5%
100%
112.5%
125%
137.5%
No Use
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
33
RT8889D
Ramp Compensation
Current Monitor, IMON
TM
The G-NAVP topology is one type of ripple based control
that has fast transient response, no beat frequency issue
in high repetitive load frequency operation and lower BOM
cost. However, ripple based control usually has no good
noise immunity. The RT8889D provides a ramp
compensation to increase noise immunity and reduce jitter
at the switching node. Figure 16 shows the ramp
compensation.
Noise Margin
w/o ramp compensation
IMON-VREF
RT8889D includes a current monitor (IMON) function which
can be used to detect over current protection and the
maximum processor current ICCMAX, and also sets a
part of current gain in the load-line setting. It produces an
analog voltage proportional to output current between the
IMON and the VREF pins.
The calculation for IMON-VREF voltage is shown as
below :
DCR
VIMON  VREF =
 REQ  IL1 + IL2 + IL3 
RCS
Where IL1 + IL2 + IL3 are output current and the definitions
of DCR, RCS and REQ can refer to Figure 6.
VCOMP
Maximum Processor Current Setting, ICCMAX
Noise Margin
w/ ramp compensation
IMON-VREF
VCOMP
The maximum processor current ICCMAX can be set by
the SET2 pin. ICCMAX register is set by an external voltage
divider by the multi-function mechanism. The Table 8
shows the ICCMAX setting in the SET2 pin. For example,
ICCMAX = 106A, the VICCMAX needs to be set as 0.67
typically. Additionally, VIMON − VREF needs to be set as
1.6V when IL1 + IL2 + IL3 = 106A. The ICCMAX alert signal
will be pulled to low level if VIMON − VREF = 1.6V.
Figure 16. Ramp Compensation
For the RT8889D, the ramp compensation also needs to
be considered during mode transition from PS0/1 to PS2.
For achieving smooth mode transition into PS2, a proper
ramp compensation design is necessary. Since the ramp
compensation needs to be proportional to the on-time, in
others words, ramp compensation is dependent on RTON
design. Table 7 shows the relationship between RTON and
ramp compensation. For example, when designed RTON
is 100kΩ, the RAMP is set as 130k  100% .
100k
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
34
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Table 8 : SET2 Pin Setting for ICCMAX
Min
0.000
12.512
25.024
37.537
50.049
62.561
75.073
87.586
100.098
112.610
125.122
137.634
150.147
162.659
175.171
187.683
200.196
R2
 VCC
R1  R2
Typical
Max
Unit
3.128
6.256
mV
15.640 18.768
mV
28.152 31.281
mV
40.665 43.793
mV
53.177 56.305
mV
65.689 68.817
mV
78.201 81.329
mV
90.714 93.842
mV
103.226 106.354 mV
115.738 118.866 mV
128.250 131.378 mV
140.762 143.891 mV
153.275 156.403 mV
165.787 168.915 mV
178.299 181.427 mV
190.811 193.939 mV
203.324 206.452 mV
212.708
225.220
237.732
250.244
262.757
275.269
287.781
300.293
312.805
325.318
337.830
350.342
362.854
375.367
387.879
400.391
412.903
425.415
437.928
450.440
462.952
475.464
487.977
500.489
215.836
228.348
240.860
253.372
265.885
278.397
290.909
303.421
315.934
328.446
340.958
353.470
365.982
378.495
391.007
403.519
416.031
428.543
441.056
453.568
466.080
478.592
491.105
503.617
VICCMAX =
218.964
231.476
243.988
256.500
269.013
281.525
294.037
306.549
319.062
331.574
344.086
356.598
369.110
381.623
394.135
406.647
419.159
431.672
444.184
456.696
469.208
481.720
494.233
506.745
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
ICCMAX Unit
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Min
513.001
525.513
538.025
550.538
563.050
575.562
588.074
600.587
613.099
625.611
638.123
650.635
663.148
675.660
688.172
700.684
713.196
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
725.709
738.221
750.733
763.245
775.758
788.270
800.782
813.294
825.806
838.319
850.831
863.343
875.855
888.368
900.880
913.392
925.904
938.416
950.929
963.441
975.953
988.465
1000.978
1013.490
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
R2
 VCC
ICCMAX Unit
R1 R2
Typical
Max
Unit
516.129 519.257 mV
82
A
528.641 531.769 mV
84
A
541.153 544.282 mV
86
A
553.666 556.794 mV
88
A
566.178 569.306 mV
90
A
578.690 581.818 mV
92
A
591.202 594.330 mV
94
A
603.715 606.843 mV
96
A
616.227 619.355 mV
98
A
628.739 631.867 mV
100
A
641.251 644.379 mV
102
A
653.763 656.891 mV
104
A
666.276 669.404 mV
106
A
678.788 681.916 mV
108
A
691.300 694.428 mV
110
A
703.812 706.940 mV
112
A
716.325 719.453 mV
114
A
728.837
741.349
753.861
766.373
778.886
791.398
803.910
816.422
828.935
841.447
853.959
866.471
878.983
891.496
904.008
916.520
929.032
941.544
954.057
966.569
979.081
991.593
1004.106
1016.618
VICCMAX =
731.965
744.477
756.989
769.501
782.014
794.526
807.038
819.550
832.063
844.575
857.087
869.599
882.111
894.624
907.136
919.648
932.160
944.673
957.185
969.697
982.209
994.721
1007.234
1019.746
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
is a registered trademark of Richtek Technology Corporation.
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35
RT8889D
Min
1026.002
1038.514
1051.026
1063.539
1076.051
1088.563
1101.075
1113.587
1126.100
1138.612
1151.124
1163.636
1176.149
1188.661
1201.173
1213.685
1226.197
R2
 VCC
ICCMAX Unit
R1 R2
Typical
Max
Unit
1029.13 1032.258 mV
164
A
1041.642 1044.770 mV
166
A
1054.154 1057.283 mV
168
A
1066.667 1069.795 mV
170
A
1079.179 1082.307 mV
172
A
1091.691 1094.819 mV
174
A
1104.203 1107.331 mV
176
A
1116.716 1119.844 mV
178
A
1129.228 1132.356 mV
180
A
1141.740 1144.868 mV
182
A
1154.252 1157.380 mV
184
A
1166.764 1169.892 mV
186
A
1179.277 1182.405 mV
188
A
1191.789 1194.917 mV
190
A
1204.301 1207.429 mV
192
A
1216.813 1219.941 mV
194
A
1229.326 1232.454 mV
196
A
1238.710
1251.222
1263.734
1276.246
1288.759
1301.271
1241.838
1254.350
1266.862
1279.374
1291.887
1304.399
VICCMAX =
1244.966
1257.478
1269.990
1282.502
1295.015
1307.527
mV
mV
mV
mV
mV
mV
198
200
202
204
206
208
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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36
A
A
A
A
A
A
Min
1313.783
1326.295
1338.807
1351.320
1363.832
1376.344
1388.856
1401.369
1413.881
1426.393
1438.905
1451.417
R2
 VCC
ICCMAX Unit
R1 R2
Typical
Max
Unit
1316.911 1320.039 mV
210
A
1329.423 1332.551 mV
212
A
1341.935 1345.064 mV
214
A
1354.448 1357.576 mV
216
A
1366.960 1370.088 mV
218
A
1379.472 1382.600 mV
220
A
1391.984 1395.112 mV
222
A
1404.497 1407.625 mV
224
A
1417.009 1420.137 mV
226
A
1429.521 1432.649 mV
228
A
1442.033 1445.161 mV
230
A
1454.545 1457.674 mV
232
A
1463.930
1476.442
1488.954
1501.466
1513.978
1526.491
1539.003
1551.515
1564.027
1576.540
1589.052
1467.058
1479.570
1492.082
1504.594
1517.107
1529.619
1542.131
1554.643
1567.155
1579.668
1592.180
VICCMAX =
1470.186
1482.698
1495.210
1507.722
1520.235
1532.747
1545.259
1557.771
1570.283
1582.796
1595.308
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
234
236
238
240
242
244
246
248
250
252
254
A
A
A
A
A
A
A
A
A
A
A
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Over Current Protection
Under Voltage Lock Out (UVLO)
The RT8889D provides Over Current Protection (OCP)
which is adjustable by the SET1 pin. The OCP threshold
setting can refer to ICCMAX current in the Table 8. For
example, if ICCMAX is set as 120A, user can set voltage
by using the external voltage divider in SET1 pin as 0.466V
typically if DVID_Threshold = 35mV, then 144A OCP
(120% x ICCMAX) threshold will be set. When output
current is higher than the OCP threshold, the OCP will be
triggered with a 40μs delay time to prevent false trigger.
Besides, the OCP function is masked when dynamic VID
transient occurs and after dynamic VID transition, OCP is
masked for 80μs.
During normal operation, if the voltage at the VCC pin
drops below POR threshold 4.1V (min), the VR will trigger
UVLO. The UVLO protection forces all high side MOSFETs
and low side MOSFETs off by shutting down internal PWM
logic drivers.
Over Output Voltage Protection
An OVP condition is detected when the VSEN pin is
350mV higher than VID. When OVP is detected, the high
side gate voltage UGATEx is pulled-low and the low side
gate voltage LGATEx is pulled-high, OVP is latched with
a 0.5μs delay time to prevent false trigger.
Negative Voltage Protection
Since the OVP latch continuously turns on all low side
MOSFETs of the VR, the VR will suffer negative output
voltage. When the VSEN detects a voltage below −0.05V
after triggering OVP, the VR will trigger NVP to turn off all
low side MOSFETs of the VR while the high side MOSFETs
remains off. After triggering NVP, if the output voltage rises
above 0V, the OVP latch will restart to turn on all low side
MOSFETs. Therefore, the output voltage may bounce
between 0V and −0.05V due to OVP latch and NVP
triggering. The NVP function will be active only after OVP
is triggered.
Power Ready (POR) Detection
During start-up, the RT8889D will detect the voltage at
the voltage input pins : VCC ,EN and PVCC. When
VCC > 4.45V and PVCC > 4.4V the RT8889D will recognize
the power state of system to be ready (POR = high) and
wait for enable command at the EN pin. After POR = high
and VEN > 0.7V, the RT8889D will enter start-up sequence.
If the voltage at any voltage pin drops below low threshold
(POR = low), the RT8889D will enter power down sequence
and all the functions will be disabled. Normally, connecting
system voltage V TT (1.05V) to the EN pin is
recommended.1ms (max) after the chip has been enabled,
the SVID circuitry will be ready. All the protection latches
(OVP, OCP, UVP) will be cleared only by VCC. The
condition of VEN = low will not clear these latches. Figure
17 and Figure 18 show the POR detection and the timing
chart for POR process, respectively.
5V
VCC
+
4.45V
PVCC
PVCC
CP
-
POR
DRIVER
Enable
VTT
1.05V
EN
+
0.7V
CP
-
Figure 17. POR Detection
Under Voltage Protection
When the VSEN pin voltage is 350mV lower than the VID
voltage, a UVP will be triggered. When UVP is latched,
both the UGATEx and LGATEx will be pulled-low. A 3μs
delay is used in UVP detection circuit to prevent false
trigger. Besides, the UVP function is masked when
dynamic VID transient occurs and after dynamic VID
transition, UVP is masked for 80μs.
VCC
PVCC
POR
EN
1ms
SVID Invalid
Valid
Invalid
Figure 18. Timing Chart for POR Process
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
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37
RT8889D
Precise Reference Current Generation, IBIAS
Analog circuits need very precise reference voltage/current
to drive/set these analog devices. The RT8889D provides
a 2V voltage source at the IBIAS pin, and a 100kΩ resistor
is required to be connected between IBIAS pin and analog
ground to generate a very precise reference current.
Through this connection, the RT8889D will generate a
20μA current from the IBIAS pin to analog ground, and
this 20μA current will be mirrored inside the RT8889D for
internal use. The IBIAS pin can only be connected with a
100kΩ resistor to GND for internal analog circuit use. The
resistance accuracy of this resistor is recommended to
be 1% or higher. Figure 19 shows the IBIAS setting circuit.
Current Mirror
2V
+
20µA
-
IBIAS
100k
Figure 19. IBIAS Setting Circuit
VDDIO
VR_HOT
VCC
R1
+
NTC
TSEN
-
R2
1.887V
Figure 20. VR_HOT Circuit
Differential Remote Sense Setting
The VR provides differential remote sense inputs to
eliminate the effects of voltage drops along the PC board
traces, CPU internal power routes and socket contacts.
The CPU contains on-die sense pins, VCC_SENSE and
VSS_SENSE. Connecting RGND to VSS_SENSE and FB to
VCC_SENSE with a resistor to build the negative input path
of the error amplifier. The VDAC and the precision voltage
reference are referred to RGND for accurate remote
sensing.
CPU VCC_SENSE
VOUT
TSEN and VR_HOT
VTSEN = VCC 
R2
R2 + R1//RNTC(100C) 
VID
RGND
COUT
R2
CPU VSS_SENSE
Figure 21. Remote Sensing Circuit
= 1.887V
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
38
FB
EA
+
+
The VR_HOT signal is an open-drain signal which is used
for VR thermal protection. When the sensed voltage in
TSEN pin is over 1.887V, the VR_HOT signal will be pulledlow to notify CPU that the thermal protection needs to
work. According to Intel VR definition, VR_HOT signal
needs acting if VR power chain temperature exceeds
100°C. Placing an NTC thermistor at the hottest area in
the VR power chain and its connection is shown in Figure
20, to design the voltage divider elements (R1, R2 and
NTC) so that VTSEN = 1.887V at 100°C. The resistance
accuracy of TSEN network is recommended to be 1% or
higher.
R1
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DS8889D-00 April 2015
RT8889D
NO Load Offset (Platform)
Phase Disable (Before POR)
RT8889D provides no load offset for platform users. Users
can disable this function by pulling the SET3 pin to ground.
Figure 22 shows a voltage divider used to set no load
offset voltage. No load offset voltage setting is :
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during startup. Normally, the VR operates as a 3-phase PWM
controller. Pulling ISEN3N to VCC programs a 2-phase
operation, and pulling ISEN2N and ISEN3N to VCC
programs a 1-phase operation. Before POR, VR detects
whether the voltages of ISEN2N and ISEN3N are higher
than “VCC − 1V” respectively to decide how many phases
should be active. Phase selection is only active during
POR. When POR = high, the number of active phases is
determined and latched. The unused ISENxP pins are
recommended to be connected to VCC and unused PWM
pins can be left floating.
1
  VSET3  1.2 
2
The range of VOFS is −250mV < VOFS < 600mV.
VOFS =
For example, a 100mV no load offset requirement, VSET3
needs to be set as 1.4V.
From gm
DAC
+
VCC
COMP
-
FB
R1
SET3
gm
R2
Figure 22. No Load Offset Circuit
Current Loop Design in Details
IL1
VREF
REQ
RIMON3
RNTC
RIMON1 IMON ISEN1N
+
-
VCORE
L1
DCR1
R1
C1
ISEN1P
ISEN1N
680
RIMON2
IL2
0.6V
DCR2
R2
C2
+
1/2
COMP
L2
+
ISEN2N
+
+
-
ISEN2P
ISEN2N
680
IL3
L3
DCR3
R3
ISEN3N
+
-
C3
ISEN3P
ISEN3N
680
Figure 23. Current Loop Structure
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
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39
RT8889D
Figure 23 shows the whole current loop structure. The
current loop plays an important role in RT8889D that can
decide ACLL performance, DCLL accuracy and ICCMAX
accuracy. For ACLL performance, the correct compensator
design is assumed, if RC network time constant matches
inductor time constant LX/DCRX, an expected load transient
waveform can be designed. If RXCX network time constant
is larger than inductor time constant LX/DCRX, VCORE
waveform has a sluggish droop during load transient. If
RXCX network is smaller than inductor time constant
LX/DCRX, a worst VCORE waveform will sag to create an
undershoot to fail the specification. Figure 24 shows the
variety of RXCX constant corresponding to the output
waveforms.
Lx
R x  Cx =
DCR x
VCORE
IOUT x RLL
For DCLL performance and ICCMAX accuracy, since the
copper wire of inductor has a positive temperature
coefficient, when temperature goes high in the heavy load
condition then DCR value goes large simultaneously. A
resistor network with NTC thermistor compensation
connecting between IMON pin and REF pin is necessary,
to compensate the positive temperature coefficient of
inductor DCR. The design flow is as follows :
Step1 : Given the three system temperature TL, TR and
TH, at which are compensated.
Step2 : Three equations can be listed as
DCR (TL ) 4
  iLi  REQ (TL ) = 1.6
680
i=1
DCR (TR ) 4
  iLi  REQ (TR ) = 1.6
680
i=1
DCR (TH ) 4
  iLi  REQ (TH ) = 1.6
680
i=1
Where :
IOUT
IOUT
Expected load transient waveform
R x  Cx <
VCORE
Lx
DCR x
IOUT x RLL
IOUT
Undershoot created in VCORE
VCORE


REQ (T) = RIMON1 + RIMON2 / / RIMON3 + RNTC (T)
And the relationship between NTC and temperature is as
follows :
RNTC (T) = RNTC (25C)  e
β(
1
1
)

T+273 298
β is in the NTC thermistor datasheet.
Step3 : Three equations and three unknowns, RIMON1,
RIMON2 and RIMON3 can be found out unique solution.
Lx
DCR x
IOUT x RLL
IOUT
IOUT
Sluggish droop
Figure 24. All Kind of RXCX Constants
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40
DCR (T) = DCR (25C)  1+ 0.00393 (T  25)
(2) REQ(T) is the equivalent resistor of the resistor network
with a NTC thermistor
IOUT
R x  Cx >
(1) The relationship between DCR and temperature is as
follows :
RIMON1 = K TR 
RIMON2 =
RIMON2  (RNTCTR +RIMON3 )
RIMON2 +RNTCTR +RIMON3
2
[KR3
+KR3 (RNTCTL +RNTCTR )
+RNTCTLRNTCTR ]α TL
RIMON3 = -RIMON2 +KR3
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DS8889D-00 April 2015
RT8889D
Where :
(1) Initial Settings :
α TH =
K TH  K TR
RNTCTH  RNTCTR
α TL =
K TL  K TR
RNTCTL  RNTCTR
KR3 =
(α TH / α TL )RNTCTH  RNTCTL
1  (α TH / α TL )

RT8889D initial voltage is 1.7V

IBIASE needs to connect a 100kΩ resistor to ground.
(2) Loop Design :

tON =
1.6
K TL =
GCS(TL)  ICC-MAX
K TR =
1.6
GCS(TR)  ICC-MAX
K TH =
1.6
GCS(TH)  ICC-MAX
On time setting : Using the specification, TON is

VDAC(MAX)
VIN
= 514n(s)
Current sensor adopts lossless RC filter to sense current
signal in DCR. For getting an expected load transient
waveform, RxCx time constant needs to match LX/DCRX
per phase. Cx = 1μF is set, then
RX =
RT8889D Excel based design tool is available. Users can
contact your Richtek representative to get the
spreadsheet. Three main design procedures for RT8889D
design, first step is initial settings, second step is loop
design and the last step is protection settings. The
following design example is to explain RT8889D design
procedure :
1.85V
ICCMAX
ICC-DY
ICC-TDC
Load-Line
90A
60A
55A
1.5m
Fast Slew Rate
Max Switching
Frequency
12.5mV/s
300kHz
In Shark Bay VRTB Guideline, the output filter
requirements of VRTB specification for desktop platform
are as follows :
Output Inductor : 360nH/0.72mΩ
Output Bulk Capacitor : 560μF/2.5V/5mΩ (max) 4 to 5pcs
Output Ceramic Capacitor : 22μF/0805 (18pcs max sites
on top side)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
LX
= 500
1F  DCR X

IMON resistor network design : TL = 25°C, TR = 50°C
and TH = 100°C are decided, NTC thermistor = 100kΩ
@25°C, β = 4485 and ICCMAX = 90A. According to the
sub-section “Current Loop Design in Details”, RIMON1
= 5.43kΩ, RIMON2 = 12.6kΩ and RIMON3 = 13.9kΩ can
be decided. The REQ (25°C) = 16.8kΩ.

Load-line design : 1.5mΩ droop is required, because
REQ (25°C) is decided, the voltage loop Av gain is also
decided by the following equation :
VCORE Specification
12V
3
1.7V
VDAC(MAX)
DS8889D-00 April 2015
fSW(MAX)

The on time setting resistor RTON = 130kΩ
Design Step :
Input Voltage
No. of Phases
Vboot
1
RLL
1 DCR

 REQ
2 RCS
A
= V =
(m)
R2
AI
R1
Where DCR (25°C) = 0.72mΩ, RCS = 680Ω and REQ (25°C)
= 16.8kΩ. Hence the AV = R2 / R1 = 5.92 can be obtained.
R1 = 10kΩ usually is decided, so R2 = 59.2kΩ.

Typical compensator design can use the following
equations to design the C1 and C2 values
C1 =
1
 106pF
R1   fSW
C2 =
COUT  ESR
 79pF
R2
For Intel platform, in order to induce the band width to
enhance transient performance to meet Intel's criterion,
the compensator of zero can be designed close to 1/10 of
switching frequency.
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41
RT8889D
R2  5
R1  R2
0.737 = 80A  R1 R2
R1  R2
0.286 


R1 = 160kΩ, R2 = 9.77kΩ.

SET2 resistor network design : the QR mechanism
parameters need to be designed first. Initial QR_TH is
designed as 0.4 x LL x ICC-DY = 36mV and QR_Width
is designed as 1.11 x TON. The ICCMAX is designed as
90A. By using the information, the two equations can
be listed by using multi-function pin setting mechanism
R2
0.566 =
5
R1 +R2
 R1 R2 
0.486=80A  

 R1 R2 
R1 = 53.7kΩ, R2 = 6.86kΩ.

No load offset function disabled. Just connect a 0Ω
resistor from SET3 pin to ground.
(3) Protection Settings :


OVP/UVP protections : When the VSEN pin voltage is
350mV more than VID, the OVP will be latched. When
the VSEN pin voltage is 350mV less than VID, the UVP
will be latched.
TSEN and VR_HOT design : Using the following equation
to calculate related resistances for VR_HOT setting.
R2
VTSEN = VCC 
= 1.887V
R2 + RNTC(100C) // R1
Choosing R1 = 100kΩ and an NTC thermistor RNTC (25°C)
= 100kΩ which β =4485. When temperature is 100°C, the
RNTC(100°C) = 4.85kΩ.Then R2 = 2.8kΩ can be calculated.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
42
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-40L 5x5 package, the thermal resistance, θJA, is
27.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.64W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 25 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
SET1 resistor network design : First the DVID
compensation parameters need to be decided. The
DVID_TH can be calculated as the following equation :
DVID
VDVID_TH = LL  COUT 
dt
Where LL is load-line, COUT is total output capacitance
and dVID/dt is DVID fast slew rate. Thus VDVID_TH = 45mV
is needed in this case. And DVID_Width is chosen as
72μs typically. Next, OCP threshold is designed as 1.4 x
ICCMAX. Last, RAMP = RTON / 130kΩ = 100%, 100% is
set. By using above information, the two equations can
be listed by using multi-function pin setting mechanism

4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 25. Derating Curve of Maximum Power
Dissipation
is a registered trademark of Richtek Technology Corporation.
DS8889D-00 April 2015
RT8889D
Layout Considerations
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
of the power components on the top side of the board
with their ground terminals flushed against one another.
Follow these guidelines for optimum PC board layout :

Keep the high current paths short, especially at the
ground terminals.

Keep the power traces and load connections short. This
is essential for high efficiency.

When trade-offs in trace lengths must be made, it's
preferable to let the inductor charging path be longer
than the discharging path.

Place the current sense component close to the
controller. ISENxP and ISENxN connections for current
limit and voltage positioning must be made using Kelvin
sense connections to guarantee current sense accuracy.
The PCB trace from the sense nodes should be
paralleled back to the controller.

Route high speed switching nodes away from sensitive
analog areas (COMP, FB, ISENxP, ISENxN, etc...)

Connect the exposed pad to a strong ground plane
through low impedance path. Recommend use of at
least 5 vias to connect to ground planes in PCB internal
layers.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8889D-00 April 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
43
RT8889D
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
b
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
44
DS8889D-00 April 2015