S71AL016D based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 16 Megabit (1 M x 16-bit) CMOS 3.0 Volt-only Flash Memory and 2 Megabit (128K x 16-bit) Static RAM/ Pseudo Static RAM ADVANCE INFORMATION Distinctive Characteristics MCP Features Power supply voltage of 2.7 to 3.1 volt High performance Packages — 7 x 9 x 1.2 mm 56 ball FBGA Operating Temperature — –25°C to +85°C (Wireless) — 70 ns General Description The S71AL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One S29AL Flash memory die pSRAM or SRAM The products covered by this document are listed in the table below: Flash Memory Density 16Mb SRAM Density Publication Number S71AL016D_02_04_00 2Mb Revision A S71AL016D02 Amendment 1 Issue Date November 11, 2004 P r e l i m i n a r y Product Selector Guide 16 Mb Flash Memory 2 Device-Model# Flash Access time (ns) SRAM density (p)SRAM Access time (ns) SRAM type Package S71AL016D02-TF 70 2 M SRAM 70 SRAM2 TLC056 S71AL016D02-BF 70 2 M SRAM 70 SRAM2 TLC056 S71AL016D02-T7 70 2 M SRAM 70 SRAM1 TLC056 S71AL016D02-B7 70 2 M SRAM 70 SRAM1 TLC056 S71AL016D based MCPs S71AL016D_02_04_00_A1 November 11, 2004 A d v a n c e I n f o r m a t i o n TABLE OF CONTENTS S71AL016D based MCPs Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1 MCP Features ........................................................................................................ 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2 16 Mb Flash Memory .............................................................................................2 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . .9 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 10 TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package ............................................................................................... 10 S29AL016D General Description 12 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 1. S29AL016D Device Bus Operations .......................... 15 Word/Byte Configuration .................................................................................15 Requirements for Reading Array Data ..........................................................15 Writing Commands/Command Sequences ................................................. 16 Program and Erase Operation Status ........................................................... 16 Standby Mode ....................................................................................................... 16 Automatic Sleep Mode .......................................................................................17 RESET#: Hardware Reset Pin ..........................................................................17 Output Disable Mode .........................................................................................17 Table 2. Sector Address Tables (Top Boot Device) ................. 18 Table 3. Sector Address Tables (Bottom Boot Device) ............ 19 Autoselect Mode ................................................................................................ 20 Table 4. S29AL016D Autoselect Codes (High Voltage Method) . 20 Sector Protection/Unprotection ................................................................... 20 Temporary Sector Unprotect ......................................................................... 21 Figure 1. Temporary Sector Unprotect Operation.................... 21 Figure 2. In-System Sector Protect/Unprotect Algorithms ........ 22 Common Flash Memory Interface (CFI) . . . . . . .23 Table 5. Table 6. Table 7. Table 8. CFI Query Identification String ................................ 23 System Interface String ......................................... 24 Device Geometry Definition .................................... 24 Primary Vendor-Specific Extended Query ................. 25 Hardware Data Protection ..............................................................................25 Low VCC Write Inhibit ..................................................................................25 Write Pulse “Glitch” Protection ................................................................25 Logical Inhibit .................................................................................................. 26 Power-Up Write Inhibit ............................................................................... 26 Reading Array Data ............................................................................................27 Reset Command ..................................................................................................27 Autoselect Command Sequence ....................................................................27 Word/Byte Program Command Sequence ................................................ 28 Unlock Bypass Command Sequence ........................................................ 28 Figure 3. Program Operation................................................ 29 Chip Erase Command Sequence ................................................................... 29 Sector Erase Command Sequence ................................................................ 30 Erase Suspend/Erase Resume Commands ....................................................31 Figure 4. Erase Operation.................................................... 32 Command Definitions ........................................................................................33 Write Operation Status . . . . . . . . . . . . . . . . . . . . 34 DQ7: Data# Polling ............................................................................................ 34 Figure 5. Data# Polling Algorithm ........................................ 35 RY/BY#: Ready/Busy# ....................................................................................... 35 DQ6: Toggle Bit I ............................................................................................... 36 DQ2: Toggle Bit II .............................................................................................. 36 Reading Toggle Bits DQ6/DQ2 ..................................................................... 37 Figure 6. Toggle Bit Algorithm ............................................. 38 DQ5: Exceeded Timing Limits ........................................................................ 38 DQ3: Sector Erase Timer ................................................................................ 39 Table 10. Write Operation Status ......................................... 39 Figure 7. Maximum Negative Overshoot Waveform ................ 40 Figure 8. Maximum Positive Overshoot Waveform.................. 40 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents).................................................. 42 Figure 10. Typical ICC1 vs. Frequency ................................... 43 Figure 11. Test Setup......................................................... 44 Table 11. Test Specifications ............................................... 44 Figure 12. Input Waveforms and Measurement Levels ............ 45 Read Operations .................................................................................................46 Figure 13. Read Operations Timings..................................... 46 Hardware Reset (RESET#) .............................................................................. 47 Figure 14. RESET# Timings................................................. 47 Word/Byte Configuration (BYTE#) ...........................................................48 Figure 15. BYTE# Timings for Read Operations...................... 48 Figure 16. BYTE# Timings for Write Operations ..................... 49 Erase/Program Operations ..............................................................................50 Figure 17. Program Operation Timings ................................. 51 Figure 18. Chip/Sector Erase Operation Timings .................... 52 Figure 19. Data# Polling Timings (During Embedded Algorithms).. 53 Figure 20. Toggle Bit Timings (During Embedded Algorithms).. 53 Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations . 54 Figure 22. Temporary Sector Unprotect/Timing Diagram......... 54 Figure 23. Sector Protect/Unprotect Timing Diagram .............. 55 Figure 24. Alternate CE# Controlled Write Operation Timings .. 57 TSOP and BGA Pin Capacitance . . . . . . . . . . . . 58 2Mbit Type 1 SRAM Common Features . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . 60 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 These parameters are verified in device characterization and are not 100% tested. . . . . . 60 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 60 Operating Characteristics (Over Specified Temperature Range) . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 1. Power Savings with Page Mode (WE# = VIH) ........... 62 Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 62 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 2. Timing of Read Cycle (CE# = OE# = VIL, WE# = CE2= VIH) ................................................................................. 64 Figure 3. Timing Waveform of Read Cycle (WE# = VIH) .......... 64 Figure 4. Timing Waveform of Write Cycle (WE# Control) ....... 65 Figure 5. Timing Waveform of Write Cycle (CE1# Control) ...... 65 Table 9. S29AL016D Command Definitions ........................... 33 November 11, 2004 S71AL016D_02_04_00_A1 3 A d v a n c e 2Mbit Type 2 SRAM Common Features . . . . . . . . . . . . . . . . . . . . . . . . 66 Functional Description . . . . . . . . . . . . . . . . . . . . . 66 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating Range ..................................................................................................67 Product Portfolio ................................................................................................67 Electrical Characteristics ..................................................................................67 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 AC Test Loads and Waveforms . . . . . . . . . . . . . 68 Figure 1. AC Test Loads and Waveforms................................ 68 Data Retention Characteristics (Over the Operation Range) . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 2. Data Retention Waveform ...................................... 69 Switching Characteristics . . . . . . . . . . . . . . . . . . 70 4 I n f o r m a t i o n Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 71 Figure 3. Read Cycle 1 (Address Transition Controlled) ........... Figure 4. Read Cycle 2 (OE# Controlled)............................... Figure 5. Write Cycle 1 (WE# Controlled).............................. Figure 6. Write Cycle 2 (CE# Controlled) .............................. Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW) .............. Figure 8. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) ..... 71 71 72 73 73 74 Typical DC and AC Parameters . . . . . . . . . . . . . 74 Figure 9. Operating Current vs. Supply Voltage ..................... 74 Figure 10. Standby Current vs. Supply Voltage...................... 74 Figure 11. Access Time vs. Supply Voltage............................ 75 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 1. Truth Table ........................................................... 75 Revision Summary S71AL016D_02_04_00_A1 November 11, 2004 P r e l i m i n a r y MCP Block Diagram VCCf VCC CE#f RST#f Flash 1 Shared Address A19-A0 OE# WE# VSS RY/BY# VCCS DQ15 to DQ0 VCC A16-A0 pSRAM/SRAM IO15-IO0 CE1#s CE1# UB# UB# LB# LB# CE2s CE2 November 11, 2004 S71AL016D_02_04_00_A1 5 P r e l i m i n a r y Connection Diagram 56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A2 A3 A4 A5 A6 A7 Legend A7 LB# RFU WE# A8 A11 B1 B2 B3 B4 B5 B6 B7 B8 A3 A6 UB# RST#f CE2s A19 A12 A15 C1 C2 C3 C4 C5 C6 C7 C8 RY/BY# RFU Flash only A2 A5 A18 A9 A13 RFU D1 D2 D3 D6 D7 D8 A1 A4 A17 A10 A14 RFU E1 E2 E3 E6 E7 E8 A0 VSS DQ1 DQ6 RFU A16 F1 F2 F3 F4 F5 F6 F7 F8 CE1#f OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU G1 G2 G3 G4 G5 G6 G7 G8 CE1#s DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS H2 H3 H4 H5 H6 H7 DQ8 DQ2 DQ11 RFU DQ5 DQ14 MCP S71AL016D02 6 RAM only Reserved for Future Use Flash Only Address Shared Addresses A19-A17 A16-A0 S71AL016D_02_04_00_A1 November 11, 2004 P r e l i m i n a r y Pin Description A16–A0 A19–A17 DQ15–DQ0 CE1#f CE1#s CE2s OE# WE# RY/BY# UB# LB# RST#f VCCf = = = = = = = = = = = = = VCCs VSS NC RFU = = = = 17 Address Inputs (Common) 3 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 1 (SRAM) Chip Enable 2 (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin, Active Low (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally Reserved for Future Use Logic Symbol 20 A19–A0 16 CE# DQ15–DQ0 CE1#s CE2s OE# RY/BY# WE# RST#f UB# LB# November 11, 2004 S71AL016D_02_04_00_A1 7 P r e l i m i n a r y Ordering Information The order number is formed by a valid combinations of the following: S71AL 016 D 02 BA W T F 0 PACKING TYPE 0 = Tray 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER See the Valid Combinations table. BOOT TYPE T = Top Boot B = Bottom Boot TEMPERATURE RANGE W = Wireless (-25°C to +85°C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package SRAM DENSITY 02 = 2Mb SRAM PROCESS TECHNOLOGY D = 200 nm, Floating Gate Technology FLASH DENSITY 016 = 16Mb PRODUCT FAMILY S71AL Multi-chip Product (MCP) 3.0-volt Flash Memory and RAM 8 S71AL016D_02_04_00_A1 November 11, 2004 P r e l i m i n a r y Valid Combinations S71AL016D Valid Combinations Base Ordering Part Number (p)SRAM Type/Access Time (ns) Package Marking TF SRAM2/ 70 (Note 2) BF SRAM2 / 70 Package & Temperature Package Modifier/ Model Number S71AL016D02 S71AL016D02 BAW BFW S71AL016D02 S71AL016D02 T7 B7 Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. November 11, 2004 S71AL016D_02_04_00_A1 Packing Type 0, 2, 3 (Note 1) Speed Options (ns) 70 SRAM1 / 70 SRAM1 / 70 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 9 P r e l i m i n a r y Physical Dimensions TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package D1 A D eD 0.15 C (2X) 8 7 SE 7 6 5 E E1 4 3 eE 2 1 H INDEX MARK PIN A1 CORNER B 10 TOP VIEW G F E D C B A PIN A1 CORNER 7 SD 0.15 C (2X) BOTTOM VIEW 0.20 C A A2 A1 C 56X 0.08 C SIDE VIEW 6 b 0.15 M C A B 0.08 M C NOTES: PACKAGE TLC 056 JEDEC N/A DxE 9.00 mm x 7.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.20 --- --- A2 0.81 --- 0.97 NOTE PROFILE 9.00 BSC. BODY SIZE 7.00 BSC. BODY SIZE D1 5.60 BSC. MATRIX FOOTPRINT E1 5.60 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n 56 0.40 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. BALL HEIGHT E 0.35 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY THICKNESS D φb 1. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.45 eE 0.80 BSC. BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT A1,A8,D4,D5,E4,E5,H1,H8 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3348 \ 16-038.22a 10 S71AL016D_02_04_00_A1 November 11, 2004 S29AL016D 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Datasheet ADVANCE INFORMATION Distinctive Characteristics Architectural Advantages Performance Characteristics Single power supply operation High performance — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications Manufactured on 200nm process technology — Access times as fast as 70 ns Ultra low power consumption (typical values at 5 MHz) — Fully compatible with 0.23 µm Am29LV160D and MBM29LV160E devices — 200 nA Automatic Sleep mode current — 200 nA standby mode current Flexible sector architecture — 9 mA read current — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirtyone 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and thirtyone 32 Kword sectors (word mode) Sector Protection features — A hardware method of locking a sector to prevent any program or erase operations within that sector — Sectors can be locked in-system or via programming equipment — Temporary Sector Unprotect feature allows code changes in previously locked sectors Unlock Bypass Program Command — 20 mA program/erase current Cycling endurance: 1,000,000 cycles per sector typical Data retention: 20 years typical Software Features CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation — Reduces overall programming time when issuing multiple program command sequences Top or bottom boot block configurations available Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion Compatibility with JEDEC standards — Pinout and software compatible with single-power supply Flash — Superior inadvertent write protection Hardware Features Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data Publication Number S29AL016D_00 Revision A Amendment 1 Issue Date August 4, 2004 A d v a n c e I n f o r m a t i o n General Description The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 70 ns and 90 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AL016D is entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. 12 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fo wl e r -Nordheim tunneling. The data is programmed using hot electron injection. August 4, 2004 S29AL016D_00_A1_E S29AL016D 13 A d v a n c e I n f o r m a t i o n Product Selector Guide Family Part Number Speed Option S29AL016D Voltage Range: VCC = 2.7–3.6 V 70 90 Max access time, ns (tACC) 70 90 Max CE# access time, ns (tCE) 70 90 Max OE# access time, ns (tOE) 30 35 Note: See “AC Characteristics” for full specifications. Block Diagram DQ0–DQ15 (A-1) RY/BY# VCC Sector Switches VSS Erase Voltage Generator RESET# WE# BYTE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Address Latch STB Timer A0–A19 14 S29AL016D STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. S29AL016D Device Bus Operations DQ8–DQ15 Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0– DQ7 BYTE# = VIH BYTE# = VIL Read L L H H AIN DOUT DOUT Write L H L H AIN DIN DIN DQ8–DQ14 = High-Z, DQ15 = A-1 VCC ± 0.3 V X X VCC ± 0.3 V X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-Z Sector Protect (Note 2) L H L VID Sector Address, A6 = L, A1 = H, A0 = L DIN X X Sector Unprotect (Note 2) L H L VID Sector Address, A6 = H, A1 = H, A0 = L DIN X X Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/ O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control August 4, 2004 S29AL016D_00_A1_E S29AL016D 15 A d v a n c e I n f o r m a t i o n and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and 16 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. August 4, 2004 S29AL016D_00_A1_E S29AL016D 17 A d v a n c e Table 2. Sector A19 A18 I n f o r m a t i o n Sector Address Tables (Top Boot Device) A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x8) Word Mode (x16) SA0 0 0 0 0 0 X X X 64/32 000000–00FFFF 00000–07FFF SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA33 1 1 1 1 1 1 0 1 8/4 1FA000–1FBFFF FD000–FDFFF SA34 1 1 1 1 1 1 1 X 16/8 1FC000–1FFFFF FE000–FFFFF Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section. 18 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e Table 3. Sector I n f o r m a t i o n Sector Address Tables (Bottom Boot Device) A19 A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x8) Word Mode (x16) SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF SA2 0 0 0 0 0 0 1 1 8/4 006000–007FFF 03000–03FFF SA3 0 0 0 0 0 1 X X 32/16 008000–00FFFF 04000–07FFF SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA34 1 1 1 1 1 X X X 64/32 1F0000–1FFFFF F8000–FFFFF August 4, 2004 S29AL016D_00_A1_E S29AL016D 19 A d v a n c e I n f o r m a t i o n Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. Table 4. Description Mode CE# S29AL016D Autoselect Codes (High Voltage Method) A19 A11 to to OE# WE# A12 A10 Manufacturer ID: Spansion L L H Device ID: S29AL016D (Top Boot Block) Word L L H Byte L L H Device ID: S29AL016D (Bottom Boot Block) Word L L H Byte L L H Sector Protection Verification L L H A9 A8 to A7 A6 A3 to A2 A1 A0 DQ8 to DQ15 DQ7 to DQ0 X 01h 22h C4h X C4h 22h 49h X 49h X 01h (protected) X 00h (unprotected) X X VID X L L L L X X VID X L L L H X X SA X VID VID X X L L L L L H H L L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact a Spansion representative for details. 20 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Details on this method are provided in a supplement, publication number 21468. Contact a Spansion representative to request a copy. Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. shows the algorithm, and Figure 22 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. August 4, 2004 S29AL016D_00_A1_E Temporary Sector Unprotect Operation S29AL016D 21 A d v a n c e I n f o r m a t i o n START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 4 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 4 µs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Unprotect Mode Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Wait 100 µs Increment PLSCNT No Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Reset PLSCNT = 1 Wait 1.2 ms Read from sector address with A7-A0 = 00000010 Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Increment PLSCNT No No PLSCNT = 25? Yes Yes Remove VID from RESET# No Yes PLSCNT = 1000? Protect another sector? No Write reset command Remove VID from RESET# Sector Protect complete Write reset command Sector Protect complete Write reset command Set up next sector address No Data = 00h? Yes Yes Remove VID from RESET# Device failed Read from sector address with A7-A0 = 00000010 Data = 01h? Last sector verified? No Yes Remove VID from RESET# Sector Unprotect complete Write reset command Sector Protect Algorithm Device failed Sector Unprotect complete Sector Unprotect Algorithm Figure 2. 22 In-System Sector Protect/Unprotect Algorithms S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5–8. In word mode, the upper address bits (A7– MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/ overview/cfi.html. Alternatively, contact a Spansion representative for copies of these documents. Table 5. CFI Query Identification String Addresses (Word Mode) Addresses (Byte Mode) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) August 4, 2004 S29AL016D_00_A1_E Description S29AL016D 23 A d v a n c e Table 6. I n f o r m a t i o n System Interface String Addresses (Word Mode) Addresses (Byte Mode) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Table 7. Description Device Geometry Definition Addresses (Word Mode) Addresses (Byte Mode) Data 27h 4Eh 0015h Device Size = 2 byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0000h 0000h 0040h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0080h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 001Eh 0000h 0000h 0001h Erase Block Region 4 Information 24 Description N S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e Table 8. I n f o r m a t i o n Primary Vendor-Specific Extended Query Addresses (Word Mode) Addresses (Byte Mode) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h 88h 0030h Minor version number, ASCII 45h 8Ah 0000h Address Sensitive Unlock 0 = Required, 1 = Not Required 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported, 01 = Supported 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Description Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. August 4, 2004 S29AL016D_00_A1_E S29AL016D 25 A d v a n c e I n f o r m a t i o n Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. 26 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. August 4, 2004 S29AL016D_00_A1_E S29AL016D 27 A d v a n c e I n f o r m a t i o n Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence. 28 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams. START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed NOTE: See Table 9 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 shows the address and data requirements for the chip erase command sequence. August 4, 2004 S29AL016D_00_A1_E S29AL016D 29 A d v a n c e I n f o r m a t i o n Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to “Write Operation Status” for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams. 30 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. August 4, 2004 S29AL016D_00_A1_E S29AL016D 31 A d v a n c e I n f o r m a t i o n START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See Table 9 for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Figure 4. 32 Erase Operation S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Command Definitions Table 9. Read (Note 6) Autoselect (Note 8) Reset (Note 7) Manufacturer ID Device ID, Top Boot Block Device ID, Bottom Boot Block Sector Protect Verify (Note 9) CFI Query (Note 10) Program Unlock Bypass Word Byte Word Byte Word Byte Bus Cycles (Notes 2–5) Cycles Command Sequence (Note 1) Addr Data 1 RA RD 1 XXX F0 4 4 4 Word First 555 AAA 555 AAA 555 AAA AAA Word 55 Word Byte AA AA AA 1 4 3 Addr 2AA 555 2AA 555 2AA 555 AA 555 AAA 555 AAA Data 55 55 55 2AA AA Byte Byte Second 555 4 Byte Word S29AL016D Command Definitions 555 AA AA 2AA 555 2AA 555 55 55 XXX A0 PA PD XXX 90 XXX F0 Sector Erase Word Byte 6 6 AAA Data 90 X00 01 X01 22C4 X02 X01 C4 2249 90 90 90 X02 49 (SA) X02 XX00 (SA) X04 00 PA PD Fifth Addr Sixth Data Addr Data XX01 01 98 2 Byte AAA Addr AAA 2 Chip Erase 555 AAA 555 Fourth Data 555 Unlock Bypass Reset (Note 12) 555 555 AAA 55 Unlock Bypass Program (Note 11) Word Third Addr AA 555 AAA AA Erase Suspend (Note 13) 1 XXX B0 Erase Resume (Note 14) 1 XXX 30 2AA 555 2AA 555 55 55 555 AAA 555 AAA 555 AAA 555 AAA A0 20 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. Note: 1. 2. See Table 1 for description of bus operations. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles. 5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 10. Command is valid when device is ready to read array data or when device is in autoselect mode. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode. August 4, 2004 S29AL016D_00_A1_E S29AL016D 33 A d v a n c e I n f o r m a t i o n Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms), in the “AC Characteristics” section illustrates this. Table 10 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm. 34 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n START Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No PASS FAIL Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because Figure 5. Data# Polling Algorithm RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. August 4, 2004 S29AL016D_00_A1_E S29AL016D 35 A d v a n c e I n f o r m a t i o n If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6. 36 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). August 4, 2004 S29AL016D_00_A1_E S29AL016D 37 A d v a n c e I n f o r m a t i o n START Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA (Note 1) No Toggle Bit = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice (DQ7–DQ0) Address = VA (Notes 1,2) Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Figure 6. Toggle Bit Algorithm DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. 38 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also the “Sector Erase Command Sequence” section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 shows the outputs for DQ3. Table 10. DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0 Operation Standard Mode Erase Suspend Mode Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. August 4, 2004 S29AL016D_00_A1_E S29AL016D 39 A d v a n c e I n f o r m a t i o n Absolute Maximum Ratings Storage Temperature Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . –0.5 V to +12.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns +0.8 V 20 ns VCC +2.0 V VCC +0.5 V –0.5 V –2.0 V 2.0 V 20 ns Figure 7. Maximum Negative Overshoot Waveform 20 ns Figure 8. Maximum Positive Overshoot Waveform Operating Ranges Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C VCC Supply Voltages VCC for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 40 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n DC Characteristics CMOS Compatible Parameter Description Test Conditions ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, Byte Mode ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Word Mode Min Typ Max Unit ±1.0 µA 35 µA ±1.0 µA 10 MHz 15 30 5 MHz 9 16 1 MHz 2 4 10 MHz 18 35 5 MHz 9 16 1 MHz 2 4 20 35 mA mA ICC2 VCC Active Write Current (Notes 2, 3, 5) ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA ICC4 VCC Standby Current During Reset RESET# = VSS ± 0.3 V (Notes 2, 4) 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4, 6) 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 VOH2 VLKO Output High Voltage CE# = VIL, OE# = VIH VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V IOH = -2.0 mA, VCC = VCC min 2.4 V IOH = -100 µA, VCC = VCC min VCC–0.4 V Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested. August 4, 2004 S29AL016D_00_A1_E S29AL016D 41 A d v a n c e I n f o r m a t i o n DC Characteristics (continued) Zero Power Flash Supply Current in mA 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1 MHz Figure 9. 42 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n 10 3.6 V Supply Current in mA 8 2.7 V 6 4 2 0 1 2 3 4 5 Frequency in MHz Note: T = 25 °C Figure 10. August 4, 2004 S29AL016D_00_A1_E Typical ICC1 vs. Frequency S29AL016D 43 A d v a n c e I n f o r m a t i o n Test Conditions 3.3 V 2.7 kΩ Device Under Test CL 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 11. Table 11. Test Setup Test Specifications Test Condition 70 Output Load Unit 1 TTL gate Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times 30 100 pF 5 ns 0.0 or VCC V Input timing measurement reference levels 0.5 VCC V Output timing measurement reference levels 0.5 VCC V Input Pulse Levels 44 90 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H VCC Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 0.5 VCC Measurement Level 0.5 VCC Output 0.0 V Figure 12. August 4, 2004 S29AL016D_00_A1_E Input Waveforms and Measurement Levels S29AL016D 45 A d v a n c e I n f o r m a t i o n AC Characteristics Read Operations Parameter Speed Options JEDEC Std Description tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE tEHQZ tGHQZ tAXQX Test Setup 70 90 Unit Min 70 90 ns CE# = VIL OE# = VIL Max 70 90 ns OE# = VIL Max 70 90 ns Output Enable to Output Delay Max 30 35 ns tDF Chip Enable to Output High Z (Note 1) Max 25 30 ns tDF Output Enable to Output High Z (Note 1) Max 25 30 ns Read Output Enable Hold Time (Note 1) Toggle and Data# Polling Min 0 ns tOEH Min 10 ns tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns Notes: 1. Not 100% tested. 2. See Figure 11 and Table 11 for test specifications. tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 13. 46 Read Operations Timings S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 14. August 4, 2004 S29AL016D_00_A1_E RESET# Timings S29AL016D 47 A d v a n c e I n f o r m a t i o n AC Characteristics Word/Byte Configuration (BYTE#) Parameter JEDEC Std Speed Options Description 70 90 5 Unit tELFL/tELFH CE# to BYTE# Switching Low or High Max ns tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 30 ns tFHQV BYTE# Switching High to Output Active Min 70 90 ns CE# OE# BYTE# BYTE# Switching from word to byte mode DQ0–DQ14 tELFL Data Output (DQ0–DQ14) Data Output (DQ0–DQ7) Address Input DQ15 Output DQ15/A-1 tFLQZ tELFH BYTE# BYTE# Switching from byte to word mode DQ0–DQ14 Data Output (DQ0–DQ7) Address Input DQ15/A-1 Data Output (DQ0–DQ14) DQ15 Output tFHQV Figure 15. 48 BYTE# Timings for Read Operations S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. August 4, 2004 S29AL016D_00_A1_E BYTE# Timings for Write Operations S29AL016D 49 A d v a n c e I n f o r m a t i o n AC Characteristics Erase/Program Operations Parameter Speed Options JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 45 45 ns tDVWH tDS Data Setup Time Min 35 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 30 tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Max 90 ns tBUSY 70 90 Unit 70 90 ns 0 35 ns 35 ns ns µs Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 50 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n AC Characteristics Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. August 4, 2004 S29AL016D_00_A1_E Program Operation Timings S29AL016D 51 A d v a n c e I n f o r m a t i o n AC Characteristics Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h 30h Status DOUT 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). 2. Illustration shows device in word mode. Figure 18. 52 Chip/Sector Erase Operation Timings S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n AC Characteristics tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ6–DQ0 Status Data Status Data Valid Data True High Z Valid Data True tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 19. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ6/DQ2 tBUSY Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. August 4, 2004 S29AL016D_00_A1_E Toggle Bit Timings (During Embedded Algorithms) S29AL016D 53 A d v a n c e I n f o r m a t i o n AC Characteristics Enter Embedded Erasing Erase Suspend Erase WE# Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Suspend Read Erase Complete DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations Temporary Sector Unprotect Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: Not 100% tested. 12 V RESET# 0 or 3 V tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP RY/BY# Figure 22. 54 Temporary Sector Unprotect/Timing Diagram S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n AC Characteristics VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Group Protect/Unprotect Data 60h Valid* Verify 60h 40h Status 1 µs Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms CE# WE# OE# Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 23. August 4, 2004 S29AL016D_00_A1_E Sector Protect/Unprotect Timing Diagram S29AL016D 55 A d v a n c e I n f o r m a t i o n AC Characteristics Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std Description 70 90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 45 45 ns tDVEH tDS Data Setup Time Min 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min tEHEL tCPH CE# Pulse Width High Min 30 tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 0 35 ns 35 ns ns µs sec Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 56 S29AL016D S29AL016D_00_A1_E August 4, 2004 A d v a n c e I n f o r m a t i o n AC Characteristics 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE# tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example. Figure 24. August 4, 2004 S29AL016D_00_A1_E Alternate CE# Controlled Write Operation Timings S29AL016D 57 A d v a n c e I n f o r m a t i o n Erase and Programming Performance Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 10 s Chip Erase Time 25 Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 5 150 µs Word Programming Time 7 210 µs Chip Programming Time Byte Mode 11 33 s (Note 3) Word Mode 7.2 21.6 s s Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. TSOP and BGA Pin Capacitance Parameter Symbol Parameter Description Test Setup CIN Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 Package Typ Max Unit TSOP 6 7.5 pF BGA 4.2 5.0 pF TSOP 8.5 12 pF BGA 5.4 6.5 pF TSOP 7.5 9 pF BGA 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. 58 S29AL016D S29AL016D_00_A1_E August 4, 2004 P r e l i m i n a r y 2Mbit Type 1 SRAM Common Features Single Wide Power Supply Range 2.3 to 3.6 Volts Very low standby current 2.0µA at 3.0V (Typical) Very low operating current 2.0mA at 3.0V and 1µs (Typical) Very low Page Mode operating current 0.8mA at 3.0V and 1µs (Typical) Simple memory control Dual Chip Enables (CE1# and CE2) Byte control for independent byte operation Output Enable (OE#) for memory expansion Low voltage data retention VCC = 1.8V Very fast output enable access time 30ns OE# access time Automatic power down to standby mode TTL compatible three-state output driver Tested wafers August 4, 2004 SRAM_Type01_03A0 2Mbit Type 1 SRAM 59 P r e l i m i n a r y Functional Description CE# CE2 WE# OE# UB# LB# IO0~15 (Note 1) Mode Power H X X X X X High-Z Standby (Note 2) Standby X L X X X X High-Z Standby (Note 2) Standby L H X X H H High-Z Standby Standby L H L X (Note 3) L (Note 1) L (Note 1) Data In Write (Note 3) Active L H H L L (Note 1) L (Note 1) Data Out Read Active L H H H L (Note 1) L (Note 1) High-Z Active Active Notes: 1. When UB# and LB# are in select mode (low), I/O0 - I/O15 are affected as shown. When only LB# is in the select mode, only I/O0 - I/O7 are affected as shown. When UB# is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB#), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit. Capacitance Item Symbol Test Condition Input Capacitance CIN I/O Capacitance CI/O Min Max Unit VIN = 0V, f = 1 MHz, TA = 25°C 8 pF VIN = 0V, f = 1 MHz, TA = 25°C 8 pF Note: These parameters are verified in device characterization and are not 100% tested. Absolute Maximum Ratings Item Symbol Ratings Unit VIN,VOUT –0.3 to VCC + 0.3 V Voltage on VCC supply relative to VSS VCC -0.3 to 4.5V V Power Dissipation PD 500 W TSTG –40 to 125 °C TA -40 to 85 °C TSOLDER 240°C, 10sec (Lead only) °C Voltage on any pin relative to VSS Storage Temperature Operating Temperature Soldering Temperature and Time Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 60 2Mbit Type 1 SRAM SRAM_Type01_03A0 August 4, 2004 P r e l i m i n a r y Operating Characteristics (Over Specified Temperature Range) Item Symbol Supply Voltage VCC Data Retention Voltage VDR Input High Voltage Test Conditions Type (Note1) Max 2.3 3.0 3.6 1.8 3.6 VIH 1.8 VCC + 0.3 Input Low Voltage VIL -0.3 0.6 Output High Voltage VOH IOH = 0.2mA Output Low Voltage VOL IOL = -0.2mA 0.2 Input Leakage Current ILI VIN = 0 to VCC 0.5 Output Leakage Current ILO OE# = VIH or Chip Disabled 0.5 Read/Write Operating Supply Current at 1 µs Cycle Time (Note 2) ICC1 VCC = 3.6 V, VIN = VIH or VIL Chip Enabled, IOUT = 0 2.0 4.0 Read/Write Operating Supply Current at 70 ns Cycle Time (Note 2) ICC2 VCC = 3.6 V, VIN = VIH or VIL Chip Enabled, IOUT = 0 12.0 16.0 Page Mode Operating Supply Current at 70ns Cycle Time (Note 2) (Figure 1) ICC3 VCC = 3.6 V, VIN = VIH or VIL Chip Enabled, IOUT = 0 4.0 Read/Write Quiescent Operating Supply Current (Note 3) ICC4 VCC = 3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f = 0 Maximum Standby Current (Note 3) ISB1 VIN = VCC or 0V Chip Disabled tA = 85°C, VCC = 3.6 V IDR VCC = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85°C Maximum Data Retention Current (Note 3) Chip Disabled (Note 3) Min Unit V VCC - 0.2 µA mA 3.0 2.0 20.0 µΑ 10.0 Notes: 1. Typical values are measured at VCC = VCC Typ., TA = 25°C and is not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1# high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. August 4, 2004 SRAM_Type01_03A0 2Mbit Type 1 SRAM 61 P r e l i m i n a r y Page Address (A4 -A16) Open page Word Address (A0 -A3) Word 1 Word 2 ... Word 16 CE1# CE2 OE# LB#, UB# Figure 1. Power Savings with Page Mode (WE# = VIH) Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels Output Load CL = 30pF Operating Temperature 62 0.5 VCC -40 to +85°C 2Mbit Type 1 SRAM SRAM_Type01_03A0 August 4, 2004 P r e l i m i n a r y Timing 2.3 - 3.6 V Item Symbol Min Read Cycle Time tRC 70 Address Access Time tAA 70 Chip Enable to Valid Output tCO 70 Output Enable to Valid Output tOE 35 tLB, tUB 70 Byte Select to Valid Output Max Chip Enable to Low-Z output tLZ 10 Output Enable to Low-Z Output tOLZ 5 tLBLZ, tUBLZ 10 Chip Disable to High-Z Output tHZ 0 20 Output Disable to High-Z Output tOHZ 0 20 tLBHZ, tUBHZ 0 20 Output Hold from Address Change tOH 10 Write Cycle Time tWC 70 Chip Enable to End of Write tCW 50 Address Valid to End of Write tAW 50 tLBW, tUBW 50 Write Pulse Width tWP 40 Address Setup Time tAS 0 Write Recovery Time tWR 0 Write to High-Z Output tWHZ Data to Write Time Overlap tDW 40 Data Hold from Write Time tDH 0 End Write to Low-Z Output tOW 10 Byte Select to Low-Z Output Byte Select Disable to High-Z Output Byte Select to End of Write August 4, 2004 SRAM_Type01_03A0 2Mbit Type 1 SRAM Units ns 20 63 P r e l i m i n a r y Timing Diagrams tRC Address tAA tOH Data Out Data Valid Previous Data Valid Figure 2. Timing of Read Cycle (CE# = OE# = VIL, WE# = CE2= VIH) tRC Address tAA tHZ CE1# tCO CE2 tLZ tOHZ tOE OE# tOLZ tLB, tUB LB#, UB# tLBLZ, tUBLZ Data Out High-Z Figure 3. 64 tLBHZ, tUBHZ Data Valid Timing Waveform of Read Cycle (WE# = VIH) 2Mbit Type 1 SRAM SRAM_Type01_03A0 August 4, 2004 P r e l i m i n a r y tWC Address tWR tAW CE1# tCW CE2 tLBW, t UBW LB#, UB# tAS tWP WE# tDW Data In High-Z tDH Data Valid tWHZ tOW High-Z Data Out Figure 4. Timing Waveform of Write Cycle (WE# Control) tWC Address tAW CE1# (for CE2 Control, use inverted signal) tWR tCW tAS tLBW, tUBW LB#, UB# tWP WE# tDW Data Valid Data In tLZ tWHZ Data Out Figure 5. August 4, 2004 SRAM_Type01_03A0 tDH High-Z Timing Waveform of Write Cycle (CE1# Control) 2Mbit Type 1 SRAM 65 P r e l i m i n a r y 2Mbit Type 2 SRAM 128K x 16 Static RAM Common Features High Speed — 55ns and 70ns availability Ultra-low active power — Typical active current: 1.5 mA @ f = 1MHz — Typical active current: 7 mA @ f = fmax (70ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power Functional Description The 2Mbit Type 2 SRAM is a family of high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE# High). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE# High), outputs are disabled (OE# High), both Byte High Enable and Byte Low Enable are disabled (BHE#, BLE# High), or during a write operation (CE# Low, and WE# Low). Writing to the device is accomplished by taking Chip Enable (CE#) and Write Enable (WE#) inputs Low. If Byte Low Enable (BLE#) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE#) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE#) and Output Enable (OE#) Low while forcing the Write Enable (WE#) High. If Byte Low Enable (BLE#) is Low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE#) is Low, then data from memory will appear on I/O8 to I/O15. See Table 1 for a complete description of read and write modes. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55°C to +125°C Supply Voltage to Ground Potential . . . . . . . . . . . . . . -0.5V to VCCmax + 0.5V DC Voltage Applied to Outputs in High-Z State (note 2) . . -0.5V to VCC + 0.5V DC Input Voltage (note 2) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V Output Current into Outputs (Low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA 66 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004 P r e l i m i n a r y Operating Range Range Ambient Temperature VCC Industrial -40°C to +85°C 2.7V to 3.3V Product Portfolio Power Dissipation (Industrial) Operating, ICC VCC Range f = 1 MHz VCC (min) VCC (typ.) (note 2) VCC (max) 2.7V 3.0V 3.3V f = fmax Standby (ISB2) Speed Typ. (note 2) Max Typ. (note 2) Max 55 ns 1.5 mA 3 mA 12 mA 25 mA 70 ns 1.5 mA 3 mA 7 mA 15 mA Typ. (note 2) Max 2 µA 10 µA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Electrical Characteristics Voltage Range 2.7V - 3.3V Parameter Description Test Conditions Min. Typ. (note 1) Max VOH Output High Voltage IOH = –1.0 mA VCC = 2.7V VOL Output Low Voltage IOL = 2.1mA VCC = 2.7V VIH Input High Voltage 2.2 VCC + 0.3V VIL Input Low Voltage -0.3 0.8 IIX Input Leakage Current GND < VI < VCC -1 +1 IOZ Output Leakage Current GND < VO < VCC, Output Disabled -1 +1 ICC VCC Operating Supply Current ISB1 Automatic CE Power-Down Current—CMOS Inputs CE# ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = fmax (Address and Data Only), f=0 (OE#, WE#, BHE# and BLE#) Automatic CE Power-Down Current—CMOS Inputs CE# ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0, VCC = 3.3V ISB2 f = fMAX = 1/tRC f = 1 MHz VCC = 3.3V IOUT = 0 mA CMOS Levels Unit 2.4 0.4 7 15 1.5 3 2 10 V µA mA µA Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. August 4, 2004 SRAM_Type04_04A0 2Mbit Type 2 SRAM 67 P r e l i m i n a r y Capacitance Parameter CIN COUT Description Test Condition Max Input Capacitance TA = 25°C, f = 1 MHz, VCC = VCC(typ.) 6 Output Capacitance Unit pF 8 Note: Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES VCC Typ OUTPUT GND Rise Time: 1 V/ns R2 30 pF 90% 10% 90% 10% Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉ VENIN EQUIVALENT RTH OUTPUT Figure 1. VTH AC Test Loads and Waveforms Parameters 2.5V 3.0V 3.3V R1 16.6 1.105 1.216 R2 15.4 1.550 1.374 RTH 8 0.645 0.645 VTH 1.20 1.75 1.75 Unit K Ohms Volts Data Retention Characteristics (Over the Operation Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR (note 2) Chip Deselect to Data Retention Time tR (note 3) Operation Recovery Time Min. Typ (note 1) 1.5 VCC = 1.5V CE# ≥ VCC – 0.2V 1 Max. Unit VCCMAX V 4 µA 0 ns tRC Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 2. Tested initially and after any design or process changes that may affect these parameters. 3. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 ms or stable at VCC(min.) > 100 ms. 68 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004 P r e l i m i n a r y VCC VCC(min) DATA RETENTION MODE VDR > 1.5 V tCDR VCC(min) tR CE# or BHE#.BLE# Figure 2. Data Retention Waveform Note: BHE#.BLE# is the AND of both BHE# and BLE#. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE# and BLE#. August 4, 2004 SRAM_Type04_04A0 2Mbit Type 2 SRAM 69 P r e l i m i n a r y Switching Characteristics Parameter Description 55 ns Min 70 ns Max Min Max Unit Read Cycle tRC Read Cycle Time 55 70 tAA Address to Data Valid tOHA Data Hold from Address Change 55 tACE CE# Low to Data Valid 55 70 tDOE OE# Low to Data Valid 25 35 tLZOE OE# Low to Low Z (note 2) tHZOE OE# High to High Z (note 2, 4) tLZCE CE# Low to Low Z (note 2) tHZCE CE# High to High Z (note 2, 4) tPU CE# Low to Power-Up tPD CE# High to Power-Down 55 70 tDBE BHE# / BLE# Low to Data Valid 55 70 tLZBE (note 3) BHE# / BLE# Low to Low Z (note 2) tHZBE BHE# / BLE# High to High Z (note 2, 4) 10 70 10 5 5 20 10 25 10 20 0 ns 25 0 5 5 20 25 Write Cycle (note 5) tWC Write Cycle Time 55 70 tSCE CE# Low to Write End 45 60 tAW Address Set-Up to Write End 45 60 tHA Address Hold from Write End 0 0 tSA Address Set-Up to Write Start 0 0 tPWE WE# Pulse Width 45 50 tBW BHE# / BLE# Pulse Width 50 60 tSD Data Set-Up to Write End 25 30 tHD Data Hold from Write End 0 0 tHZWE WE# Low to High Z (note 2, 4) tLZWE WE# High to Low Z (note 2) 20 5 ns 25 5 Notes: 1. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 3. If both byte enables are toggled together this value is 10ns. 4. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 5. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 70 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004 P r e l i m i n a r y Switching Waveforms tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Figure 3. Read Cycle 1 (Address Transition Controlled) Notes: 1. Device is continuously selected. OE#, CE# = VIL, BHE#, BLE# = VIL. 2. WE# is High for read cycle. ADDRESS tRC CE# t PD tHZCE tACE OE# BHE#/BLE# ttLZOE LZOE t HZOE tDOE tHZBE tLZBE DATA OUT tDBE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% Figure 4. ICC ISB Read Cycle 2 (OE# Controlled) Notes: 1. WE# is High for read cycle. 2. Address valid prior to or coincident with CE#, BHE#, BLE# transition Low. August 4, 2004 SRAM_Type04_04A0 2Mbit Type 2 SRAM 71 P r e l i m i n a r y tWC ADDRESS tS C E CE# tAW tHA tSA tPWE WE# tBW BHE#/BLE# OE# tSD DATA I/O tHD DATA IN VALID NOTE 4 tHZOE Figure 5. Write Cycle 1 (WE# Controlled) Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 2. Data I/O is high-impedance if OE# = VIH. 3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 4. During this period, the I/Os are in output state and input signals should not be applied. 72 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004 P r e l i m i n a r y tWC ADDRESS tSCE CE# tSA tAW tHA tPWE WE# tBW BHE#/BLE# OE# tSD DATA I/O tHD DATA IN VALID NOTE 4 t HZOE Figure 6. Write Cycle 2 (CE# Controlled) Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 2. Data I/O is high-impedance if OE# = VIH. 3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 4. During this period, the I/Os are in output state and input signals should not be applied. tWC ADDRESS tS C E CE# t BW BHE#/BLE# tAW tSA tHA tPWE WE# tSD DATAI/O NOTE 2 tH D DATA IN VALID tLZWE tHZWE Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW) Notes: 1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 2. During this period, the I/Os are in output state and input signals should not be applied. August 4, 2004 SRAM_Type04_04A0 2Mbit Type 2 SRAM 73 P r e l i m i n a r y tWC ADDRESS CE# tS C E tAW tHA tBW BHE#/BLE# tSA tPWE WE# tSD DATA I/O DATAIN VALID NOTE 2 Figure 8. tHD Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) Notes: 1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 2. During this period, the I/Os are in output state and input signals should not be applied. Typical DC and AC Parameters 14.0 (f = max f , 55ns) ICC (mA) 12.0 10.0 8.0 MoBL (f = max f , 70ns) 6.0 4.0 2.0 (f = 1 MHz) 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) Figure 9. Operating Current vs. Supply Voltage ISB (mA) 12.0 10.0 MoBL 8.0 6.0 4.0 2.0 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) Figure 10. 74 Standby Current vs. Supply Voltage 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004 P r e l i m i n a r y 60 MoBL 50 T AA (ns) 40 30 20 10 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) Figure 11. Access Time vs. Supply Voltage Truth Table Table 1. CE# WE# OE# BHE# BLE# Truth Table Inputs / Outputs Mode H X X X X High-Z Deselect/Power-Down L X X H H High-Z Output Disabled L H L L L Data Out (I/OO–I/O15) Read L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read L H H L L High-Z Output Disabled L H H H L High-Z Output Disabled L H H L H High-Z Output Disabled L L X L L Data In (I/OO–I/O15) Write L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write August 4, 2004 SRAM_Type04_04A0 2Mbit Type 2 SRAM Power Standby (ISB) Active (ICC) 75 A d v a n c e I n f o r m a t i o n Revision Summary Revision A (September 27, 2004) Initial release. Revision A+1 (November 11, 2004) Deleted parameter "tOES" at page 50,56. Changed the symbol of " tLBZ, tUBZ" to " tLBLZ, tUBLZ" at page 63. Trademarks and Notice The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004 Spansion LLC. All rights reserved. SpansionTM, the SpansionTM logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 76 Revision Summary S71AL016D_02_04_00_A0 November 11, 2004