INFINEON SAF-XC886LM-8FFI

Data Sheet, V0.1, Feb. 2006
XC886/888CLM
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8-Bit Single-Chip Microcontroller
Microcontrollers
Edition 2006-02
Published by Infineon Technologies AG,
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V0.1, Feb. 2006
ar
y
XC886/888CLM
P
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in
8-Bit Single-Chip Microcontroller
Microcontrollers
XC886/888 Data Sheet
Revision History:
2006-02
V0.1
Previous Version:
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8-Bit Single-Chip Microcontroller
1
XC886/888
Summary of Features
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 12 Kbytes of Boot ROM
– 256 bytes of RAM
– 1.5 Kbytes of XRAM
– 24/32 Kbytes of Flash; or
24/32 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
• I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
(more features on next page)
Flash or ROM1)
24K/32K x 8
On-Chip Debug Support
Boot ROM
12K x 8
UART
SSC
Port 0
8-bit Digital I/O
Capture/Compare Unit
16-bit
Port 1
8-bit Digital I/O
Compare Unit
16-bit
Port 2
8-bit Digital/
Analog Input
XC800 Core
.
XRAM
1.5K x 8
RAM
256 x 8
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
Watchdog
Timer
ADC
10-bit
8-channel
Port 3
8-bit Digital I/O
MDU
CORDIC
MultiCAN
Timer 21
16-bit
UART1
Port 5
Port 4
8-bit Digital I/O
1) All ROM devices come with an additional 4K x 8 Flash
Figure 1
Data Sheet
Prelimary
8-bit Digital I/O
XC886/888 Functional Units
1
V0.1, 2006-02
XC886/888CLM
Summary of Features
Features (continued):
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Six ports
– 34/48 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Four 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
– Timer 2 and Timer 21
• Multiplication/Division Unit for arithmetic operations (MDU)
• CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear
functions
• MultiCAN with 2 nodes, 32 message objects (MCAN)
• Capture/compare unit for PWM signal generation (CCU6)
• Two full-duplex serial interfaces (UART and UART1)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM)
– 64 bytes of monitor RAM
• Packages:
– PG-TQFP-48
– PG-TQFP-64
• Temperature range TA:
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
Data Sheet
Prelimary
2
V0.1, 2006-02
XC886/888CLM
Summary of Features
XC886/888 Variant Devices
The XC886/888 product family features devices with different configurations, program
memory sizes, package options, temperature and quality profiles (Automotive or
Industrial), to offer cost-effective solutions for different application requirements.
The list of XC886/888 device configurations are summarized in Table 1. For each
configuration, 2 types of packages are available:
• PG-TQFP-48, which is denoted by XC886 and;
• PG-TQFP-64, which is denoted by XC888.
Table 1
Device Configuration
Device Name
CAN
Module
LIN BSL
Support
MDU
Module
XC886/888
No
No
No
XC886/888C
Yes
No
No
XC886/888CM
Yes
No
Yes
XC886/888LM
No
Yes
Yes
XC886/888CLM
Yes
Yes
Yes
From these 10 different combinations of configuration and package type, each are
further made available in 6 sales types, which are grouped according to program
memory sizes, temperature and quality profiles (Automotive or Industrial), as shown in
Table 2.
Table 2
Device Profile
Sales Type
Device
Type
Program Memory Temperature Quality
Size (Kbytes)
Profile (°C) Profile
SAK-XC886*/888*-8FFA
Flash
32
-40 to 125
Automotive
SAK-XC886*/888*-6FFA
Flash
24
-40 to 125
Automotive
SAF-XC886*/888*-8FFA
Flash
32
-40 to 85
Automotive
SAF-XC886*/888*-6FFA
Flash
24
-40 to 85
Automotive
SAF-XC886*/888*-8FFI
Flash
32
-40 to 85
Industrial
SAF-XC886*/888*-6FFI
Flash
24
-40 to 85
Industrial
Note: The asterisk (*) above denotes the device configuration letters from Table 1.
Corresponding ROM derivatives will be available on request.
Data Sheet
Prelimary
3
V0.1, 2006-02
XC886/888CLM
Summary of Features
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code indentifies:
• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery
For the available ordering codes for the XC886/888, please refer to the “Product
Catalog Microcontrollers” which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet
Prelimary
4
V0.1, 2006-02
XC886/888CLM
General Device Information
2
General Device Information
2.1
Block Diagram
XC886/888
T0 & T1
UART
CORDIC
UART1
MDU
SSC
WDT
Timer 2
1.5-Kbyte XRAM
24/32-Kbyte
Flash or ROM 2)
Port 0
TMS
MBC
RESET
VDDP
VSSP
VDDC
VSSC
256-byte RAM
+
64-byte monitor
RAM
P0.0 - P0.7
Port 1
XC800 Core
P1.0 - P1.7
Port 2
Internal Bus
12-Kbyte
Boot ROM1)
P2.0 - P2.7
ADC
CCU6
Port 3
Timer 21
9.6 MHz
On-chip OSC
P3.0 - P3.7
Port 4
OCDS
VAREF
VAGND
P4.0 - P4.7
Port 5
XTAL1
XTAL2
Clock Generator
P5.0 - P5.7
PLL
MCAN
1) Includes 1-Kbyte monitor ROM
2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash
Figure 2
Data Sheet
Prelimary
XC886/888 Block Diagram
5
V0.1, 2006-02
XC886/888CLM
General Device Information
2.2
Logic Symbol
VDDP
VDDP
VSSP
VSSP
Port 0 8-Bit
VAREF
VAREF
Port 0 7-Bit
VAGND
Port 1 8-Bit
VAGND
Port 1 8-Bit
RESET
XC886
MBC
TMS
Port 2 8-Bit
RESET
Port 2 8-Bit
MBC
Port 3 8-Bit
Port 4 8-Bit
XTAL1
Port 4 3-Bit
XTAL2
VDDC
Data Sheet
Prelimary
Port 3 8-Bit
TMS
XTAL1
Figure 3
XC888
XTAL2
VSSC
Port 5 8-Bit
VDDC
VSSC
XC886/888 Logic Symbol
6
V0.1, 2006-02
XC886/888CLM
General Device Information
P2.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P4.3
P3.6
P3.7
P3.0
Pin Configuration
P3.1
2.3
36 35 34 33 32 31 30 29 28 27 26 25
P3.2
37
24
V AREF
P3.3
38
23
V AGND
P3.4
39
22
P2.6
P3.5
40
21
P2.5
RESET
41
20
P2.4
V SSP
42
19
P2.3
V DDP
43
18
V SSP
MBC
44
17
V DDP
P4.0
45
16
P2.2
XC886
P4.1
46
15
P2.1
P0.7
47
14
P2.0
P0.3
48
13
P0.1
VSSC
VDDC
9
10 11 12
P0.2
XTAL1
8
P0.0
XTAL2
7
TMS
6
P1.7
5
P1.6
4
VDDP
3
P0.5
Data Sheet
Prelimary
2
P0.4
Figure 4
1
XC886 Pin Configuration, PG-TQFP-48 Package (top view)
7
V0.1, 2006-02
XC886/888CLM
P2.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P4.3
P3.6
P3.7
P3.0
P3.1
P4.4
P4.5
P4.6
P4.7
General Device Information
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P3.2
49
32
V AREF
P3.3
50
31
V AGND
P3.4
51
30
P2.6
P3.5
52
29
P2.5
RESET
53
28
P2.4
V SSP
54
27
P2.3
V DDP
55
26
V SSP
NC
56
25
V DDP
NC
57
MBC
XC888
24
P2.2
58
23
P2.1
P4.0
59
22
P2.0
P4.1
60
21
P0.1
P4.2
61
20
P5.7
P0.7
62
19
P5.6
P0.3
63
18
P0.2
P0.4
64
17
P0.0
P0.5
P0.6
XTAL2
XTAL1
VSSC
VDDC
VDDP
P5.0
9
10 11 12 13 14 15 16
TMS
8
P5.5
7
P5.4
6
P5.3
5
P5.2
4
P1.7
3
P1.6
2
P5.1
1
Note: The pins shaded in blue are not available in the PG-TQFP-48 package.
Figure 5
Data Sheet
Prelimary
XC888 Pin Configuration, PG-TQFP-64 Package (top view)
8
V0.1, 2006-02
XC886/888CLM
General Device Information
2.4
Pin Definitions and Functions
Table 3
Pin Definitions and Functions
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P0
I/O
Port 0
Port 0 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, UART1, Timer 2,
Timer 21, MCAN and SSC.
P0.0
11/17
Hi-Z
TCK_0
T12HR_1
JTAG Clock Input
CCU6 Timer 12 Hardware Run
Input
CC61_1
Input/Output of Capture/
Compare channel 1
CLKOUT_0 Clock Output
RXDO_1
UART Transmit Data Output
P0.1
13/21
Hi-Z
TDI_0
T13HR_1
P0.2
12/18
PU
CTRAP_2
TDO_0
TXD_1
JTAG Serial Data Input
CCU6 Timer 13 Hardware Run
Input
RXD_1
UART Receive Data Input
RXDC1_0
MCAN Node 1 Receiver Input
COUT61_1 Output of Capture/Compare
channel 1
EXF2_1
Timer 2 External Flag Output
TXDC1_0
P0.3
48/63
Data Sheet
Prelimary
Hi-Z
CCU6 Trap Input
JTAG Serial Data Output
UART Transmit Data Output/
Clock Output
MCAN Node 1 Transmitter
Output
SCK_1
SSC Clock Input/Output
COUT63_1 Output of Capture/Compare
channel 3
RXDO1_0 UART1 Transmit Data Output
9
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P0.4
1/64
Hi-Z
MTSR_1
CC62_1
TXD1_0
SSC Master Transmit Output/
Slave Receive Input
Input/Output of Capture/
Compare channel 2
UART1 Transmit Data Output/
Clock Output
P0.5
2/1
Hi-Z
MRST_1
P0.6
–/2
PU
GPIO
P0.7
47/62
PU
CLKOUT_1 Clock Output
Data Sheet
Prelimary
SSC Master Receive Input/
Slave Transmit Output
EXINT0_0 External Interrupt Input 0
T2EX1_1
Timer 21 External Trigger Input
RXD1_0
UART1 Receive Data Input
COUT62_1 Output of Capture/Compare
channel 2
10
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P1
I/O
Port 1
Port 1 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for the JTAG, CCU6, UART, Timer 0, Timer 1,
Timer 2, Timer 21, MCAN and SSC.
P1.0
26/34
PU
RXD_0
T2EX
RXDC0_0
UART Receive Data Input
Timer 2 External Trigger Input
MCAN Node 0 Receiver Input
P1.1
27/35
PU
EXINT3
T0_1
TDO_1
TXD_0
External Interrupt Input 3
Timer 0 Input
JTAG Serial Data Output
UART Transmit Data Output/
Clock Output
MCAN Node 0 Transmitter
Output
TXDC0_0
P1.2
28/36
PU
SCK_0
SSC Clock Input/Output
P1.3
29/37
PU
MTSR_0
SSC Master Transmit Output/
Slave Receive Input
MCAN Node 1 Transmitter
Output
TXDC1_3
P1.4
P1.5
30/38
31/39
Data Sheet
Prelimary
PU
PU
MRST_0
EXINT0_1
RXDC1_3
SSC Master Receive Input/
Slave Transmit Output
External Interrupt Input 6
MCAN Node 1 Receiver Input
CCPOS0_1
EXINT5
T1_1
EXF2_0
RXDO_0
CCU6 Hall Input 0
External Interrupt Input 5
Timer 1 Input
Timer 2 External Flag Output
UART Transmit Data Output
11
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P1.6
8/10
PU
CCPOS1_1 CCU6 Hall Input 1
T12HR_0
CCU6 Timer 12 Hardware Run
Input
EXINT6_0 External Interrupt Input 6
RXDC0_2
MCAN Node 0 Receiver Input
T21_1
Timer 21 Input
P1.7
9/11
PU
CCPOS2_1 CCU6 Hall Input 2
T13HR_0
CCU6 Timer 13 Hardware Run
Input
T2_1
Timer 2 Input
TXDC0_2
MCAN Node 0 Transmitter
Output
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
Data Sheet
Prelimary
12
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P2
I
Port 2
Port 2 is an 8-bit general purpose input-only
port. It can be used as alternate functions for
the digital inputs of the JTAG and CCU6. It is
also used as the analog inputs for the ADC.
P2.0
14/22
Hi-Z
CCPOS0_0 CCU6 Hall Input 0
EXINT1_0 External Interrupt Input 1
T12HR_2
CCU6 Timer 12 Hardware Run
Input
TCK_1
JTAG Clock Input
CC61_3
Input of Capture/Compare
channel 1
AN0
Analog Input 0
P2.1
15/23
Hi-Z
CCPOS1_0 CCU6 Hall Input 1
EXINT2_0 External Interrupt Input 2
T13HR_2
CCU6 Timer 13 Hardware Run
Input
TDI_1
JTAG Serial Data Input
CC62_3
Input of Capture/Compare
channel 2
AN1
Analog Input 1
P2.2
16/24
Hi-Z
CCPOS2_0 CCU6 Hall Input 2
CCU6 Trap Input
CTRAP_1
CC60_3
Input of Capture/Compare
channel 0
AN2
Analog Input 2
P2.3
19/27
Hi-Z
AN3
Analog Input 3
P2.4
20/28
Hi-Z
AN4
Analog Input 4
P2.5
21/29
Hi-Z
AN5
Analog Input 5
P2.6
22/30
Hi-Z
AN6
Analog Input 6
P2.7
25/33
Hi-Z
AN7
Analog Input 7
Data Sheet
Prelimary
13
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P3
I/O
Port 3
Port 3 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, UART1, Timer 21 and MCAN.
P3.0
35/43
Hi-Z
CCPOS1_2 CCU6 Hall Input 1
CC60_0
Input/Output of Capture/
Compare channel 0
RXDO1_1 UART1 Transmit Data Output
P3.1
36/44
Hi-Z
CCPOS0_2 CCU6 Hall Input 0
CC61_2
Input/Output of Capture/
Compare channel 1
COUT60_0 Output of Capture/Compare
channel 0
TXD1_1
UART1 Transmit Data Output/
Clock Output
P3.2
37/49
Hi-Z
CCPOS2_2
RXDC1_1
RXD1_1
CC61_0
P3.3
38/50
Hi-Z
COUT61_0 Output of Capture/Compare
channel 1
TXDC1_1
MCAN Node 1 Transmitter
Output
P3.4
39/51
Hi-Z
CC62_0
RXDC0_1
T2EX1_0
CCU6 Hall Input 2
MCAN Node 0 Receiver Input
UART1 Receive Data Input
Input/Output of Capture/
Compare channel 1
Input/Output of Capture/
Compare channel 2
MCAN Node 0 Receiver Input
Timer 21 External Trigger Input
P3.5
40/52
Hi-Z
COUT62_0 Output of Capture/Compare
channel 2
EXF21_0
Timer 21 External Flag Output
TXDC0_1
MCAN Node 0 Transmitter
Output
P3.6
33/41
PD
CTRAP_0
Data Sheet
Prelimary
14
CCU6 Trap Input
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P3.7
34/42
P4
Hi-Z
I/O
EXINT4
External Interrupt Input 4
COUT63_0 Output of Capture/Compare
channel 3
Port 4
Port 4 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for CCU6, Timer 0, Timer 1, Timer 21 and
MCAN.
P4.0
45/59
Hi-Z
RXDC0_3
CC60_1
P4.1
46/60
Hi-Z
TXDC0_3
P4.2
–/61
PU
EXINT6_1
T21_0
P4.3
32/40
Hi-Z
EXF21_1
Timer 21 External Flag Output
COUT63_2 Output of Capture/Compare
channel 3
P4.4
–/45
Hi-Z
CCPOS0_3 CCU6 Hall Input 0
T0_0
Timer 0 Input
CC61_4
Output of Capture/Compare
channel 1
P4.5
–/46
Hi-Z
CCPOS1_3 CCU6 Hall Input 1
T1_0
Timer 1 Input
COUT61_2 Output of Capture/Compare
channel 1
P4.6
–/47
Hi-Z
CCPOS2_3 CCU6 Hall Input 2
T2_0
Timer 2 Input
CC62_2
Output of Capture/Compare
channel 2
P4.7
–/48
Hi-Z
CCU6 Trap Input
CTRAP_3
COUT62_2 Output of Capture/Compare
channel 2
Data Sheet
Prelimary
MCAN Node 0 Receiver Input
Output of Capture/Compare
channel 0
MCAN Node 0 Transmitter
Output
COUT60_1 Output of Capture/Compare
channel 0
15
External Interrupt Input 6
Timer 21 Input
V0.1, 2006-02
XC886/888CLM
General Device Information
Table 3
Pin Definitions and Functions (cont’d)
Symbol Pin Number Type Reset Function
(TQFP-48/64)
State
P5
I/O
Port 5
Port 5 is an 8-bit bidirectional general purpose
I/O port. It can be used as alternate functions
for UART, UART1 and JTAG.
P5.0
–/8
PU
EXINT1_1
External Interrupt Input 1
P5.1
–/9
PU
EXINT2_1
External Interrupt Input 2
P5.2
–/12
PU
RXD_2
UART Receive Data Input
P5.3
–/13
PU
TXD_2
UART Transmit Data Output/
Clock Output
P5.4
–/14
PU
RXDO_2
UART Transmit Data Output
P5.5
–/15
PU
TDO_2
TXD1_2
JTAG Serial Data Output
UART1 Transmit Data Output/
Clock Output
P5.6
–/19
PU
TCK_2
RXDO1_2
JTAG Clock Input
UART1 Transmit Data Output
P5.7
–/20
PU
TDI_2
RXD1_2
JTAG Serial Data Input
UART1 Receive Data Input
VDDP
7, 17, 43/
7, 25, 55
–
I/O Port Supply (3.3 or 5.0 V)
VSSP
VDDC
VSSC
VAREF
VAGND
18, 42/26, 54
–
–
I/O Port Ground
6/6
–
–
Core Supply Monitor (2.5 V)
5/5
–
–
Core Supply Ground
24/32
–
–
ADC Reference Voltage
23/31
–
–
ADC Reference Ground
XTAL1
4/4
I
Hi-Z
External Oscillator Input
(backup for on-chip OSC, normally NC)
XTAL2
3/3
O
Hi-Z
External Oscillator Output
(backup for on-chip OSC, normally NC)
TMS
–
10/16
I
PD
Test Mode Select
RESET 41/53
I
PU
Reset Input
MBC
44/58
I
PU
Monitor & BootStrap Loader Control
NC
–/21, 59, 60
–
–
No Connection
Data Sheet
Prelimary
16
V0.1, 2006-02
XC886/888CLM
Functional Description
3
Functional Description
3.1
Processor Architecture
The XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU)
that is compatible with the standard 8051 processor. While the standard 8051 processor
is designed around a 12-clock machine cycle, the XC886/888 CPU uses a 2-clock
machine cycle. This allows fast access to ROM or RAM memories without wait state.
Access to the Flash memory, however, requires an additional wait state (one machine
cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte
instructions.
The XC886/888 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and SFRs.
Figure 6 shows the CPU functional blocks.
Data Sheet
Prelimary
17
V0.1, 2006-02
XC886/888CLM
Functional Description
Internal Data
Memory
Core SFRs
Register Interface
External Data
Memory
External SFRs
16-bit Registers &
Memory Interface
ALU
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
State Machine &
Power Saving
UART
Program Memory
fCCLK
Memory Wait
Reset
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
Figure 6
3.2
Interrupt
Controller
CPU Block Diagram
Memory Organization
The XC886/888 CPU operates in the following five address spaces:
• 12 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 1.5 Kbytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 24/32 Kbytes of Flash program memory (Flash devices); or
24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the
24-Kbyte Flash devices, the shaded banks are not available.
Data Sheet
Prelimary
18
V0.1, 2006-02
XC886/888CLM
Functional Description
FFFFH
FFFF H
F600H
F600H
1)
In 24-Kbyte Flash devices, the upper 2Kbyte of Banks 4 and 5 are not available.
XRAM
1.5 Kbytes
XRAM
1.5 Kbytes
F000H
F000H
Boot ROM
12 Kbytes
C000H
D-Flash Bank 1
4 Kbytes
B000H
D-Flash Bank 0
4 Kbytes
A000H
8000H
D-Flash Bank 0
4 Kbytes
7000H
D-Flash Bank 1
4 Kbytes
6000H
P-Flash Banks 4 and 5
2 x 4 Kbytes 1)
5000H
Indirect
Address
Direct
Address
Internal RAM
Special Function
Registers
FF H
4000H
P-Flash Banks 2 and 3
2 x 4 Kbytes
80H
2000H
7FH
P-Flash Banks 0 and 1
2 x 4 Kbytes
Internal RAM
0000H
Program Space
Figure 7
Data Sheet
Prelimary
0000H
00H
External Data Space
Internal Data Space
Memory Map of XC886/888 Flash Device
19
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.1
Memory Protection Strategy
The XC886/888 memory protection strategy includes:
• Read-out protection: The user is able to protect the contents in the Flash (for Flash
devices) and ROM (for ROM devices) memory from being read
• Flash program and erase protection (for Flash devices only)
Flash memory protection modes are available only for Flash devices:
• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 4.
Table 4
Flash Protection Modes
Mode
0
1
Activation
Program a valid password via BSL mode 6
Selection
MSB of password = 0
MSB of password = 1
P-Flash contents Read instructions in the
can be read by
P-Flash
Read instructions in the
P-Flash or D-Flash
P-Flash program Not possible
and erase
Not possible
D-Flash contents Read instructions in any program
can be read by
memory
Read instructions in the
P-Flash or D-Flash
D-Flash program Possible
Not possible
D-Flash erase
Not possible
Possible, on the condition that bit
DFLASHEN in register MISC_CON
is set to 1 prior to each erase
operation
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. A
password match triggers an automatic erase of the protected P-Flash and D-Flash
contents, including the programmed password. The Flash protection is then disabled
upon the next reset.
Although no protection scheme can be considered infallible, the XC886/888 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Data Sheet
Prelimary
20
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.2
Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.2.2.1
Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number
of addressable SFRs to 256. The extended address range is not directly controlled by
the CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 8.
SYSCON0
System Control Register 0
7
6
Reset Value: 00H
5
4
3
2
1
0
0
IMODE
0
RMAP
r
rw
r
rw
The functions of the shaded bits are not described here
Field
Bits
Type Description
RMAP
0
rw
Special Function Register Map Control
0
The access to the standard SFR area is
enabled.
1
The access to the mapped SFR area is
enabled.
0
[7:5],
[3:1]
r
Reserved
Returns 0 if read; should be written with 0.
Data Sheet
Prelimary
21
V0.1, 2006-02
XC886/888CLM
Functional Description
Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of
SYSCON0 should not be modified.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
Standard Area (RMAP = 0)
FFH
Module 1 SFRs
Module 2 SFRs
SYSCON0.RMAP
rw
…...
Module n SFRs
80H
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
FFH
Module (n+1) SFRs
Module (n+2) SFRs
…...
Module m SFRs
80H
Direct
Internal Data
Memory Address
Figure 8
Data Sheet
Prelimary
Address Extension by Mapping
22
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.2.2
Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC886/888 has a 256-SFR address range. However, this is
still less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 9.
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
SFR0
rw
SFR1
…...
SFRx
PAGE 1
SFR0
SFR Data
(to/from CPU)
SFR1
…...
SFRy
…...
PAGE q
SFR0
SFR1
…...
SFRz
Module
Figure 9
Data Sheet
Prelimary
Address Extension by Paging
23
V0.1, 2006-02
XC886/888CLM
Functional Description
In order to access a register located in a page different from the actual one, the current
page must be left. This is done by reprogramming the bit field PAGE in the page register.
Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and finally, the old page
setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and
restore action of the current page setting. By indicating which storage bit field should be
used in parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to
the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
PAGE
value update
from CPU
Figure 10
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC886/888 supports local address extension for:
•
•
•
•
Parallel Ports
Analog-to-Digital Converter (ADC)
Capture/Compare Unit 6 (CCU6)
System Control Registers
Data Sheet
Prelimary
24
V0.1, 2006-02
XC886/888CLM
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
00
01
10
11
Data Sheet
Prelimary
ST0 is selected.
ST1 is selected.
ST2 is selected.
ST3 is selected.
25
V0.1, 2006-02
XC886/888CLM
Functional Description
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
Data Sheet
Prelimary
26
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.3
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. Note that access is opened for
maximum 32 CCLKs if the “close access” password is not written. If “open access”
password is written again before the end of 32 CCLK cycles, there will be a recount of
32 CCLK cycles. The protected bits include the N- and K-Divider bits, NDIV and KDIV;
the Watchdog Timer enable bit, WDTEN; and the power-down and slow-down enable
bits, PD and SD.
PASSWD
Password Register
7
Reset Value: 07H
6
5
4
3
2
1
0
PASS
PROTECT
_S
MODE
wh
rh
rw
Field
Bits
Type Description
MODE
[1:0]
rw
Bit Protection Scheme Control bits
00
Scheme Disabled
11
Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000B; only then, will the
MODE[1:0] be registered.
PROTECT_S
2
rh
Bit Protection Signal Status bit
This bit shows the status of the protection.
0
Software is able to write to all protected bits.
1
Software is unable to write to any protected
bits.
PASS
[7:3]
wh
Password bits
The Bit Protection Scheme only recognizes three
patterns.
11000B Enables writing of the bit field MODE.
10011B Opens access to writing of all protected bits.
10101B Closes access to writing of all protected bits.
Data Sheet
Prelimary
27
V0.1, 2006-02
XC886/888CLM
Functional Description
3.2.4
XC886/888 Register Overview
The SFRs of the XC886/888 are organized into groups according to their functional units.
The contents (bits) of the SFRs are summarized in Table 5 to Table 18, with the
addresses of the bitaddressable SFRs appearing in bold typeface.
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 5
Addr
CPU Register Overview
Register Name
RMAP = 0 or 1
SP
81H
Stack Pointer Register
Bit
Reset: 07H
Bit Field
Type
82H
DPL
Reset: 00H
Data Pointer Register Low
Bit Field
Type
83H
DPH
Reset: 00H
Data Pointer Register High
Bit Field
Type
87H
PCON
Power Control Register
Reset: 00H
Bit Field
Type
88H
TCON
Timer Control Register
Reset: 00H
Bit Field
Type
89H
TMOD
Timer Mode Register
Reset: 00H
Bit Field
Type
8AH
TL0
Timer 0 Register Low
Reset: 00H
Bit Field
Type
8BH
TL1
Timer 1 Register Low
Reset: 00H
Bit Field
Type
8CH
TH0
Timer 0 Register High
Reset: 00H
Bit Field
Type
8DH
TH1
Timer 1 Register High
Reset: 00H
Bit Field
Type
98H
SCON
Reset: 00H
Serial Channel Control Register
Bit Field
Type
99H
SBUF
Reset: 00H
Serial Data Buffer Register
Bit Field
Type
A2H
EO
Reset: 00H
Extended Operation Register
Bit Field
A8H
IEN0
Reset: 00H
Interrupt Enable Register 0
B8H
IP
Reset: 00H
Interrupt Priority Register
B9H
IPH
Reset: 00H
Interrupt Priority Register High
D0H
PSW
Reset: 00H
Program Status Word Register
E0H
ACC
Accumulator Register
E8H
IEN1
Reset: 00H
Interrupt Enable Register 1
7
6
Reset: 00H
Bit Field
Type
Bit Field
Type
Bit Field
Type
Data Sheet
Prelimary
4
3
2
1
0
SP
rw
DPL7 DPL6
rw
rw
DPH7 DPH6
rw
rw
SMOD
rw
TF1
TR1
rwh
rw
GATE1
0
rw
r
SM0
rw
SM1
rw
0
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
5
r
EA
rw
0
r
DPL5 DPL4 DPL3 DPL2
rw
rw
rw
rw
DPH5 DPH4 DPH3 DPH2
rw
rw
rw
rw
0
GF1
GF0
r
rw
rw
TF0
TR0
IE1
IT1
rwh
rw
rwh
rw
T1M
GATE0
0
rw
rw
r
VAL
rwh
VAL
rwh
VAL
rwh
VAL
rwh
SM2
REN
TB8
RB8
rw
rw
rw
rwh
VAL
rwh
TRAP_
0
EN
rw
r
DPL1 DPL0
rw
rw
DPH1 DPH0
rw
rw
0
IDLE
r
rw
IE0
IT0
rwh
rw
T0M
rw
ET2
rw
PT2
rw
PT2H
rw
RI
rwh
DPSEL
0
rw
ET1
rw
PT1
rw
PT1H
rw
EX1
rw
PX1
rw
PX1H
rw
ET0
rw
PT0
rw
PT0H
rw
EX0
rw
PX0
rw
PX0H
rw
CY
AC
F0
RS1
RS0
rwh
rwh
rw
rw
rw
ACC7 ACC6 ACC5 ACC4 ACC3
rw
rw
rw
rw
rw
ECCIP ECCIP ECCIP ECCIP EXM
3
2
1
0
rw
rw
rw
rw
rw
OV
rwh
ACC2
rw
EX2
F1
rw
ACC1
rw
ESSC
P
rh
ACC0
rw
EADC
rw
rw
rw
0
r
0
r
28
ES
rw
PS
rw
PSH
rw
TI
rwh
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 5
CPU Register Overview (cont’d)
Addr
Register Name
F0H
B
B Register
Bit
F8H
IP1
Reset: 00H
Interrupt Priority Register 1
F9H
IPH1
Reset: 00H
Interrupt Priority Register 1 High
Reset: 00H
Bit Field
Type
Bit Field
Type
Bit Field
Type
7
6
5
4
3
B7
B6
B5
B4
B3
rw
rw
rw
rw
rw
PCCIP PCCIP PCCIP PCCIP PXM
3
2
1
0
rw
rw
rw
rw
rw
PCCIP PCCIP PCCIP PCCIP PXMH
3H
2H
1H
0H
rw
rw
rw
rw
rw
2
1
0
B2
rw
PX2
B1
rw
PSSC
B0
rw
PADC
rw
rw
rw
PX2H PSSCH PADC
H
rw
rw
rw
The MDU SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6
Addr
MDU Register Overview
Register Name
RMAP = 1
MDUSTAT
B0H
MDU Status Register
Bit
Reset: 00H
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
B1H
MDUCON
MDU Control Register
Reset: 00H
B2H
MD0
MDU Data Register 0
Reset: 00H
MR0
MDU Data Register 0
Reset: 00H
MD1
MDU Data Register 1
Reset: 00H
MR1
MDU Data Register 1
Reset: 00H
MD2
MDU Data Register 2
Reset: 00H
MR2
MDU Data Register 2
Reset: 00H
MD3
MDU Data Register 3
Reset: 00H
MR3
MDU Data Register 3
Reset: 00H
MD4
MDU Data Register 4
Multiplication/Division
Shift/Normalization
Reset: 00H
MR4
MDU Data Register 4
Multiplication/Division
Shift/Normalization
Reset: 00H
MD5
MDU Data Register 5
Reset: 00H
Bit Field
MR5
MDU Data Register 5
Reset: 00H
Type
Bit Field
B3H
B4H
B5H
B6H
B7H
Data Sheet
Prelimary
7
6
IE
rw
IR
rw
5
4
3
0
r
RSEL START
rw
rwh
DATA
rw
DATA
rh
DATA
rw
DATA
rh
DATA
rw
DATA
rh
DATA
rw
DATA
rh
DATA
Type
2
1
BSY
IERR
rh
rwh
OPCODE
rw
0
IRDY
rwh
rw
0
rw
SLR
rw
Bit Field
SCTR
rw
DATA
Type
rh
0
rh
SCTR
rh
DATA
rw
DATA
rh
Type
29
V0.1, 2006-02
XC886/888CLM
Functional Description
The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 7
Addr
CORDIC Register Overview
Register Name
Bit
RMAP = 1
CD_CORDXL
Reset: 00H
9AH
CORDIC X Data Low Byte
9BH
CD_CORDXH
Reset: 00H
CORDIC X Data High Byte
9CH
CD_CORDYL
Reset: 00H
CORDIC Y Data Low Byte
9DH
CD_CORDYH
Reset: 00H
CORDIC Y Data High Byte
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
9EH
CD_CORDZL
Reset: 00H
CORDIC Z Data Low Byte
Bit Field
Type
9FH
CD_CORDZH
Reset: 00H
CORDIC Z Data High Byte
A0H
CD_STATC
Reset: 00H
CORDIC Status and Data Control
Register
Bit Field
Type
Bit Field
A1H
CD_CON
Reset: 00H
CORDIC Control Register
Type
Bit Field
Type
7
6
5
4
3
2
1
0
DATAL
rw
DATAH
rw
DATAL
rw
DATAH
rw
DATAL
rw
DATAH
rw
KEEPZ KEEPY KEEPX DMAP INT_E EOC ERRO
N
R
rw
rw
rw
rw
rw
rwh
rh
MPS
X_USI ST_MO ROTVE
MODE
GN
DE
C
rw
w
rw
rw
rw
BSY
rh
ST
rwh
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8
Addr
System Control Register Overview
Register Name
Bit
RMAP = 0 or 1
SYSCON0
Reset: 00H
8FH
System Control Register 0
Bit Field
Type
RMAP = 0
SCU_PAGE
BFH
Page Register
Bit Field
Type
Reset: 00H
RMAP = 0, PAGE 0
MODPISEL
Reset: 00H
B3H
Peripheral Input Select Register
B4H
IRCON0
Reset: 00H
Interrupt Request Register 0
B5H
IRCON1
Reset: 00H
Interrupt Request Register 1
B6H
IRCON2
Reset: 00H
Interrupt Request Register 2
B7H
EXICON0
Reset: F0H
External Interrupt Control Register 0
BAH
EXICON1
Reset: 3FH
External Interrupt Control Register 1
Data Sheet
Prelimary
7
OP
w
0
Type
Bit Field
0
Type
Bit Field
r
0
Type
r
r
Bit Field
Type
Bit Field
Type
5
4
0
r
Bit Field
Type
Bit Field
6
IMODE
rw
STNR
w
2
1
0
r
0
r
0
RMAP
rw
PAGE
rw
URRIS JTAGT JTAGT EXINT EXINT EXINT URRIS
H
DIS
CKS
2IS
1IS
0IS
rw
rw
rw
rw
rw
rw
rw
EXINT EXINT EXINT EXINT EXINT EXINT EXINT
6
5
4
3
2
1
0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
CANS CANS ADCS ADCS
RIR
TIR
EIR
RC2
RC1
RC1
RC0
rwh
0
r
EXINT3
rw
0
r
30
3
rwh
rwh
CANS
RC3
rwh
EXINT2
rw
EXINT6
rw
rwh
rwh
0
r
EXINT1
rw
EXINT5
rw
rwh
rwh
CANS
RC0
rwh
EXINT0
rw
EXINT4
rw
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 8
System Control Register Overview (cont’d)
Addr
Register Name
BBH
NMICON
NMI Control Register
Reset: 00H
BCH
NMISR
NMI Status Register
Reset: 00H
BDH
BCON
Reset: 00H
Baud Rate Control Register
BEH
BG
Reset: 00H
Baud Rate Timer/Reload Register
E9H
FDCON
Reset: 00H
Fractional Divider Control Register
EAH
FDSTEP
Reset: 00H
Fractional Divider Reload Register
EBH
FDRES
Reset: 00H
Fractional Divider Result Register
Bit
7
Bit Field
0
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
RMAP = 0, PAGE 1
ID
B3H
Identity Register
Reset: 09H
Bit Field
Type
Bit Field
Type
r
r
0
Type
r
PMCON1
Reset: 00H
Power Mode Control Register 1
B6H
OSC_CON
OSC Control Register
Reset: 08H
Bit Field
B7H
PLL_CON
PLL Control Register
Reset: 90H
Bit Field
BAH
CMCON
Clock Control Register
Reset: 10H
Type
Bit Field
BBH
PASSWD
Password Register
Reset: 07H
Type
Bit Field
BCH
FEAL
Reset: 00H
Flash Error Address Register Low
BDH
FEAH
Reset: 00H
Flash Error Address Register High
BEH
COCON
Reset: 00H
Clock Output Control Register
E9H
MISC_CON
Reset: 00H
Miscellaneous Control Register
PRODID
r
WDT WKRS
RST
rwh
rwh
CDC_D CAN_D
IS
IS
rw
rw
0
Type
r
NDIV
rw
VCO
SEL
rw
Type
RMAP = 0, PAGE 3
XADDRH
Reset: F0H
B3H
On-chip XRAM Address Higher Order
Data Sheet
Prelimary
3
2
NMI
NMI
OCDS FLASH
1
0
NMI
PLL
NMI
WDT
rw
rw
rw
FNMI FNMI FNMI FNMI FNMI
VDDP VDD OCDS FLASH PLL
rwh
rwh
rwh
rwh
rwh
0
BRDIS
BRPRE
r
rw
rw
BR_VALUE
rwh
BGS SYNEN ERRSY EOFSY BRK NDOV FDM
N
N
rw
rw
rwh
rwh
rwh
rwh
rw
STEP
rw
RESULT
rh
Type
Bit Field
B5H
4
NMI
VDD
rw
rw
FNMI
WDT
rwh
R
rw
FNMI
ECC
r
rwh
BGSEL
rw
0
PMCON0
Reset: 00H
Power Mode Control Register 0
5
NMI
VDDP
rw
0
Bit Field
Type
Bit Field
B4H
6
NMI
ECC
rw
KDIV
0
rw
r
PASS
0
Type
r
WK
SD
PD
SEL
rw
rw
rwh
rw
MDU_ T2_DIS CCU
SSC
ADC
DIS
_DIS
_DIS
_DIS
rw
rw
rw
rw
rw
OSC
XPD
OSC ORDR OSCR
PD
SS
ES
rw
rw
rw
rwh
rh
VCOB OSC RESLD LOCK
YP
DISC
rw
rw
rwh
rh
FCCFG
CLKREL
rw
rw
PROTE
CT_S
rh
ECCERRADDR
rh
ECCERRADDR
rh
TLEN COUT
S
rw
rw
Bit Field
0
Type
r
Bit Field
Type
ADDRH
rw
31
rw
VERID
r
WS
wh
Bit Field
Type
Bit Field
Type
Bit Field
FDEN
MODE
rw
COREL
rw
DFLAS
HEN
rwh
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 8
System Control Register Overview (cont’d)
Addr
Register Name
Bit
B4H
IRCON3
Reset: 00H
Interrupt Request Register 3
Bit Field
B5H
IRCON4
Reset: 00H
Interrupt Request Register 4
B7H
MODPISEL1
Reset: 00H
Peripheral Input Select Register 1
BAH
MODPISEL2
Reset: 00H
Peripheral Input Select Register 2
BBH
PMCON2
Reset: 00H
Power Mode Control Register 2
BDH
MODSUSP
Reset: 00H
Module Suspend Control Register
7
6
0
Type
r
Bit Field
0
Type
Bit Field
Type
Bit Field
Type
5
4
3
CANS CCU6S
RC5
R1
rwh
rwh
CANS CCU6S
RC7
R3
rwh
rwh
0
UR1RIS
r
EXINT
6IS
rw
0
Type
r
Bit Field
0
Type
r
1
0
CANS CCU6S
RC4
R0
rwh
rwh
CANS CCU6S
RC6
R2
r
rwh
rwh
T21EXI JTAGT JTAGT
S
DIS1 CKS1
rw
rw
rw
rw
T21IS T2IS
T1IS
T0IS
rw
rw
rw
rw
UART1 T21
_DIS
_DIS
r
0
r
Bit Field
2
0
r
0
rw
rw
T21SU T2SUS T13SU T12SU WDTS
SP
P
SP
SP
USP
rw
rw
rw
rw
rw
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 9
Addr
WDT Register Overview
Register Name
Bit
RMAP = 1
WDTCON
Reset: 00H
BBH
Watchdog Timer Control Register
BCH
WDTREL
Reset: 00H
Watchdog Timer Reload Register
BDH
WDTWINB
Reset: 00H
Watchdog Window-Boundary Count
Register
BEH
WDTL
Reset: 00H
Watchdog Timer Register Low
BFH
WDTH
Reset: 00H
Watchdog Timer Register High
7
6
Bit Field
0
Type
r
5
4
3
2
1
0
WINB
EN
rw
WDT
PR
rh
0
WDT
EN
WDT
RS
WDT
IN
rw
rwh
rw
1
0
Bit Field
Type
Bit Field
r
WDTREL
rw
WDTWINB
Type
Bit Field
rw
WDT[7:0]
rh
WDT[15:8]
rh
Type
Bit Field
Type
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10
Addr
Port Register Overview
Register Name
Bit
RMAP = 0
PORT_PAGE
Reset: 00H
B2H
Page Register for PORT
Bit Field
Type
RMAP = 0, Page 0
P0_DATA
80H
P0 Data Register
Reset: 00H
Bit Field
Type
7
OP
w
86H
P0_DIR
P0 Direction Register
Reset: 00H
Bit Field
Type
P7
rw
P7
rw
90H
P1_DATA
P1 Data Register
Reset: 00H
Bit Field
Type
P7
rw
Data Sheet
Prelimary
6
32
5
4
STNR
w
P6
rw
P6
rw
P5
rw
P5
rw
P4
rw
P4
rw
P6
rw
P5
rw
P4
rw
3
2
0
r
PAGE
rw
P3
rw
P3
P2
rw
P2
P1
rw
P1
P0
rw
P0
rw
P3
rw
rw
P2
rw
rw
P1
rw
rw
P0
rw
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr
Register Name
Bit
7
6
5
4
3
2
1
0
91H
P1_DIR
P1 Direction Register
Reset: 00H
Bit Field
92H
P5_DATA
P5 Data Register
Reset: 00H
Type
Bit Field
93H
P5_DIR
P5 Direction Register
Reset: 00H
Type
Bit Field
A0H
P2_DATA
P2 Data Register
Reset: 00H
Type
Bit Field
Type
Bit Field
P0
rw
P0
rw
P0
rw
P0
rw
B0H
P3_DATA
P3 Data Register
Reset: 00H
Type
Bit Field
B1H
P3_DIR
P3 Direction Register
Reset: 00H
Bit Field
Type
C8H
P4_DATA
P4 Data Register
Reset: 00H
Bit Field
Type
C9H
P4_DIR
P4 Direction Register
Reset: 00H
Bit Field
Type
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P1
rw
P1
rw
P1
rw
P1
rw
Reset: 00H
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2_DIR
P2 Direction Register
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P3
rw
P3
rw
P3
rw
P3
rw
A1H
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0_PUDEN
Reset: C4H Bit Field
P0 Pull-Up/Pull-Down Enable Register Type
P1_PUDSEL
Reset: FFH Bit Field
P1 Pull-Up/Pull-Down Select Register Type
P1_PUDEN
Reset: FFH Bit Field
P1 Pull-Up/Pull-Down Enable Register Type
P5_PUDSEL
Reset: FFH Bit Field
P5 Pull-Up/Pull-Down Select Register Type
P5_PUDEN
Reset: FFH Bit Field
P5 Pull-Up/Pull-Down Enable Register Type
P2_PUDSEL
Reset: FFH Bit Field
P2 Pull-Up/Pull-Down Select Register Type
P2_PUDEN
Reset: 00H Bit Field
P2 Pull-Up/Pull-Down Enable Register Type
P3_PUDSEL
Reset: BFH Bit Field
P3 Pull-Up/Pull-Down Select Register Type
P3_PUDEN
Reset: 40H Bit Field
P3 Pull-Up/Pull-Down Enable Register Type
P4_PUDSEL
Reset: FFH Bit Field
P4 Pull-Up/Pull-Down Select Register Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
P4_PUDEN
Reset: 04H Bit Field
P4 Pull-Up/Pull-Down Enable Register Type
P7
rw
P6
rw
P5
rw
P4
rw
rw
P3
rw
rw
P2
rw
rw
P1
rw
rw
P0
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
Type
RMAP = 0, Page 1
P0_PUDSEL
Reset: FFH
80H
P0 Pull-Up/Pull-Down Select Register
86H
90H
91H
92H
93H
A0H
A1H
B0H
B1H
C8H
C9H
RMAP = 0, Page 2
P0_ALTSEL0
Reset: 00H
80H
P0 Alternate Select 0 Register
86H
P0_ALTSEL1
Reset: 00H
P0 Alternate Select 1 Register
90H
P1_ALTSEL0
Reset: 00H
P1 Alternate Select 0 Register
Data Sheet
Prelimary
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
33
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 10
Port Register Overview (cont’d)
Addr
Register Name
Bit
7
6
5
4
3
2
1
0
91H
P1_ALTSEL1
Reset: 00H
P1 Alternate Select 1 Register
Bit Field
92H
P5_ALTSEL0
Reset: 00H
P5 Alternate Select 0 Register
93H
P5_ALTSEL1
Reset: 00H
P5 Alternate Select 1 Register
B0H
P3_ALTSEL0
Reset: 00H
P3 Alternate Select 0 Register
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P3_ALTSEL1
Reset: 00H
P3 Alternate Select 1 Register
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P3
rw
P3
rw
P3
rw
P3
rw
B1H
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
1
0
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
C8H
P4_ALTSEL0
Reset: 00H
P4 Alternate Select 0 Register
C9H
P4_ALTSEL1
Reset: 00H
P4 Alternate Select 1 Register
Bit Field
Type
RMAP = 0, Page 3
P0_OD
Reset: 00H
80H
P0 Open Drain Control Register
Bit Field
Type
90H
P1_OD
Reset: 00H
P1 Open Drain Control Register
Bit Field
Type
92H
P5_OD
Reset: 00H
P5 Open Drain Control Register
Bit Field
Type
B0H
P3_OD
Reset: 00H
P3 Open Drain Control Register
Bit Field
Type
C8H
P4_OD
Reset: 00H
P4 Open Drain Control Register
Bit Field
Type
Type
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11
Addr
ADC Register Overview
Register Name
Bit
RMAP = 0
ADC_PAGE
D1H
Page Register for ADC
Reset: 00H
RMAP = 0, Page 0
CAH
ADC_GLOBCTR
Global Control Register
Reset: 30H
Bit Field
CBH
ADC_GLOBSTR
Global Status Register
Reset: 00H
Type
Bit Field
CCH
ADC_PRAR
Reset: 00H
Priority and Arbitration Register
Type
Bit Field
Type
CDH
ADC_LCBR
Reset: B7H
Limit Check Boundary Register
Bit Field
Type
CEH
ADC_INPCR0
Input Class Register 0
Reset: 00H
Bit Field
Type
CFH
ADC_ETRCR
Reset: 00H
External Trigger Control Register
Bit Field
7
Bit Field
Type
Type
6
5
OP
w
ANON
rw
4
STNR
w
DW
rw
0
r
ASEN1 ASEN0
0
rw
rw
r
BOUND1
rw
SYNEN SYNEN
1
0
rw
rw
CTC
rw
CHNR
3
2
0
r
PAGE
rw
0
r
SAM BUSY
PLE
r
rh
rh
rh
ARBM CSM1 PRIO1 CSM0 PRIO0
rw
rw
rw
rw
rw
BOUND0
rw
STC
rw
ETRSEL1
ETRSEL0
rw
0
rw
RMAP = 0, Page 1
Data Sheet
Prelimary
34
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr
Register Name
Bit
7
CAH
ADC_CHCTR0
Reset: 00H
Channel Control Register 0
Bit Field
CBH
ADC_CHCTR1
Reset: 00H
Channel Control Register 1
CCH
ADC_CHCTR2
Reset: 00H
Channel Control Register 2
CDH
ADC_CHCTR3
Reset: 00H
Channel Control Register 3
CEH
ADC_CHCTR4
Reset: 00H
Channel Control Register 4
0
r
0
r
0
r
0
r
0
r
0
r
0
r
0
r
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
CFH
ADC_CHCTR5
Reset: 00H
Channel Control Register 5
D2H
ADC_CHCTR6
Reset: 00H
Channel Control Register 6
Bit Field
Type
D3H
ADC_CHCTR7
Reset: 00H
Channel Control Register 7
Bit Field
Type
Type
RMAP = 0, Page 2
ADC_RESR0L
CAH
Result Register 0 Low
Reset: 00H
Bit Field
Type
CBH
ADC_RESR0H
Result Register 0 High
Reset: 00H
Bit Field
Type
CCH
ADC_RESR1L
Result Register 1 Low
Reset: 00H
Bit Field
Type
CDH
ADC_RESR1H
Result Register 1 High
Reset: 00H
Bit Field
Type
CEH
ADC_RESR2L
Result Register 2 Low
Reset: 00H
Bit Field
Type
CFH
ADC_RESR2H
Result Register 2 High
Reset: 00H
Bit Field
Type
D2H
ADC_RESR3L
Result Register 3 Low
Reset: 00H
Bit Field
Type
D3H
ADC_RESR3H
Result Register 3 High
Reset: 00H
Bit Field
Type
RMAP = 0, Page 3
ADC_RESRA0L
Reset: 00H
CAH
Result Register 0, View A Low
Bit Field
Type
CBH
ADC_RESRA0H
Reset: 00H
Result Register 0, View A High
Bit Field
Type
CCH
ADC_RESRA1L
Reset: 00H
Result Register 1, View A Low
Bit Field
Type
CDH
ADC_RESRA1H
Reset: 00H
Result Register 1, View A High
CEH
ADC_RESRA2L
Reset: 00H
Result Register 2, View A Low
CFH
ADC_RESRA2H
Reset: 00H
Result Register 2, View A High
D2H
ADC_RESRA3L
Reset: 00H
Result Register 3, View A Low
D3H
ADC_RESRA3H
Reset: 00H
Result Register 3, View A High
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Data Sheet
Prelimary
6
5
RESULT[1:0]
rh
0
r
RESULT[1:0]
rh
0
r
RESULT[1:0]
rh
0
r
RESULT[1:0]
rh
0
r
RESULT[2:0]
rh
RESULT[2:0]
rh
RESULT[2:0]
rh
RESULT[2:0]
rh
35
4
3
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
LCC
rw
2
1
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
0
r
0
r
0
r
0
r
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
RESRSEL
rw
VF
DRC
rh
rh
RESULT[9:2]
rh
VF
DRC
rh
rh
RESULT[9:2]
rh
VF
DRC
rh
rh
RESULT[9:2]
rh
VF
DRC
rh
rh
RESULT[9:2]
rh
CHNR
rh
VF
DRC
rh
rh
RESULT[10:3]
rh
VF
DRC
rh
rh
CHNR
rh
RESULT[10:3]
rh
VF
DRC
rh
rh
RESULT[10:3]
rh
VF
DRC
rh
rh
RESULT[10:3]
rh
0
0
r
0
r
0
r
0
r
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
CHNR
rh
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 11
Addr
ADC Register Overview (cont’d)
Register Name
RMAP = 0, Page 4
ADC_RCR0
Reset: 00H
CAH
Result Control Register 0
Bit
Type
Bit Field
rw
rw
VFCTR WFR
rw
FEN
rw
IEN
r
0
Type
Bit Field
rw
rw
VFCTR WFR
rw
FEN
rw
IEN
r
0
Type
Bit Field
rw
rw
VFCTR WFR
rw
FEN
rw
IEN
r
0
rw
rw
ADC_RCR3
Reset: 00H
Result Control Register 3
CEH
ADC_VFCR
Reset: 00H
Valid Flag Clear Register
Bit Field
Type
RMAP = 0, Page 5
ADC_CHINFR
Reset: 00H
CAH
Channel Interrupt Flag Register
Bit Field
Type
Type
ADC_CHINPR
Reset: 00H
Channel Interrupt Node Pointer
Register
CEH
ADC_EVINFR
Reset: 00H
Event Interrupt Flag Register
CFH
ADC_EVINCR
Reset: 00H
Event Interrupt Clear Flag Register
D2H
ADC_EVINSR
Reset: 00H
Event Interrupt Set Flag Register
D3H
ADC_EVINPR
Reset: 00H
Event Interrupt Node Pointer Register
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
RMAP = 0, Page 6
ADC_CRCR1
Reset: 00H Bit Field
CAH
Conversion Request Control Register 1
Type
CBH
ADC_CRPR1
Reset: 00H Bit Field
Conversion Request Pending
Register 1
Type
CCH
ADC_CRMR1
Reset: 00H
Conversion Request Mode Register 1
CDH
ADC_QMR0
Reset: 00H
Queue Mode Register 0
Bit Field
Type
Data Sheet
Prelimary
2
0
CDH
CDH
3
IEN
ADC_RCR2
Reset: 00H
Result Control Register 2
ADC_CHINSR
Reset: 00H
Channel Interrupt Set Register
4
FEN
CCH
CCH
5
VFCTR WFR
ADC_RCR1
Reset: 00H
Result Control Register 1
ADC_CHINCR
Reset: 00H
Channel Interrupt Clear Register
6
Bit Field
CBH
CBH
7
Bit Field
Type
rw
rw
0
r
CHINF CHINF CHINF CHINF CHINF
7
6
5
4
3
rh
rh
rh
rh
rh
CHINC CHINC CHINC CHINC CHINC
7
6
5
4
3
w
w
w
w
w
CHINS CHINS CHINS CHINS CHINS
7
6
5
4
3
w
w
w
w
w
CHINP CHINP CHINP CHINP CHINP
7
6
5
4
3
rw
rw
rw
rw
rw
CH7
CH6
CH5
rwh
rwh
CHP5
CHP4
rwh
Rsv
rwh
LDEV
rwh
CLR
PND
w
rwh
SCAN
36
w
rw
rw
rw
EVINF EVINF
1
0
rh
rh
EVINC EVINC
1
0
r
0
r
0
w
w
EVINS EVINS
1
0
w
w
EVINP EVINP
1
0
rw
rw
r
0
r
r
0
rwh
CHP6
r
rh
rh
rh
CHINC CHINC CHINC
2
1
0
w
w
w
CHINS CHINS CHINS
2
1
0
w
w
w
CHINP CHINP CHINP
2
1
0
0
rwh
rw
TREV FLUSH CLRV
w
w
w
rw
VFC0
w
CHINF CHINF CHINF
2
1
0
CH4
CHP7
CEV
w
VFC1
w
0
EVINS EVINS EVINS EVINS
7
6
5
4
w
w
w
w
EVINP EVINP EVINP EVINP
7
6
5
4
rw
rw
rw
rw
0
DRCT
R
rw
DRCT
R
rw
DRCT
R
rw
DRCT
R
r
VFC2
w
VFC3
w
EVINF EVINF EVINF EVINF
7
6
5
4
rh
rh
rh
rh
EVINC EVINC EVINC EVINC
7
6
5
4
w
w
w
w
1
r
ENSI
ENTR
ENGT
rw
0
r
rw
ENTR
rw
rw
ENGT
rw
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 11
ADC Register Overview (cont’d)
Addr
Register Name
Bit
CEH
ADC_QSR0
Reset: 20H
Queue Status Register 0
Bit Field
CFH
ADC_Q0R0
Queue 0 Register 0
Reset: 00H
D2H
ADC_QBUR0
Reset: 00H
Queue Backup Register 0
D2H
ADC_QINR0
Queue Input Register 0
Reset: 00H
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
7
Rsv
r
EXTR
rh
EXTR
rh
EXTR
w
6
5
4
0
EMPTY
r
rh
ENSI
RF
rh
rh
ENSI
RF
rh
rh
ENSI
RF
w
w
3
EV
rh
V
rh
V
rh
2
0
r
1
0
FILL
rh
REQCHNR
rh
REQCHNR
rh
REQCHNR
w
0
r
0
r
0
r
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 12
Timer 2 Register Overview
Addr
Register Name
Bit
C0H
T2_T2CON
Reset: 00H
Timer 2 Control Register
Bit Field
C1H
T2_T2MOD
Timer 2 Mode Register
C2H
T2_RC2L
Reset: 00H
Timer 2 Reload/Capture Register Low
C3H
T2_RC2H
Reset: 00H Bit Field
Timer 2 Reload/Capture Register High Type
T2_T2L
Reset: 00H Bit Field
Timer 2 Register Low
Type
T2_T2H
Reset: 00H Bit Field
Timer 2 Register High
Type
Reset: 00H
Type
Bit Field
Type
C4H
C5H
Bit Field
Type
7
6
TF2
EXF2
5
4
0
3
2
1
0
EXEN2
TR2
0
rwh
T2PRE
r
CP/
RL2
rw
DCEN
rwh
rwh
r
rw
T2
T2
EDGE PREN
REGS RHEN SEL
rw
rw
rw
rw
RC2
rwh
RC2
rwh
THL2
rwh
THL2
rwh
rw
rw
The Timer 21 SFRs can be accessed in the standard memory area (RMAP = 1).
Table 13
Addr
T21 Register Overview
Register Name
Bit
RMAP = 1
T2CON
Reset: 00H
C0H
Timer 2 Control Register
Bit Field
C1H
T2MOD
Timer 2 Mode Register
Reset: 00H
Type
Bit Field
C2H
RC2L
Reset: 00H
Timer 2 Reload/Capture Register Low
Type
Bit Field
Type
C3H
RC2H
Reset: 00H Bit Field
Timer 2 Reload/Capture Register High Type
T2L
Reset: 00H Bit Field
Timer 2 Register Low
Type
C4H
C5H
T2H
Timer 2 Register High
Data Sheet
Prelimary
Reset: 00H
7
TF2
6
5
4
3
2
1
0
EXF2
0
0
EXEN2
TR2
C/T2
rwh
T2PRE
rw
CP/
RL2
rw
DCEN
rwh
rwh
r
r
rw
T2
T2
EDGE PREN
REGS RHEN SEL
rw
rw
rw
rw
RC2
rwh
rw
rw
RC2
rwh
THL2
rwh
THL2
rwh
Bit Field
Type
37
V0.1, 2006-02
XC886/888CLM
Functional Description
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 14
Addr
CCU6 Register Overview
Register Name
RMAP = 0
CCU6_PAGE
Reset: 00H
A3H
Page Register for CCU6
Bit
7
6
OP
w
Bit Field
Type
5
4
3
STNR
w
2
1
0
r
0
PAGE
rw
RMAP = 0, Page 0
9AH
9BH
CCU6_CC63SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC63 Low
Type
CCU6_CC63SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC63 High
Type
9CH
CCU6_TCTR4L
Reset: 00H
Timer Control Register 4 Low
Bit Field
9DH
CCU6_TCTR4H
Reset: 00H
Timer Control Register 4 High
9EH
CCU6_MCMOUTSL
Reset: 00H
Multi-Channel Mode Output Shadow
Register Low
9FH
CCU6_MCMOUTSH
Reset: 00H
Multi-Channel Mode Output Shadow
Register High
CCU6_ISRL
Reset: 00H
Capture/Compare Interrupt Status
Reset Register Low
A5H
CCU6_ISRH
Reset: 00H
Capture/Compare Interrupt Status
Reset Register High
Bit Field
A6H
CCU6_CMPMODIFL
Reset: 00H
Compare State Modification Register
Low
A7H
CCU6_CMPMODIFH
Reset: 00H
Compare State Modification Register
High
FAH
FBH
FCH
FDH
FEH
FFH
rw
CC63SH
T12
STR
w
T13
STR
w
0
Type
Bit Field
Type
STRHP
w
0
r
Bit Field
RT12P RT12O RCC62 RCC62 RCC61 RCC61 RCC60
M
M
F
R
F
R
F
w
w
w
w
w
w
w
RSTR RIDLE RWHE RCHE
0
RTRPF RT13
PM
w
w
w
w
r
w
w
0
MCC63
0
MCC62 MCC61
S
S
S
r
w
r
w
w
0
MCC63
0
MCC62 MCC61
R
R
R
r
w
r
w
w
CC60SL
Type
Bit Field
Bit Field
Type
Type
Bit Field
Type
Bit Field
Type
CCU6_CC60SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC60 Low
Type
CCU6_CC60SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC60 High
Type
0
T12
RES
w
w
T13
RES
w
MCMPS
r
0
r
r
T12RS T12RR
w
w
T13RS T13RR
w
w
rw
CURHS
rw
EXPHS
rw
RCC60
R
w
RT13
CM
w
MCC60
S
w
MCC60
R
w
rwh
CC60SH
rwh
CCU6_CC61SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC61 Low
Type
CCU6_CC61SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC61 High
Type
CCU6_CC62SRL
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC62 Low
Type
CCU6_CC62SRH
Reset: 00H Bit Field
Capture/Compare Shadow Register for
Channel CC62 High
Type
Data Sheet
Prelimary
rw
DTRES
T12
STD
w
T13
STD
w
STRM
CM
w
Type
A4H
CC63SL
CC61SL
rwh
CC61SH
rwh
CC62SL
rwh
CC62SH
rwh
38
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 14
Addr
CCU6 Register Overview (cont’d)
Register Name
Bit
7
6
5
RMAP = 0, Page 1
CCU6_CC63RL
Reset: 00H Bit Field
9AH
Capture/Compare Register for Channel
CC63 Low
Type
CCU6_CC63RH
Reset: 00H Bit Field
9BH
Capture/Compare Register for Channel
CC63 High
Type
CCU6_T12PRL
Reset: 00H Bit Field
9CH
Timer T12 Period Register Low
Type
9DH
CCU6_T12PRH
Reset: 00H
Timer T12 Period Register High
9EH
CCU6_T13PRL
Reset: 00H
Timer T13 Period Register Low
9FH
CCU6_T13PRH
Reset: 00H
Timer T13 Period Register High
A4H
CCU6_T12DTCL
Reset: 00H
Dead-Time Control Register for Timer
T12 Low
Bit Field
Type
Bit Field
T13PVH
rwh
DTM
Type
CCU6_TCTR0L
Reset: 00H
Timer Control Register 0 Low
A7H
CCU6_TCTR0H
Reset: 00H
Timer Control Register 0 High
FAH
CCU6_CC60RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC60 Low
Type
CCU6_CC60RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC60 High
Type
0
rw
Bit Field
0
DTR2
DTR1
DTR0
0
DTE2
DTE1
DTE0
Type
Bit Field
r
CTM
rh
CDIR
rh
STE12
rh
T12R
rw
rw
T12CLK
rw
rh
r
T12
PRE
rw
T13
PRE
Type
Bit Field
0
rh
STE13
rh
T13R
Type
r
rh
rh
FCH
CCU6_CC61RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC61 Low
Type
FDH
CCU6_CC61RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC61 High
Type
CCU6_CC62RL
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC62 Low
Type
FFH
1
rh
CC63VH
Type
Bit Field
Type
A6H
2
CC63VL
Bit Field
CCU6_T12DTCH
Reset: 00H
Dead-Time Control Register for Timer
T12 High
FEH
3
rh
T12PVL
rwh
T12PVH
rwh
T13PVL
rwh
A5H
FBH
4
rw
rw
T13CLK
rw
CC60VL
rw
rh
CC60VH
rh
CC61VL
rh
CC61VH
rh
CC62VL
rh
CC62VH
CCU6_CC62RH
Reset: 00H Bit Field
Capture/Compare Register for Channel
CC62 High
Type
rh
RMAP = 0, Page 2
9AH
CCU6_T12MSELL
Reset: 00H
T12 Capture/Compare Mode Select
Register Low
9BH
CCU6_T12MSELH
Reset: 00H
T12 Capture/Compare Mode Select
Register High
Data Sheet
Prelimary
Bit Field
Type
Bit Field
Type
MSEL61
DBYP
rw
39
rw
HSYNC
rw
MSEL60
rw
MSEL62
rw
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr
Register Name
Bit
9CH
CCU6_IENL
Reset: 00H
Capture/Compare Interrupt Enable
Register Low
Bit Field
9DH
CCU6_IENH
Reset: 00H
Capture/Compare Interrupt Enable
Register High
9EH
CCU6_INPL
Reset: 40H
Capture/Compare Interrupt Node
Pointer Register Low
9FH
CCU6_INPH
Reset: 39H
Capture/Compare Interrupt Node
Pointer Register High
A4H
CCU6_ISSL
Reset: 00H Bit Field
Capture/Compare Interrupt Status Set
Register Low
Type
CCU6_ISSH
Reset: 00H Bit Field
Capture/Compare Interrupt Status Set
Register High
Type
CCU6_PSLR
Reset: 00H Bit Field
Passive State Level Register
Type
CCU6_MCMCTR
Reset: 00H Bit Field
Multi-Channel Mode Control Register Type
CCU6_TCTR2L
Reset: 00H Bit Field
Timer Control Register 2 Low
Type
A5H
A6H
A7H
FAH
Type
Bit Field
Type
Bit Field
7
Type
Bit Field
Type
FBH
CCU6_TCTR2H
Reset: 00H
Timer Control Register 2 High
Bit Field
Type
Bit Field
FCH
CCU6_MODCTRL
Reset: 00H
Modulation Control Register Low
FDH
CCU6_MODCTRH
Reset: 00H
Modulation Control Register High
FEH
CCU6_TRPCTRL
Reset: 00H
Trap Control Register Low
Bit Field
Type
FFH
CCU6_TRPCTRH
Reset: 00H
Trap Control Register High
Bit Field
Type
Bit Field
Type
Type
6
5
4
3
2
1
0
ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC
PM
OM
62F
62R
61F
61R
60F
60R
rw
rw
rw
rw
rw
rw
rw
rw
ENSTR EN
EN
EN
0
EN
ENT13 ENT13
IDLE
WHE
CHE
TRPF
PM
CM
rw
rw
rw
rw
r
rw
rw
rw
INPCHE
INPCC62
INPCC61
INPCC60
rw
0
rw
INPT13
rw
INPT12
rw
INPERR
r
rw
rw
rw
ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60
M
M
F
R
F
R
F
R
w
w
w
w
w
w
w
w
SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13
PM
CM
w
w
w
w
w
w
w
w
PSL63
0
PSL
rwh
r
rwh
0
SWSYN
0
SWSEL
r
rw
r
rw
0
T13TED
T13TEC
T13
T12
SSC
SSC
r
rw
rw
rw
rw
0
T13RSEL
T12RSEL
r
rw
rw
MC
0
T12MODEN
MEN
rw
r
rw
ECT13
0
T13MODEN
O
rw
r
rw
0
TRPM2 TRPM1 TRPM0
r
rw
rw
rw
TRPPE TRPEN
TRPEN
N
13
rw
rw
rw
RMAP = 0, Page 3
9AH
CCU6_MCMOUTL
Reset: 00H
Multi-Channel Mode Output Register
Low
9BH
CCU6_MCMOUTH
Reset: 00H
Multi-Channel Mode Output Register
High
9CH
CCU6_ISL
Reset: 00H
Capture/Compare Interrupt Status
Register Low
9DH
CCU6_ISH
Reset: 00H
Capture/Compare Interrupt Status
Register High
9EH
CCU6_PISEL0L
Reset: 00H
Port Input Select Register 0 Low
Data Sheet
Prelimary
Bit Field
0
Type
Bit Field
r
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
R
MCMP
rh
0
rh
CURH
EXPH
r
rh
rh
T12PM T12OM ICC62F ICC62 ICC61F ICC61 ICC60F ICC60
R
R
R
rh
rh
rh
rh
rh
rh
rh
rh
STR
IDLE
WHE
CHE TRPS TRPF T13PM T13CM
rh
rh
ISTRP
rw
40
rh
rh
ISCC62
rw
rh
rh
ISCC61
rw
rh
rh
ISCC60
rw
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 14
CCU6 Register Overview (cont’d)
Addr
Register Name
Bit
7
9FH
CCU6_PISEL0H
Reset: 00H
Port Input Select Register 0 High
Bit Field
IST12HR
ISPOS2
ISPOS1
ISPOS0
rw
0
r
rw
CCU6_PISEL2
Reset: 00H
Port Input Select Register 2
Type
Bit Field
Type
rw
A4H
rw
IST13HR
rw
FAH
CCU6_T12L
Reset: 00H
Timer T12 Counter Register Low
Bit Field
Type
FBH
CCU6_T12H
Reset: 00H
Timer T12 Counter Register High
Bit Field
Type
FCH
CCU6_T13L
Reset: 00H
Timer T13 Counter Register Low
Bit Field
Type
FDH
CCU6_T13H
Reset: 00H
Timer T13 Counter Register High
Bit Field
Type
FEH
CCU6_CMPSTATL
Reset: 00H
Compare State Register Low
Bit Field
FFH
CCU6_CMPSTATH
Reset: 00H
Compare State Register High
Type
Bit Field
Type
6
5
4
3
2
1
0
T12CVL
rwh
T12CVH
rwh
T13CVL
rwh
T13CVH
rwh
0
CC63 CCPO CCPO CCPO
ST
S2
S1
S0
r
rh
rh
rh
rh
T13IM COUT COUT CC62 COUT
63PS 62PS
PS
61PS
rwh
rwh
rwh
rwh
rwh
CC62
ST
rh
CC61
PS
rwh
CC61
ST
rh
COUT
60PS
rwh
CC60
ST
rh
CC60
PS
rwh
The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 15
Addr
UART1 Register Overview
Register Name
RMAP = 1
C8H
SCON
Reset: 00H
Serial Channel Control Register
C9H
SBUF
Reset: 00H
Serial Data Buffer Register
CAH
BCON
Reset: 00H
Baud Rate Control Register
CBH
CCH
CDH
CEH
BG
Reset: 00H
Baud Rate Timer/Reload Register
FDCON
Reset: 00H
Fractional Divider Control Register
FDSTEP
Reset: 00H
Fractional Divider Reload Register
FDRES
Reset: 00H
Fractional Divider Result Register
Bit
Bit Field
Type
Bit Field
Type
Bit Field
7
SM0
rw
6
5
SM1
rw
SM2
rw
4
3
REN
TB8
rw
rw
VAL
rwh
0
r
Type
Bit Field
2
1
0
RB8
rwh
TI
rwh
RI
rwh
BRPRE
rw
R
rw
BR_VALUE
rwh
Type
Bit Field
0
r
Type
Bit Field
NDOV
rwh
FDM
rw
FDEN
rw
2
1
0
CIS
rw
SIS
rw
MIS
rw
STEP
rw
RESULT
rh
Type
Bit Field
Type
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 16
Addr
SSC Register Overview
Register Name
RMAP = 0
SSC_PISEL
Reset: 00H
A9H
Port Input Select Register
Data Sheet
Prelimary
Bit
7
Bit Field
Type
6
5
0
r
41
4
3
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 16
AAH
SSC Register Overview
SSC_CONL
Control Register Low
Programming Mode
Operating Mode
Reset: 00H
Bit Field
Type
LB
rw
PO
rw
Bit Field
PH
rw
BC
rh
EN
MS
0
Operating Mode
Type
Bit Field
Type
rw
EN
rw
rw
MS
rw
r
0
r
ACH
SSC_TBL
Reset: 00H
Transmitter Buffer Register Low
Bit Field
Type
ADH
SSC_RBL
Reset: 00H
Receiver Buffer Register Low
AEH
SSC_BRL
Reset: 00H
Baudrate Timer Reload Register Low
AFH
SSC_BRH
Reset: 00H
Baudrate Timer Reload Register High
SSC_CONH
Control Register High
Programming Mode
Reset: 00H
BM
rw
0
r
Type
Bit Field
ABH
HB
rw
AREN
BEN
PEN
REN
TEN
rw
PE
rwh
rw
RE
rwh
rw
TE
rwh
Bit Field
Type
rw
rw
BSY
BE
rh
rwh
TB_VALUE
rw
RB_VALUE
rh
Bit Field
Type
Bit Field
Type
BR_VALUE
rw
BR_VALUE
rw
The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0).
Table 17
Addr
MultiCAN Register Overview
Register Name
Bit
RMAP = 0
ADCON
Reset: 00H
D8H
CAN Address/Data Control Register
Bit Field
Type
D9H
ADL
Reset: 00H
CAN Address Low Register
Bit Field
Type
DAH
ADH
Reset: 00H
CAN Address High Register
Bit Field
Type
DBH
DATA0
CAN Data Register 0
Reset: 00H
Bit Field
Type
DCH
DATA1
CAN Data Register 1
Reset: 00H
Bit Field
Type
DDH
DATA2
CAN Data Register 2
Reset: 00H
Bit Field
Type
DEH
DATA3
CAN Data Register 3
Reset: 00H
Bit Field
Type
7
V3
rw
CA9
rwh
6
5
4
V2
rw
CA8
rwh
V1
rw
CA7
rwh
V0
rw
CA6
rwh
0
r
3
2
AUAD
rw
CA5
CA4
rwh
rwh
CA13 CA12
rwh
rwh
CD
rwh
CD
rwh
CD
rwh
CD
rwh
1
0
BSY
rh
CA3
rwh
CA11
rwh
RWEN
rw
CA2
rwh
CA10
rwh
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 18
Addr
OCDS Register Overview
Register Name
RMAP = 1
MMCR2
Reset: 1UH
E9H
Monitor Mode Control 2 Register
F1H
MMCR
Reset: 00H
Monitor Mode Control Register
Bit
Bit Field
Type
Bit Field
Type
Data Sheet
Prelimary
7
6
5
4
3
2
1
0
STMO EXBC DSUSP MBCO ALTDI MMEP MMOD JENA
DE
N
E
rw
rw
rw
rwh
rw
rwh
rh
rh
MEXIT MEXIT
0
MSTEP MRAM MRAM TRF
RRF
_P
S_P
S
w
hw
r
rw
w
rwh
rh
rh
42
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 18
OCDS Register Overview (cont’d)
Addr
Register Name
Bit
F2H
MMSR
Reset: 00H
Monitor Mode Status Register
Bit Field
Type
MBCA MBCIN EXBF
M
rw
rwh
rwh
F3H
MMBPCR
Reset: 00H
BreakPoints Control Register
Bit Field
SWBC
F4H
Type
MMICR
Reset: 00H Bit Field
Monitor Mode Interrupt Control Register
F5H
MMDR
Reset: 00H
Monitor Mode Data Transfer Register
Receive
Transmit
Type
Bit Field
7
Type
HWBPSR
Reset: 00H Bit Field
Hardware Breakpoints Select Register
Type
F7H
HWBPDR
Reset: 00H
Hardware Breakpoints Data Register
EBH
MMWR1
Reset: 00H
Monitor Work Register 1
ECH
MMWR2
Reset: 00H
Monitor Work Register 2
5
HWB3C
rw
rw
DVECT DRETR COM
RST
rwh
rwh
rwh
Type
Bit Field
F6H
4
3
2
1
0
SWBF HWB3 HWB2 HWB1 HWB0
F
F
F
F
rwh
rwh
rwh
rwh
rwh
HWB2C
HWB1
HWB0C
C
rw
rw
rw
MST MMUIE MMUIE RRIE_ RRIE
SEL
_P
P
w
rw
w
rw
rh
MMRR
rh
MMTR
0
r
w
BPSEL
_P
w
Bit Field
HWBPxx
Type
Bit Field
rw
MMWR1
Type
rw
MMWR2
Bit Field
Type
Data Sheet
Prelimary
6
BPSEL
rw
rw
43
V0.1, 2006-02
XC886/888CLM
Functional Description
3.3
Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features:
•
•
•
•
•
•
•
•
•
•
•
•
In-System Programming (ISP) via UART
In-Application Programming (IAP)
Error Correction Code (ECC) for dynamic correction of single-bit errors
Background program and erase operations for CPU load minimization
Support for aborting erase operation
Minimum program width1) of 32-byte for D-Flash and 64-byte for P-Flash
1-sector minimum erase width
1-byte read access
135.1 ns minimum read access time (3 × tCCLK @ fCCLK = 24 MHz ± 7.5 %2))
Operating supply voltage: 2.5 V ± 7.5 %
Program time: 2.3 ms3)
Erase time: 120 ms3)
Table 19 shows the Flash data retention and endurance targets4).
Table 19
Flash Data Retention and Endurance Targets
Retention up to
Endurance up to
Programming
Temperature
Size
20 years
1,000 cycles
0 – 100°C
15 Kbytes
5 years
10,000 cycles
-40 – 125°C
896 bytes
2 years
70,000 cycles
-40 – 125°C
512 bytes
2 years
100,000 cycles
-40 – 125°C
128 bytes
1)
P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed.
D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
fsys = 96 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the maximum frequency range for Flash read access.
fsys = 96 MHz ± 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for
obtaining the worst case timing.
4)
Specification according to operating temperature profile with 0.2ppm error rate.
2)
3)
Data Sheet
Prelimary
44
V0.1, 2006-02
XC886/888CLM
Functional Description
3.3.1
Flash Bank Sectorization
The XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes
of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash)
bank(s) and a single Data Flash (D-Flash) bank with different sectorization shown in
Figure 11. Both types can be used for code and data storage. The label “Data” neither
implies that the D-Flash is mapped to the data memory region, nor that it can only be
used for data storage. It is used to distinguish the different Flash bank sectorizations.
The XC886/888 ROM devices offer a single 4-Kbyte D-Flash bank.
Sector 2: 128-byte
Sector 1: 128-byte
Sector 9:
Sector 8:
Sector 7:
Sector 6:
128-byte
128-byte
128-byte
128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 3: 512-byte
Sector 0: 3.75-Kbyte
Sector 2: 512-byte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
P-Flash
Figure 11
D-Flash
Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
Data Sheet
Prelimary
45
V0.1, 2006-02
XC886/888CLM
Functional Description
3.3.2
Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be
reprogrammed as the Flash cells can only withstand one gate disturb. This means that
the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to
program the same WL, for example, with 16 bytes of data in two times (see Figure 12).
16 bytes
16 bytes
0000 ….. 0000 H
32 bytes (1 WL)
0000 ….. 0000 H
Program 1
0000 ….. 0000 H
1111 ….. 1111 H
0000 ….. 0000 H
1111 ….. 1111 H
Program 2
1111 ….. 0000 H
0000 ….. 0000 H
1111 ….. 0000 H
1111 ….. 1111 H
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
Flash memory cells
Figure 12
32-byte write buffers
D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain
its original contents and to prevent “over-programming”.
Data Sheet
Prelimary
46
V0.1, 2006-02
XC886/888CLM
Functional Description
3.4
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC886/888 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1
Interrupt Source
Figure 13 to Figure 17 give a general overview of the interrupt sources and illustrates
the request and control flags.
WDT Overflow
FNMIWDT
NMIISR.0
NMIWDT
NMICON.0
PLL Loss of Lock
FNMIPLL
NMIISR.1
NMIPLL
NMICON.1
Flash Operation
Complete
FNMIFLASH
NMIISR.2
NMIFLASH
>=1
VDD Pre-Warning
0073
FNMIVDD
NMIISR.4
H
Non
Maskable
Interrupt
NMIVDD
NMICON.4
VDDP Pre-Warning
FNMIVDDP
NMIISR.5
NMIVDDP
NMICON.5
Flash ECC Error
FNMIECC
NMIISR.6
NMIECC
NMICON.6
Figure 13
Data Sheet
Prelimary
Non-Maskable Interrupt Request Sources
47
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Timer 0
Overflow
TF0
TCON.5
ET0
000B
Lowest
Priority Level
H
IEN0.1
Timer 1
Overflow
IP.1/
IPH.1
TF1
TCON.7
ET1
001B
H
IEN0.3
IP.3/
IPH.3
RI
SCON.0
UART
EINT0
>=1
TI
ES
SCON.1
IEN0.4
EXINT0
IE0
IRCON0.0
TCON.1
EX0
IT0
0023
0003
H
H
IEN0.0
EXINT0
P
o
l
l
i
n
g
TCON.0
IP.4/
IPH.4
S
e
q
u
e
n
c
e
IP.0/
IPH.0
EXICON0.0/1
EINT1
EXINT1
IE1
IRCON0.1
TCON.3
EX1
IT1
0013
H
IEN0.2
EXINT1
TCON.2
IP.2/
IPH.2
EXICON0.2/3
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 14
Data Sheet
Prelimary
Interrupt Request Sources (Part 1)
48
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Timer 2
Overflow
TF2
Lowest
Priority Level
T2_T2CON.7
>=1
T2EX
EXF2
T2_T2CON.6
EXEN2
EDGES
EL
T2_T2MOD.5
T2_T2CON.3
Normal Divider
Overflow
NDOV
>=1
FDCON.2
End of
Syn Byte
ET2
EOFSYN
Syn Byte Error
ERRSYN
002B
H
IEN0.5
SYNEN
FDCON.6
FDCON.4
IP.5/
IPH.5
FDCON.5
MCAN_0
CANSRC0
IRCON2.0
ADC_0
ADCSRC0
IRCON1.3
ADC_1
ADCSRC1
MCAN_1
CANSRC1
IRCON1.4
>=1
EADC
IRCON1.5
MCAN_2
0033
H
IEN1.0
IP1.0/
IPH1.0
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
CANSRC2
EA
IEN0.7
IRCON1.6
Bit-addressable
Request flag is cleared by hardware
Figure 15
Data Sheet
Prelimary
Interrupt Request Sources (Part 2)
49
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
SSC_EIR
EIR
IRCON1.0
SSC_TIR
TIR
>=1
IRCON1.1
SSC_RIR
ESSC
003B
H
IEN1.1
RIR
IP1.1/
IPH1.1
IRCON1.2
P
o
l
l
i
n
g
EXINT2
EINT2
IRCON0.2
EXINT2
EXICON0.4/5
RI
UART1_SCON.0
UART1
>=1
TI
UART1_SCON.1
Timer 21
Overflow
TF2
>=1
EX2
T21_T2CON.7
T21EX
0043
H
IEN1.2
EXF2
EXEN2
EDGES
EL
T21_T2MOD.5
>=1
IP1.2/
IPH1.2
S
e
q
u
e
n
c
e
T21_T2CON.6
T21_T2CON.3
Normal Divider
Overflow
NDOV
UART1_FDCON.2
Cordic
EOC
CDSTATC.2
MDU_0
IRDY
MDUSTAT.0
MDU_1
EA
IERR
MDUSTAT.1
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 16
Data Sheet
Prelimary
Interrupt Request Sources (Part 3)
50
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Lowest
Priority Level
EXINT3
EINT3
IRCON0.3
EXINT3
EXICON0.6/7
EXINT4
EINT4
P
o
l
l
i
n
g
IRCON0.4
EXINT3
EXICON1.0/1
>=1
EXINT5
EINT5
IRCON0.5
EXM
004B
H
IEN1.3
EXINT5
EXICON1.2/3
EXINT6
EINT6
IP1.3/
IPH1.3
S
e
q
u
e
n
c
e
IRCON0.6
EXINT6
EXICON1.4/5
MCAN_3
CANSRC3
EA
IEN0.7
IRCON2.4
Bit-addressable
Request flag is cleared by hardware
Figure 17
Data Sheet
Prelimary
Interrupt Request Sources (Part 4)
51
V0.1, 2006-02
XC886/888CLM
Functional Description
Highest
Lowest
CCU6 interrupt node 0
CCU6SR0
IRCON3.0
MCAN_4
Priority Level
>=1
MCANSRC4
ECCIP0
IRCON3.1
0053
H
IEN1.4
CCU6 interrupt node 1
CCU6SR1
IRCON3.4
MCAN_5
>=1
MCANSRC5
ECCIP1
IRCON3.5
CCU6 interrupt node 2
>=1
ECCIP2
MCANSRC6
IP1.5/
IPH1.5
0063
H
IP1.6/
IPH1.6
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
CCU6SRC3
IRCON4.4
MCAN_7
H
IEN1.6
IRCON4.1
CCU6 interrupt node 3
005B
IEN1.5
CCU6SR2
IRCON4.0
MCAN_6
IP1.4/
IPH1.4
>=1
MCANSRC7
ECCIP3
IRCON4.5
IEN1.7
006B
H
IP1.7/
IPH1.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 18
Data Sheet
Prelimary
Interrupt Request Sources (Part 5)
52
V0.1, 2006-02
XC886/888CLM
Functional Description
ICC60R
CC60
ISL.0
ENCC60R
IENL.0
>=1
ICC60F
ISL.1
ENCC60F
IENL.1
INPL.1
INPL.0
INPL.3
INPL.2
INPL.5
INPL.4
INPH.3
INPH.2
INPH.5
INPH.4
INPH.1
INPH.0
INPL.7
INPL.6
ICC61R
CC61
ISL.2
ENCC61R
IENL.2
>=1
ICC61F
ISL.3
ENCC61F
IENL.3
ICC62R
CC62
ISL.4
ENCC62R
IENL.4
>=1
ICC62F
ISL.5
T12
One match
T12OM
T12
Period match
T12PM
T13
Compare match
T13CM
T13
Period match
T13PM
ISL.6
ISL.7
ISH.0
ISH.1
CTRAP
Correct Hall
Event
>=1
ENT12PM
IENL.7
ENT13CM
IENH.0
>=1
ENT13PM
IENH.1
ENTRPF
IENH.2
>=1
WHE
ISH.5
ENWHE
IENH.5
CHE
ISH.4
Multi-Channel
Shadow
Transfer
ENT12OM
IENL.6
TRPF
ISH.2
Wrong Hall
Event
ENCC62F
IENL.5
ENCHE
IENH.4
>=1
STR
ISH.7
ENSTR
IENH.7
CCU6 Interrupt node 0
CCU6 Interrupt node 1
.
CCU6 Interrupt node 2
CCU6 Interrupt node 3
Figure 19
Data Sheet
Prelimary
Interrupt Request Sources (Part 6)
53
V0.1, 2006-02
XC886/888CLM
Functional Description
3.4.2
Interrupt Source and Vector
Each interrupt source has an associated interrupt vector address. This vector is
accessed to service the corresponding interrupt source request. The interrupt service of
each interrupt source can be individually enabled or disabled via an enable bit. The
assignment of the XC886/888 interrupt sources to the interrupt vector addresses and the
corresponding interrupt source enable bits are summarized in Table 20.
Table 20
Interrupt
Source
NMI
Interrupt Vector Addresses
Vector
Address
Assignment for XC886/
888
Enable Bit
SFR
0073H
Watchdog Timer NMI
NMIWDT
NMICON
PLL NMI
NMIPLL
Flash NMI
NMIFLASH
VDDC Prewarning NMI
NMIVDD
VDDP Prewarning NMI
NMIVDDP
Flash ECC NMI
NMIECC
XINTR0
0003H
External Interrupt 0
EX0
XINTR1
000BH
Timer 0
ET0
XINTR2
0013H
External Interrupt 1
EX1
XINTR3
001BH
Timer 1
ET1
XINTR4
0023H
UART
ES
XINTR5
002BH
T2
ET2
IEN0
UART Fractional Divider
(Normal Divider Overflow)
MultiCAN Node 0
LIN
Data Sheet
Prelimary
54
V0.1, 2006-02
XC886/888CLM
Functional Description
Table 20
XINTR6
Interrupt Vector Addresses (cont’d)
0033H
MultiCAN Nodes 1 and 2
EADC
IEN1
ADC[1:0]
XINTR7
003BH
SSC
ESSC
XINTR8
0043H
External Interrupt 2
EX2
T21
CORDIC
UART1
UART1 Fractional Divider
(Normal Divider Overflow)
MDU[1:0]
XINTR9
004BH
External Interrupt 3
EXM
External Interrupt 4
External Interrupt 5
External Interrupt 6
MultiCAN Node 3
XINTR10
0053H
XINTR11
005BH
XINTR12
0063H
CCU6 INP0
ECCIP0
MultiCAN Node 4
CCU6 INP1
ECCIP1
MultiCAN Node 5
CCU6 INP2
ECCIP2
MultiCAN Node 6
XINTR13
006BH
CCU6 INP3
ECCIP3
MultiCAN Node 7
Data Sheet
Prelimary
55
V0.1, 2006-02
XC886/888CLM
Functional Description
3.4.3
Interrupt Priority
Each interrupt source, except for NMI, can be individually programmed to one of the four
possible priority levels. The NMI has the highest priority and supersedes all other
interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are
available to program the priority level of each non-NMI interrupt vector.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot
be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 21.
Table 21
Priority Structure within Interrupt Level
Source
Level
Non-Maskable Interrupt (NMI)
(highest)
External Interrupt 0
1
Timer 0 Interrupt
2
External Interrupt 1
3
Timer 1 Interrupt
4
UART Interrupt
5
Timer 2,UART Fractional Divider, MCAN, LIN
Interrupt
6
ADC, MCAN Interrupt
7
SSC Interrupt
8
External Interrupt 2, Timer 21, UART1, UART1 9
Fractional Divider, MDU, CORDIC Interrupt
External Interrupt [6:3], MCAN Interrupt
10
CCU6 Interrupt Node Pointer 0, MCAN interrupt 11
CCU6 Interrupt Node Pointer 1, MCAN Interrupt 12
CCU6 Interrupt Node Pointer 2, MCAN Interrupt 13
CCU6 Interrupt Node Pointer 3, MCAN Interrupt 14
Data Sheet
Prelimary
56
V0.1, 2006-02
XC886/888CLM
Functional Description
3.5
Parallel Ports
The XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4),
while the XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 6
(P6). Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as
general purpose input/output (GPIO) or to perform alternate input/output functions for the
on-chip peripherals. When configured as an output, the open drain mode can be
selected. Port P2 is an input-only port, providing general purpose input functions,
alternate input functions for the on-chip peripherals, and also analog inputs for the
Analog-to-Digital Converter (ADC).
Bidirectional Port Features:
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Transfer of data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Input Port Features:
•
•
•
•
•
Configurable input driver
Configurable pull-up/pull-down devices
Receive of data through digital input (general purpose input)
Alternate input for on-chip peripherals
Analog input for ADC module
Data Sheet
Prelimary
57
V0.1, 2006-02
XC886/888CLM
Functional Description
Internal Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_ALTSEL0
Alternate Select
Register 0
VDDP
Px_ALTSEL1
Alternate Select
Register 1
enable
AltDataOut 3
AltDataOut 2
AltDataOut1
enable
11
10
Pull
Up
Device
Output
Driver
Pin
01
00
Px_Data
Data Register
enable
Out
In
Input
Driver
Schmitt Trigger
AltDataIn
enable
Pull
Down
Device
Pad
Figure 20
Data Sheet
Prelimary
General Structure of Bidirectional Port
58
V0.1, 2006-02
XC886/888CLM
Functional Description
Internal Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_DIR
Direction Register
VDDP
enable
enable
Px_DATA
Data Register
In
Input
Driver
Pull
Up
Device
Pin
Schmitt Trigger
AltDataIn
AnalogIn
enable
Pull
Down
Device
Pad
Figure 21
Data Sheet
Prelimary
General Structure of Input Port
59
V0.1, 2006-02
XC886/888CLM
Functional Description
3.6
Power Supply System with Embedded Voltage Regulator
The XC886/888 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 22 shows the XC886/888 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
Memory
On-chip
OSC
Peripheral
logic
ADC
V DDC (2.5V)
FLASH
PLL
GPIO Ports
(P0-P5)
XTAL1&
XTAL2
EVR
VDDP (3.3V/5.0V)
VSSP
Figure 22
XC886/888 Power Supply System
EVR Features:
•
•
•
•
•
Input voltage (VDDP): 3.3 V/5.0 V
Output voltage (VDDC): 2.5 V ± 7.5%
Low power voltage regulator provided in power-down mode
VDDC and VDDP prewarning detection
VDDC brownout detection
Data Sheet
Prelimary
60
V0.1, 2006-02
XC886/888CLM
Functional Description
3.7
Reset Control
The XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC886/888 is first powered up, the status of certain pins (see Table 23) must
be defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external
capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches
0.4 V, but not before VDDC reaches 0.9* VDDC.
A typical application example is shown in Figure 23. For a voltage regulator with IDDmax
= 100 mA, the VDDP capacitor value is 10 µF. VDDC capacitor value is 220 nF. The
capacitor connected to RESET pin is 100 nF.
Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 µs once VDDP
reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less
than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 24.
Vin
VR
3 - 5V /
e.g. 100mA
e.g. 10uF
VSSP
typ.
100nF
VDDP
220nF
VDDC
VSSC
RESET
EVR
30k
XC886/888
Figure 23
Data Sheet
Prelimary
Reset Circuitry
61
V0.1, 2006-02
XC886/888CLM
Functional Description
Voltage
5V
VDDP
2.5V
2.3V
0.9*VDDC
VDDC
Time
Voltage
RESET with
capacitor
5V
< 0.4V
0V
Time
typ. < 50 us
Figure 24
VDDP, VDDC and VRESET during Power-on Reset
The second type of reset in XC886/888 is the hardware reset. This reset function can be
used during normal operation or when the chip is in power-down mode. A reset input pin
RESET is provided for the hardware reset.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
Data Sheet
Prelimary
62
V0.1, 2006-02
XC886/888CLM
Functional Description
3.7.1
Module Reset Behavior
Table 22 shows how the functions of the XC886/888 are affected by the various reset
types. A “ ” means that this function is reset to its default state.
Table 22
Effect of Reset on Device Functions
Module/
Function
Wake-Up
Reset
Watchdog
Reset
Hardware
Reset
Power-On
Reset
Brownout
Reset
CPU Core
Peripherals
On-Chip
Static RAM
Not affected, Not affected, Not affected, Affected, un- Affected, unreliable
reliable
reliable
reliable
reliable
Oscillator,
PLL
Not affected
Port Pins
EVR
The voltage Not affected
regulator is
switched on
FLASH
NMI
Disabled
3.7.2
Disabled
Booting Scheme
When the XC886/888 is reset, it must identify the type of configuration with which to start
the different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 23
shows the available boot options in the XC886/888.
Table 23
MBC
XC886/888 Boot Selection
TMS
P0.0
Type of Mode
PC Start Value
1
0
x
User Mode; on-chip OSC/PLL non-bypassed
0000H
0
0
x
BSL Mode; on-chip OSC/PLL non-bypassed
0000H
0
1
0
OCDS Mode; on-chip OSC/PLL nonbypassed
0000H
1
1
0
User (JTAG) Mode1); on-chip OSC/PLL nonbypassed (normal)
0000H
1)
Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Data Sheet
Prelimary
63
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XC886/888CLM
Functional Description
3.8
Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC886/888. The power consumption is indirectly proportional to the frequency, whereas
the performance of the microcontroller is directly proportional to the frequency. During
user program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features:
•
•
•
•
•
Phase-Locked Loop (PLL) for multiplying clock source by different factors
PLL Base Mode
Prescaler Mode
PLL Mode
Power-down mode support
The CGU consists of an oscillator circuit and a PLL. In the XC886/888, the oscillator can
be from either of these two sources: the on-chip oscillator (9.6 MHz) or the external
oscillator (3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip
oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip
oscillator will be used by default.The external oscillator can be selected via software. In
addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock
detection. This allows emergency routines to be executed for system recovery or to
perform system shut down.
Data Sheet
Prelimary
64
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XC886/888CLM
Functional Description
OSC
fosc
osc fail
detect
OSCR
lock
detect
LOCK
P:1
PLL
core
fp
fn
N:1
OSCDISC
Figure 25
fsys
K:1
fvco
PLLBYP
VCOBYP
NDIV
CGU Block Diagram
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source. For the XC886/888, the PLL bypass cannot be set active. Hence, the direct
drive mode is not available for use.
f SYS = f OSC
PLL Base Mode
The system clock is derived from the VCO base frequency clock divided by the K factor.
Both VCO bypass and PLL bypass must be inactive for this PLL mode.
1
f SYS = f VCObase × ---K
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
1
f SYS = f OSC × ------------P×K
Data Sheet
Prelimary
65
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XC886/888CLM
Functional Description
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and
divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for
this PLL mode. The PLL mode is used during normal system operation. .
N
f SYS = f OSC × ------------P×K
System Frequency Selection
For the XC886/888, the value of P is fixed to 1. In order to obtain the required fsys, the
value of N and K can be selected by bits NDIV and KDIV respectively for different
oscillator inputs. The output frequency must always be configured for 96 MHz. Table 24
provides examples on how fsys = 96 MHz can be obtained for the different oscillator
sources.
Table 24
System frequency (fsys = 96 MHz)
Oscillator
fosc
N
P
K
fsys
On-chip
9.6 MHz
20
1
2
96 MHz
External
8 MHz
24
1
2
96 MHz
6 MHz
32
1
2
96 MHz
4 MHz
48
1
2
96 MHz
Table 25 shows the VCO range for the XC886/888.
Table 25
VCO Range
fVCOmin
fVCOmax
fVCOFREEmin
fVCOFREEmax
Unit
150
200
20
80
MHz
100
150
10
80
MHz
3.8.1
Resonator Circuitry
Figure 26 shows the recommended ceramic resonator circuitry. When using an external
resonator, its frequency can be within the range of 3 MHz to 12 MHz. A resonator load
circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists
of two load capacitances C1 and C2, and in some cases, a feedback (Rf) and/or damp
(Rd) resistor might be necessary.
Data Sheet
Prelimary
66
V0.1, 2006-02
XC886/888CLM
Functional Description
C1
XTAL1
Ceramic
Resonator
C2
Rf
XC886/888
Rd
XTAL2
Figure 26
External Ceramic Resonator Circuitry
Note: The manufacturer of the ceramic resonator should check the resonator circuitry
and make recommendations for the C1, C2, Rf and Rd values to be used for stable
start-up behavior.
Data Sheet
Prelimary
67
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XC886/888CLM
Functional Description
3.8.2
Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, fsys. During normal system operation, the typical frequencies of the different
modules are as follow:
•
•
•
•
CPU clock: CCLK, SCLK = 24 MHz
Fast clock (used by MCAN): FCLK = 24 or 48 MHz
Peripheral clock: PCLK = 24 MHz
Flash Interface clock: CCLK2 = 96 MHz and CCLK = 24 MHz
In addition, different clock frequency can output to pin CLKOUT(P0.0 or P0.7). The clock
output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the
resulting output frequency has 50% duty cycle. Figure 27 shows the clock distribution of
the XC886/888.
FCCFG
FCLK
MCAN
CLKREL
PCLK
Peripherals
SCLK
OSC
fosc
PLL
N,P,K
fsys=
96MHz
/2
CCLK
CCLK2
COREL
CORE
FLASH
Interface
TLEN
Toggle
Latch
CLKOUT
COUTS
Figure 27
Data Sheet
Prelimary
Clock Generation from fsys
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XC886/888CLM
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 26.
Table 26
System frequency (fsys = 96 MHz)
Power Saving Mode
Action
Idle
Clock to the CPU is disabled.
Slow-down
Clocks to the CPU and all the peripherals are divided by a
common programmable factor defined by bit field
CMCON.CLKREL.
Power-down
Oscillator and PLL are switched off.
Data Sheet
Prelimary
69
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XC886/888CLM
Functional Description
3.9
Power Saving Modes
The power saving modes of the XC886/888 provide flexible power consumption through
a combination of techniques, including:
•
•
•
•
Stopping the CPU clock
Stopping the clocks of individual system components
Reducing clock speed of some peripheral components
Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 28) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
ACTIVE
any interrupt
& SD=0
set PD
bit
set IDLE
bit
set SD
bit
IDLE
clear SD
bit
set IDLE
bit
any interrupt
& SD=1
Figure 28
Data Sheet
Prelimary
EXINT0/RXD pin
& SD=0
POWER-DOWN
set PD
bit
SLOW-DOWN
EXINT0/RXD pin
& SD=1
Transition between Power Saving Modes
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Functional Description
3.10
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC886/888 system reset. Hence, routine service of the WDT
confirms that the system is functioning properly. This ensures that an accidental
malfunction of the XC886/888 will be aborted in a user-specified time period. In debug
mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh
the WDT during debugging.
Features:
•
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Selectable input frequency of fPCLK/2 or fPCLK/128
Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This
16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT
can be preset to a user-programmable value via a watchdog service access in order to
modify the watchdog expire time period. The lower 8 bits are reset on each service
access. Figure 29 shows the block diagram of the WDT unit.
WDT
Control
Clear
1:2
MUX
f PCLK
WDTREL
WDT Low Byte
WDT High Byte
1:128
Overflow/Time-out Control &
Window-boundary control
WDTTO
WDTRST
WDTIN
ENWDT
Logic
ENWDT_P
Figure 29
Data Sheet
Prelimary
WDTWINB
WDT Block Diagram
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Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is
entered. The prewarning period lasts for 30H count, after which the system is reset
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000H to the value obtained from the concatenation of WDTWINB and
00H.
After being serviced, the WDT continues counting up from the value (<WDTREL> * 28).
The time period for an overflow of the WDT is programmable in two ways:
• the input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
The period, PWDT, between servicing the WDT and the next overflow can be determined
by the following formula:
( 1 + WDTIN × 6 ) × ( 2 16 – WDTREL × 2 8 )
P WDT = 2----------------------------------------------------------------------------------------------------f PCLK
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 30. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not
be smaller than WDTREL.
Count
FFFF H
WDTWINB
WDTREL
time
No refresh
allowed
Figure 30
Data Sheet
Prelimary
Refresh allowed
WDT Timing Diagram
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Functional Description
Table 27 lists the possible watchdog time range that can be achieved for different
module clock frequencies . Some numbers are rounded to 3 significant digits.
Table 27
Reload value
in WDTREL
Watchdog Time Ranges
Prescaler for fPCLK
2 (WDTIN = 0)
128 (WDTIN = 1)
24 MHz
24 MHz
FFH
21.3 µs
1.37 ms
7FH
2.75 ms
176 ms
00H
5.46 ms
350 ms
Data Sheet
Prelimary
73
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XC886/888CLM
Functional Description
3.11
UART and UART1
The XC886/888 provides two Universal Asynchronous Receiver/Transmitter (UART and
UART1) modules for full-duplex asynchronous reception/transmission. Both are also
receive-buffered, i.e., they can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features:
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
The UART modules can operate in four asynchronous modes as shown in Table 28.
Data is transmitted on TXD and received on RXD.
Table 28
UART Modes
Operating Mode
Baud Rate
Mode 0: 8-bit shift register
fPCLK/2
Mode 1: 8-bit shift UART
Variable
Mode 2: 9-bit shift UART
fPCLK/32 or fPCLK/641)
Mode 3: 9-bit shift UART
Variable
1)
For UART1 module, the baud rate is fixed at fPCLK/64.
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock
and can be configured to either fPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64
is available. The variable baud rate is set by the underflow rate on the dedicated baudrate generator. For UART module, the variable baud rate alternatively can be set by the
overflow rate on Timer 1.
Data Sheet
Prelimary
74
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XC886/888CLM
Functional Description
3.11.1
Baud-Rate Generator
Both UART modules have their own dedicated baud-rate generator, which is based on
a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and
fractional divider) for generating a wide range of baud rates based on its input clock
fPCLK, see Figure 31.
Fractional Divider
8-Bit Reload Value
FDSTEP
1
FDM
1
FDEN&FDM
0
Adder
fDIV
00
01
FDRES
FDEN
0
1
0
11
fMOD (overflow)
10
8-Bit Baud Rate Timer
fBR
R
fPCLK
Prescaler
fDIV
clk
11
10
NDOV
01
‘0’
Figure 31
00
Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the
output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (fBR) value is dependent on the following parameters:
• Input clock fPCLK
• Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON
Data Sheet
Prelimary
75
V0.1, 2006-02
XC886/888CLM
Functional Description
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
f PCLK
BRPRE
- where 2
baud rate = ---------------------------------------------------------------------------------× ( BR_VALUE + 1 ) > 1
BRPRE
16 × 2
× ( BR_VALUE + 1 )
f PCLK
- × STEP
--------------baud rate = ---------------------------------------------------------------------------------BRPRE
256
16 × 2
× ( BR_VALUE + 1 )
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 29 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 29
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor
(2BRPRE)
Reload Value
(BR_VALUE + 1)
Deviation Error
19.2 kBaud
1 (BRPRE=000B)
78 (4EH)
0.17 %
9600 Baud
1 (BRPRE=000B)
156 (9CH)
0.17 %
4800 Baud
2 (BRPRE=001B)
156 (9CH)
0.17 %
2400 Baud
4 (BRPRE=010B)
156 (9CH)
0.17 %
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 30 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
Prelimary
76
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XC886/888CLM
Functional Description
Table 30
fPCLK
Deviation Error for UART with Fractional Divider enabled
STEP
Prescaling Factor Reload Value
(BR_VALUE + 1)
(2BRPRE)
Deviation
Error
24 MHz
1
10 (AH)
197 (C5H)
+0.20 %
12 MHz
1
6 (6H)
236 (ECH)
+0.03 %
6.67 MHz
1
3 (3H)
236 (ECH)
+0.03 %
Data Sheet
Prelimary
77
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XC886/888CLM
Functional Description
3.11.2
Baud Rate Generation using Timer 1
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
[3.1]
SMOD
2
× f PCLK
Mode 1, 3 baud rate = ---------------------------------------------------32 × 2 × ( 256 – TH1 )
3.12
Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 31). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP.
The output frequency in normal divider mode is derived as follows:
[3.2]
f MOD
Data Sheet
Prelimary
1
= f DIV × -----------------------------256 – STEP
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Functional Description
3.13
LIN Protocol
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. This option is not available with UART1 module.
The LIN baud rate detection feature provides the capability to detect the baud rate within
LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud
rate for data transmission and reception.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 32. The frame consists of the:
•
•
•
•
header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field
response time
data bytes (according to UART protocol)
checksum
Frame slot
Frame
Header
Synch
Figure 32
3.13.1
Response
space
Protected
identifier
Interframe
space
Response
Data 1
Data 2
Data N
Checksum
Structure of LIN Frame
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
Data Sheet
Prelimary
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V0.1, 2006-02
XC886/888CLM
Functional Description
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet
Prelimary
80
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Functional Description
3.14
High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data Sheet
Prelimary
81
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XC886/888CLM
Functional Description
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 33 shows the block diagram of the SSC.
PCLK
Baud-rate
Generator
SS_CLK
MS_CLK
Clock
Control
Shift
Clock
RIR
SSC Control Block
Register CON
Status
Receive Int. Request
TIR
Transmit Int. Request
EIR
Error Int. Request
Control
TXD(Master)
Pin
Control
16-Bit Shift
Register
RXD(Slave)
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 33
Data Sheet
Prelimary
SSC Block Diagram
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Functional Description
3.15
Timer 0 and Timer 1
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
Timer 0 and 1 are fully compatible and can be configured in four different operating
modes for use in a variety of applications, see Table 31. In modes 0, 1 and 2, the two
timers operate independently, but in mode 3, their functions are specialized.
Table 31
Timer 0 and Timer 1 Modes
Mode
Operation
0
13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
1
16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
2
8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
3
Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet
Prelimary
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Functional Description
3.16
Timer 2 and Timer 21
Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible
and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel
capture mode. As a timer, the timers count with an input clock of PCLK/12 (if prescaler
is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode,
the maximum resolution for the count is PCLK/24 (if prescaler is disabled).
Table 32
Timer 2 Modes
Mode
Description
Auto-reload Up/Down Count Disabled
• Count up only
• Start counting from 16-bit reload value, overflow at FFFFH
• Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up
– Start counting from 16-bit reload value, overflow at FFFFH
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
• Count down
– Start counting from FFFFH, underflow at value defined in register
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFFH
Channel
capture
Data Sheet
Prelimary
•
•
•
•
•
•
•
Count up only
Start counting from 0000H, overflow at FFFFH
Reload event triggered by overflow condition
Reload value fixed at 0000H
Capture event triggered by falling/rising edge at pin T2EX
Captured timer value stored in register RC2
Interrupt is generated with reload or capture event
84
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Functional Description
3.17
Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features:
• Three capture/compare channels, each channel can be used either as a capture or as
a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features:
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock frequency
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Supports single-shot mode
Additional Features:
•
•
•
•
•
•
•
Implements block commutation for Brushless DC-drives
Position detection via Hall-sensor pattern
Automatic rotational speed measurement for block commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
Data Sheet
Prelimary
85
V0.1, 2006-02
XC886/888CLM
Functional Description
The block diagram of the CCU6 module is shown in Figure 34.
module kernel
channel 1
1
channel 2
1
deadtime
control
compare
channel 3
compare
capture
T13
compare
start
multichannel
control
trap
control
trap input
clock
control
1
output select
T12
channel 0
Hall input
address
decoder
output select
compare
compare
interrupt
control
1
2
3
2
2
3
1
CTRAP
CCPOS2
CCPOS1
CCPOS0
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
T13HR
T12HR
input / output control
port control
CCU6_block_diagram
Figure 34
Data Sheet
Prelimary
CCU6 Block Diagram
86
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XC886/888CLM
Functional Description
3.18
Analog-to-Digital Converter
The XC886/888 includes a high-performance 10-bit Analog-to-Digital Converter (ADC)
with eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at Port 2.
Features:
• Successive approximation
• 8-bit or 10-bit resolution
(TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access
(wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter
(accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
Data Sheet
Prelimary
87
V0.1, 2006-02
XC886/888CLM
Functional Description
3.18.1
ADC Clocking Scheme
A common module clock fADC generates the various clock signals used by the analog
and digital parts of the ADC module:
• fADCA is input clock for the analog part.
• fADCI is internal clock for the analog part (defines the time base for conversion length
and the sample time). This clock is generated internally in the analog part, based on
the input clock fADCA to generate a correct duty cycle for the analog components.
• fADCD is input clock for the digital part.
The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz.
Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI
does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register
GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of
the ADC is not required.
fADCD
fADC = fPCLK
arbiter
registers
interrupts
digital part
fADCA
CTC
÷ 32
f ADCI
÷4
MUX
÷3
÷2
clock prescaler
analog
components
analog part
Condition: f ADCI ≤ 10 MHz, where t ADCI =
Figure 35
Data Sheet
Prelimary
1
fADCI
ADC Clocking Scheme
88
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XC886/888CLM
Functional Description
For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as
shown in Table 33.
Table 33
fADCI Frequency Selection
Module Clock fADC
CTC
Prescaling Ratio
Analog Clock fADCI
24 MHz
00B
÷2
12 MHz (N.A)
01B
÷3
8 MHz
10B
÷4
6 MHz
11B (default)
÷ 32
750 kHz
As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00B when fADC is
24 MHz. During slow-down mode where fADC may be reduced to 12 MHz, 6 MHz etc.,
CTC can be set to 00B as long as the divided analog clock fADCI does not exceed
10 MHz. However, it is important to note that the conversion error could increase due to
loss of charges on the capacitors, if fADC becomes too low during slow-down mode.
3.18.2
ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
•
•
•
•
Synchronization phase (tSYN)
Sample phase (tS)
Conversion phase
Write result phase (tWR)
conversion start
trigger
Source
interrupt
Sample Phase
Channel
interrupt
Result
interrupt
Conversion Phase
fADCI
BUSY Bit
SAMPLE Bit
tSYN
tS
Write Result Phase
tCONV
Figure 36
Data Sheet
Prelimary
tWR
ADC Conversion Timing
89
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XC886/888CLM
Functional Description
3.19
On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
•
•
•
•
use the built-in debug functionality of the XC800 Core
add a minimum of hardware overhead
provide support for most of the operations by a Monitor Program
use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and on address range within the Program
Memory
• Set breakpoints on internal RAM address range
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks via JTAG and upon activating a dedicated pin
• Step through the program code
The OCDS functional blocks are shown in Figure 37. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals.
After processing memory address and control signals from the core, the MMC provides
proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and
a Monitor RAM (for work-data and Monitor-stack).
The OCDS system is accessed through the JTAG1), which is an interface dedicated
exclusively for testing and debugging activities and is not normally used in an
application. The dedicated MBC pin is used for external configuration and debugging
control.
Note: All the debug functionality described here can normally be used only after XC886/
888 has been started in OCDS mode.
1)
The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports
(Ports 1 and 2/Port 5).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet
Prelimary
90
V0.1, 2006-02
XC886/888CLM
Functional Description
JTAG Module
Debug
Interface
TMS
TCK
TDI
TDO
JTAG
Memory
Control
Unit
TCK
TDI
TDO
Control
User
Program
Memory
Boot/
Monitor
ROM
User
Internal
RAM
Monitor
RAM
Reset
Monitor Mode Control
MBC
Monitor &
Bootstrap loader
Control line
Suspend
Control
System
Control
Unit
Reset
Clock
- parts of
OCDS
Reset Clock Debug PROG PROG Memory
Interface & IRAM Data Control
Addresses
XC800 Core
OCDS_XC886C-Block_Diagram-UM-v0.2
Figure 37
3.19.1
OCDS Block Diagram
JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is
also true immediately after reset.
The JTAG ID register contents for the XC886/888 Flash devices are given in Table 34.
Table 34
JTAG ID Summary
Device Type
Device Name
JTAG ID
Flash
XC886/888*-8FF
1012 0083H
XC886/888*-6FF
1012 5083H
Note: The asterisk (*) above denotes all possible device configurations.
Data Sheet
Prelimary
91
V0.1, 2006-02
XC886/888CLM
Functional Description
3.20
Identification Register
The XC886/888 identity register is located at Page 1 of address B3H.
ID
Identity Register
7
Reset Value: 0000 1001B
6
5
4
3
1
PRODID
VERID
r
r
Field
Bits
Type Description
VERID
[2:0]
r
Version ID
001B
PRODID
[7:3]
r
Product ID
00001B
Data Sheet
Prelimary
2
92
0
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4
Electrical Parameters
4.1
General Parameters
4.1.1
Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC886/
888 and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
• CC
These parameters indicate Controller Characteristics, which are distinctive features of
the XC886/888 and must be regarded for a system design.
• SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC886/888 designed in.
Data Sheet
Prelimary
93
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XC886/888CLM
Electrical Parameters
4.1.2
Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC886/888 can be subjected to
without permanent damage.
Parameter
y
Absolute Maximum Rating Parameters
Symbol
TA
Storage temperature
TST
TJ
Junction temperature
Voltage on power supply pin with VDDP
respect to VSS
Input current on any pin during
IIN
overload condition
min.
max.
125
°C
-65
150
°C
-40
150
°C
-0.5
6
V
-10
10
mA
–
tbd
mA
under bias
under bias
m
Absolute sum of all input currents Σ|IIN|
during overload condition
Unit Notes
-40
in
Ambient temperature
Limit Values
ar
Table 35
P
re
li
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS)
the voltage on VDDP pin with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
Prelimary
94
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.1.3
Operating Conditions
Operating Condition Parameters
Parameter
Symbol
Digital power supply voltage
VDDP
Digital ground voltage
VSS
VDDC
fSYS
TA
min.
Limit Values
max.
Unit Notes/
Conditions
4.5
5.5
V
5V range
3.6
V
3.3V range
3.0
System Clock Frequency1)
V
2.3
2.7
V
88.8
103.2
MHz
-40
85
°C
SAF-XC886/
888...
-40
125
°C
SAK-XC886/
888...
fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 4. Please refer to Figure 27
for detailed description.
P
re
li
1)
m
Ambient temperature
0
in
Digital core supply voltage
ar
Table 36
y
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC886/888. All parameters mentioned in the following table refer to
these operating conditions, unless otherwise noted.
Data Sheet
Prelimary
95
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.2
DC Parameters
4.2.1
Input/Output Characteristics
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
VDDP = 5V Range
VOL CC
Output low voltage
–
–
VOH CC
Output high voltage
Unit Test Conditions
max.
ar
min.
y
Table 37
V
IOL = 15 mA
IOL = 5 mA
IOH = -15 mA
V
IOH = -5 mA
V
CMOS Mode
V
CMOS Mode
–
V
CMOS Mode
VDDP
V
CMOS Mode
V
CMOS Mode
VIH,min
VIL,max
VIL,max
VIH,min
0 < VIN < VDDP,
1.0
V
0.4
V
VDDP - –
in
1.0
VDDP - –
0.4
0.3 ×
–
VDDP
m
Input low voltage on
VILP SR
port pins
(all except P0.0 & P0.1)
VILP0 SR
Input low voltage on
P0.0 & P0.1
li
Input high voltage on
VIHP SR
port pins
(all except P0.0 & P0.1)
VIHP0 SR
Input Hysteresis1)
HYS CC
re
Input high voltage on
P0.0 & P0.1
0.3 ×
-0.2
VDDP
0.7 ×
VDDP
0.7 ×
VDDP
0.08 × –
VDDP
IPU
SR
–
-10
µA
-150
–
µA
Pull-down current
IPD
SR
–
10
µA
150
–
µA
Input leakage current2)
IOZ1 CC
-1
1
µA
P
Pull-up current
Overload current on any IOV
pin
Absolute sum of
overload currents
Data Sheet
Prelimary
TA ≤ 125°C
SR -5
Σ|IOV|
–
5
mA
tbd
mA
3)
SR
96
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Input/Output Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min.
max.
–
1.0
V
–
0.4
V
VDDP = 3.3V Range
VOH CC
Output high voltage
V
IOL = 8 mA
IOL = 2.5 mA
IOH = -8 mA
V
IOH = -2.5 mA
V
CMOS Mode
V
CMOS Mode
–
V
CMOS Mode
VDDP
V
CMOS Mode
V
CMOS Mode
VIH,min
VIL,max
VIL,max
VIH,min
0 < VIN < VDDP,
ar
VOL CC
Output low voltage
VDDP - –
1.0
VDDP - –
0.4
VILP0 SR
Input low voltage on
P0.0 & P0.1
HYS CC
IPU
re
Pull-up current
SR
IPD
Input leakage current2)
IOZ1 CC
P
Pull-down current
Overload current on any IOV
pin
Absolute sum of
overload currents
0.3 ×
-0.2
0.7 ×
m
VIHP0 SR
li
Input Hysteresis1)
VDDP
VDDP
Input high voltage on
VIHP SR
port pins
(all except P0.0 & P0.1)
Input high voltage on
P0.0 & P0.1
0.3 ×
–
in
Input low voltage on
VILP SR
port pins
(all except P0.0 & P0.1)
Unit Test Conditions
y
Table 37
SR
VDDP
0.7 ×
VDDP
0.03 × –
VDDP
–
-5
µA
-50
–
µA
–
5
µA
50
–
µA
-1
1
µA
TA ≤ 125°C
SR -5
Σ|IOV|
–
5
mA
tbd
mA
3)
SR
1)
Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching
due to external system noise.
2)
An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and
RESET pin have internal pull devices and are not included in the input leakage current characteristic.
Data Sheet
Prelimary
97
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Not subjected to production test, verified by design/characterization.
4.2.2
Supply Threshold Characteristics
y
3)
5.0V
ar
VDDP
VDDPPW
2.5V
VDDCPW
VDDCBO
in
VDDC
VDDCPOR
VDDCRDR
VDDCBOPD
Supply Threshold Parameters
Table 38
Supply Threshold Parameters (Operating Conditions apply)
m
Figure 38
VDDC prewarning
Symbol
li
Parameters
voltage1)
Limit Values
min.
typ.
max.
Unit
CC 2.2
2.3
2.4
V
VDDCBO
CC 2.0
2.1
2.2
V
RAM data retention voltage
VDDCRDR CC 0.9
1.0
1.1
V
VDDC brownout voltage in
power-down mode2)
VDDCBOPD CC 1.3
1.5
1.7
V
VDDP prewarning voltage3)
VDDPPW
CC 3.4
4.0
4.6
V
VDDCPOR CC 1.3
1.5
1.7
V
P
re
VDDCPW
VDDC brownout voltage in
active mode1)
Power-on reset voltage2)4)
1)
Detection is disabled in power-down mode.
2)
Detection is enabled in both active and power-down mode.
3)
Detection is enabled for external power supply of 5.0V.
Detection must be disabled for external power supply of 3.3V.
4)
The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
Data Sheet
Prelimary
98
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XC886/888CLM
Electrical Parameters
4.2.3
ADC Characteristics
y
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (VSS) must be
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Parameter
Symbol
ar
ADC Characteristics (Operating Conditions apply; VDDP = 5V Range)
Table 39
Limit Values
min.
typ .
Unit
max.
VDDP V
+ 0.05
Analog reference
voltage
VAREF
Analog reference
ground
VAGND
VSS
SR - 0.05
Analog input
voltage range
VAIN SR VAGND –
VAREF V
ADC clocks
fADC
in
VAGND VDDP
SR + 1
VSS
24
25.8
MHz
module clock
–
–
10
MHz
internal analog clock
See Figure 35
CC (2 + INPCR0.STC) ×
tADCI
µs
CC See Section 4.2.3.1
µs
tS
Conversion time
tC
Total unadjusted
error
TUE1)CC
Switched
capacitance at the
reference voltage
input
CAREFSW –
CC
Switched
capacitance at the
analog voltage
inputs
li
Sample time
±1
LSB
8-bit conversion.2)
±2
LSB
10-bit conversion.
20
pF
2)3)
7
pF
2)4)
1
2
kΩ
2)
1
1.5
kΩ
2)
–
–
–
10
–
CAINSW
CC
5
Input resistance of RAREFCC –
the reference input
Input resistance of RAIN CC –
the selected analog
channel
re
–
P
VAREF V
-1
–
m
fADCI
Data Sheet
Prelimary
Test Conditions/
Remarks
99
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
TUE is tested at VAREF = 5.0 V, VAGND = 0 V , VDDP = 5.0 V.
2)
Not subject to production test, verified by design/characterization
3)
This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4)
The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2.
ar
y
1)
Analog Input Circuitry
CEXT
ANx
RAIN, On
C AINSW
m
VAIN
in
REXT
li
VAGNDx
P
re
Reference Voltage Input Circuitry
R AREF, On
VAREFx
VAREF
C AREFSW
VAGNDx
Figure 39
Data Sheet
Prelimary
ADC Input Circuits
100
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.2.3.1
ADC Conversion Timing
Conversion time, tC = tADC × ( 1 + r × (3 + n + STC) ) , where
r = 32 for CTC = 11B,
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
y
r = CTC + 2 for CTC = 00B, 01B or 10B,
P
re
li
m
in
ar
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
tADC = 1 / fADC
Data Sheet
Prelimary
101
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.2.4
Power Supply Current
Table 40
Power Supply Current Parameters (Operating Conditions apply;
Parameter
Symbol
Limit Values
Active Mode
Idle Mode
29
tbd
mA
3)
21.1
tbd
mA
4)
tbd
tbd
mA
5)
in
Active Mode with slow-down
enabled
IDDP
IDDP
IDDP
Unit Test Condition
max.2)
ar
typ.1)
VDDP = 5V Range
y
VDDP = 5V range )
Idle Mode with slow-down
enabled
IDDP
tbd
tbd
mA
6)
Power-Down Mode
IPDP
10
tbd
µA
7)
The typical IDDP values are based on prelimary measurements and are to be used as reference only. These
values are periodically measured at TA = + 25 °C and VDDP = 5.0 V.
2)
The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 5.5 V).
3)
IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by
on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP.
4)
IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP.
5)
IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP.
6)
IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B,
RESET = VDDP.
7)
IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs.
P
re
li
m
1)
Data Sheet
Prelimary
102
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Table 41
Power Supply Current Parameters (Operating Conditions apply;
VDDP = 3.3V range)
Parameter
Symbol
Limit Values
max.
Unit Test Condition
2)
y
typ.1)
VDDP = 3.3V Range
Idle Mode
Active Mode with slow-down
enabled
IDDP
tbd
IPDP
Power-Down Mode
tbd
mA
3)
tbd
tbd
mA
4)
tbd
tbd
mA
5)
tbd
tbd
mA
6)
tbd
µA
7)
in
Idle Mode with slow-down
enabled
IDDP
IDDP
IDDP
ar
Active Mode
tbd
The typical IDDP values are periodically measured at TA = + 25 °C and VDDP = 3.3 V.
2)
The maximum IDDP values are measured under worst case conditions (TA = + 125 °C and VDDP = 3.6 V).
3)
IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz(set by
on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP.
4)
IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
enabled and running at 24 MHz, RESET = VDDP.
5)
IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP.
6)
IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B,,
RESET = VDDP.
7)
IPDP (power-down mode) is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0= VDDP; rest of the ports
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs
P
re
li
m
1)
Data Sheet
Prelimary
103
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3
AC Parameters
4.3.1
Testing Waveforms
ar
y
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 40, Figure 41 and Figure 42.
VDDP
90%
90%
10%
in
10%
VSS
tR
Rise/Fall Time Parameters
m
Figure 40
tF
li
VDDP
VDDE / 2
Figure 41
P
VLoad - 0.1 V
Data Sheet
Prelimary
VDDE / 2
Testing Waveform, Output Delay
VLoad + 0.1 V
Figure 42
Test Points
re
VSS
Timing
Reference
Points
VOH - 0.1 V
VOL - 0.1 V
Testing Waveform, Output High Impedance
104
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Output Rise/Fall Times
Table 42
Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter
Symbol
Limit
Values
min. max.
Rise/fall times 1) 2)
ar
VDDP = 5V Range
tR, tF
–
10
ns
20 pF. 3)
tR, tF
–
10
ns
20 pF. 4)
VDDP = 3.3V Range
Rise/fall times 1) 2)
Unit Test Conditions
y
4.3.2
Rise/Fall time measurements are taken with 10% - 90% of the pad supply.
2)
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3)
Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF.
4)
Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF.
m
in
1)
VDDP
90%
li
90%
10%
10%
VSS
tF
Rise/Fall Times Parameters
P
Figure 43
re
tR
Data Sheet
Prelimary
105
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Power-on Reset and PLL Timing
Table 43
Power-On Reset and PLL Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
min. typ.
On-Chip Oscillator
start-up time
VPAD CC 2.3
–
tOSCST
CC
RESET hold time1)
tFINIT CC –
tRST SR –
–
V
–
500
ns
160
–
µs
500
–
µs
PLL lock-in in time
tLOCK CC –
–
200
µs
PLL accumulated jitter
DP
–
tbd
ns
–
VDDP rise time
(10% – 90%) ≤ 500µs
in
Flash initialization time
–
max.
ar
Pad operating voltage
Unit Test Conditions
y
4.3.3
2)
RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5V).
2)
PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.
P
re
li
m
1)
Data Sheet
Prelimary
106
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
VDDP
ar
y
VPAD
VDDC
tOSCST
in
OSC
PLL unlock
PLL
PLL lock
tLOCK
Reset
tRST
RESET
2)
1)
Ready to Read
3)
li
Pads
1)Pad state undefined 2)ENPS control 3)As Programmed
II)until PLL is locked
III) until Flash go IV) CPU reset is released; Boot
to Ready-to-Read ROM software begin execution
re
I)until EVR is stable
Power-on Reset Timing
P
Figure 4-1
Initialization
tFINIT
m
Flash State
Data Sheet
Prelimary
107
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Table 44
On-Chip Oscillator Characteristics
On-chip Oscillator Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
min. typ. max.
fNOM CC –
9.6
–
Long term frequency
deviation
∆fLT CC -5.0
–
Short term frequency
deviation
∆fST CC -1.0
%
with respect to fNOM
5.0
%
with respect to fNOM, over
lifetime and temperature,
for one given device after
trimming
m
–
%
with respect to fNOM,
within one LIN message
(<10 ms .... 100 ms)
1.0
Nominal condition: VDDC = 2.5 V, TA = + 25°C.
P
re
li
1)
MHz under nominal
conditions1) after
IFX-backend trimming
2.5
in
Chip-to-chip frequency ∆fCC CC -2.5
deviation
–
ar
Nominal frequency
Unit Test Conditions
y
4.3.4
Data Sheet
Prelimary
108
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
4.3.5
JTAG Timing
Table 45
TCK Clock Timing (Operating Conditions apply; CL = 50 pF)
Symbol
tTCK SR
t1 SR
t2 SR
t3 SR
t4 SR
ar
TCK clock period
TCK high time
TCK low time
TCK clock rise time
min
0.5 V DDP
Unit
max
50
−
ns
tbd
−
ns
tbd
−
ns
−
tbd
ns
−
tbd
ns
in
TCK clock fall time
0.9 V DDP
0.1 V DDP
m
TCK
t1
t2
t4
t TCK
t3
li
TCK Clock Timing
P
re
Figure 44
Limits
y
Parameter
Data Sheet
Prelimary
109
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
Table 46
JTAG Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min
TDI hold to TCK
TDO valid output from TCK
TDO high impedance to valid output from TCK
m
TCK
t1
li
TMS
t1
re
TDI
ns
−
ns
SR tbd
−
ns
SR tbd
−
ns
CC −
tbd
ns
CC −
tbd
ns
CC −
tbd
ns
t2
t2
t4
t3
t5
JTAG Timing
P
Figure 45
−
SR tbd
in
TDO valid output to high impedance from TCK
max
SR tbd
ar
TDI setup to TCK
TDO
t1
t2
t1
t2
t3
t4
t5
y
TMS setup to TCK
TMS hold to TCK
Unit
Data Sheet
Prelimary
110
V0.1, 2006-02
XC886/888CLM
Electrical Parameters
SSC Master Mode Timing
Table 47
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
y
4.3.6
min.
MRST setup to SCLK
MRST hold from SCLK
max.
–
ns
CC 0
tbd
ns
SR tbd
–
ns
SR tbd
–
ns
TSSCmin = TCPU = 1/fCPU. When fCPU = 24MHz, t0 = 83.3ns. TCPU is the CPU clock period.
in
1)
CC 2*TSSC
ar
t0
t1
t2
t3
SCLK clock period
MTSR delay from SCLK
1)
Unit
SCLK1)
t1
m
t0
t1
re
MRST1)
li
MTSR1)
t2
t3
Data
valid
t1
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
SSC Master Mode Timing
P
Figure 46
SSC_Tmg1
Data Sheet
Prelimary
111
V0.1, 2006-02
XC886/888CLM
Package and Quality Declaration
Package and Quality Declaration
5.1
Package Outline
PG-TQFP-48-4 Package Outline
P
Figure 47
re
li
m
in
ar
y
5
Data Sheet
Prelimary
112
V0.1, 2006-02
XC886/888CLM
PG-TQFP-64-8 Package Outline
P
re
Figure 48
li
m
in
ar
y
Package and Quality Declaration
Data Sheet
Prelimary
113
V0.1, 2006-02
XC886/888CLM
Package and Quality Declaration
5.2
Quality Declaration
Table 48 shows the characteristics of the quality parameters in the XC886/888.
Quality Parameters
Parameter
Symbol
Limit Values
Unit
Notes
y
Table 48
Max.
–
2000
V
Conforming to
EIA/JESD22A114-B
ESD susceptibility
VCDM
according to Charged
Device Model (CDM) pins
–
500
V
Conforming to
JESD22-C101-C
P
re
li
m
in
ar
Min.
ESD susceptibility
VHBM
according to Human Body
Model (HBM)
Data Sheet
Prelimary
114
V0.1, 2006-02
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