SL339 Quad Single Supply Comparator The SL339 consists of four independent precision voltage comparators with an offset voltage specification as low as 2.0 mV max for four comparators which were designed specifically to operate from a single power supply over a wide range of voltages. Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. • Single or Split Supply Operation • Low Input Bias Current • Low Input Offset Current • Input Common Mode Voltage Range to Gnd • Low Output Saturation Voltage • TTL and CMOS Compatible ORDERING INFORMATION SL339N Plastic SL339D SOIC TA = 0° to 70° C for all packages. LOGIC DIAGRAM PIN ASSIGNMENT PIN 3 = VCC PIN 12 = GND SLS System Logic Semiconductor SL339 MAXIMUM RATINGS * Symbol Value Unit Single Supply Split Supplies 36 ±18 V VIDR Input Differential Voltage Range 36 V VICR Input Common Mode Voltage Range (1) -0.3 to VCC V VCC Parameter Power Supply Voltages ISC Output Short Circuit to Ground IIN Input Current, per pin (2) TJ Junction Temperature Plastic Packages Tstg Storage Temperature Continuous 50 mA 150 °C -65 to +150 °C TL Lead Temperature, 1mm from Case for 10 Seconds 260 °C PD Power Dissipation @TA=25°C Plastic Package Derate above 25°C 1.0 8.0 W mW/°C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Notes: 1. Split Power Supplies. 2. VIN<-0.3V. This input current will only exist when voltage at any of the input leads is driven negative. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage TA Operating Temperature, All Package Types Min Max Unit ±2.5 or 5.0 ±15 or 30 V 0 +70 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL339 DC ELECTRICAL CHARACTERISTICS (TA=0 to +70°C) Guaranteed Limit Symbol Parameter Test Conditions Min Typ Max Unit VIO Input Offset Voltage V0=1.4V VCC=5.0-30V;RS≤100Ω VICR=0V - (VCC-1.5)V - 9.0 mV IIB Input Bias Current V0=1.4V VCC=5.0-30V VICR=0V - (VCC-1.5)V - 400 nA IIO Input Offset Current V0=1.4V VCC=5.0-30V VICR=0V - (VCC-1.5)V - ±150 nA VICR Input Common Mode Voltage Range VCC=5.0-30V 0 VCC-2.0V V ICC Supply Current RL=∞,VCC=5.0 - 2.0* mA RL=∞,VCC=30V - 2.5* Voltage Gain VCC=15V, RL=15KΩ - 200* - V/mV t1 Large Signal Response Time VIN=TTL Logic Swing, Vref=1.4V, VCC=5.0V, RL=5.1KΩ, VRL=5.0V - 300* - ns t2 Response Time VCC=5.0V, RL=5.1KΩ, VRL=5.0V - 1.3* - µs Isink Output Sink Current VI(-)=1.0V, VI(+)=0V, V0≤1.5V, VCC=5.0V 6.0* - - mA Vsat Saturation Voltage VI(-)=1.0V, VI(+)=0V, Isink≤4.0mA, VCC=5.0V - - 700 mV IOL Output Leakage Current VI(+)=1.0V, VI(-)=0V, V0=5.0V V0=30V A VOL nA 0.1* 1000 VIDR Differential Input Voltage Range *=@25°C System Logic SLS Semiconductor All VIN≥GND or V-Supply (if used) VCC* V SL339 TYPICAL PERFORMANCE CHARACTERISTICS (VCC=1.5V, TA=+25°C, (each comporator)) Figure 1. Normalized Input Offset Voltage Figure 2. Input Bias Current Figure 3. Output Sink Current versus Output Saturation Voltage SLS System Logic Semiconductor