SUMMIT SMP9317 MICROELECTRONICS, Inc. Nonvolatile DACPOT™ Electronic Potentiometer With Up/Down Counter Interface FEATURES • Digitally Controlled Electronic Potentiometer OVERVIEW • 7-Bit Digital-to-Analog Converter (DAC) – Independent Reference Inputs – Differential Non-Linearity - +0.5LSB – Integral Non-Linearity - +1LSB • VOUT Value in EEPROM for Power-On Recall – Equivalent to 128-Step Potentiometer • Unity Gain Op Amp Drives ±100µA The SMP9317 DACPOT™ trimmer is a 7-bit nonvolatile DAC designed to replace mechanical potentiometers. The SMP9317 includes a unity-gain amplifier to buffer the DAC output and enables VOUT to swing from rail to rail. The DACPOT trimmer operates over a supply voltage range of 2.7V to 5.5V. The SMP9317’s simple up/down counter input provides an ideal interface for automatic test equipment to dither and monitor the VOUT voltage. This interface allows for quick and consistent calibration of even the most sophisticated systems. • Simple Trimming Adjustment – Up/Down Counter Style Operation • Low Noise Operation • “Clickless” Transitions between DAC Steps The SMP9317 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. The SMP9317 offers higher resolution than these devices and provides ‘clickless’ transitions of VOUT. • No Mechanical Wearout Problem – 1,000,000 Stores (typical) – 100 Year Data Retention • Operation from +2.7V to +5.5V Supply • Ultra-Low Power, 0.5mW max at +5V FUNCTIONAL BLOCK DIAGRAM VDD VH 7-bit E2 PROM - UP/DN INC CS Counter & Write Control AMP 7-bit Data Register 7-bit DAC VOUT + VL GND 2031 ILL2.0 SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 © SUMMIT MICROELECTRONICS, Inc. 1998 2031-04 12/4/98 • Campbell, CA 95008 1 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice SMP9317 PIN NAMES Symbol INC UP/DN VH PINOUT Description Increment Input, High to Low Edge Trigger Up/Down Input controlling relative VOUT movement V+ reference input GND Analog and Digital Ground VOUT Trimmed Voltage Output VL V- reference input CS Active low chip select input VDD Supply Voltage (2.7V to 5.5V) INC 1 8 VDD UP/DN 2 7 CS VH 3 6 VL GND 4 5 VOUT 2031 ILL1.0 INC Increment (INC INC) is an edge triggered input. Whenever CS is low and a high to low transition occurs on the INC input, the VOUT voltage will either move toward VH or VL depending upon the state of the UP/DN input. Analog Section The SMP9317 is a 7-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts a 7-bit value into equivalent analog output voltages in proportion to the applied reference voltage. DN UP/Down (UP/DN DN) is an input that will determine the VOUT movement relative to VH and VL. When CS is low, UP/DN is high and there is a high to low transition on INC, the VOUT voltage will move (1/128th x VH-VL) toward VH. When CS and UP/DN are low, and there is a high to low transition on INC, the VOUT will move (1/128th x VH-VL) toward VL. Reference Inputs The voltage differential between the VL and VH inputs sets the full-scale output voltage range. VL must be equal to or greater than ground (i.e. a positive voltage). VH must be greater than VL and less than or equal to VDD. See table on page 3 for guaranteed operating limits. Power–Up/Power–Down Conditions On power–up the SMP9317 loads the value of EEPROM memory into the wiper position register. The value in the register is changed using the CS, INC, and UP/DN pins. The new data in the register will be lost at power-down unless CS was brought high, with INC high, to initiate a store operation after the last increment or decrement. On the next device power–up, the value of EEPROM memory will be loaded into the wiper position register. During power-up the SMP9317 is write-protected in two ways: Output Buffer Amplifier The voltage output is from a precision unity-gain follower that can slew up to 1V/µs. Digital Interface The interface is designed to emulate a simple up/down counter, but instead of a parallel count output, a ratiometric voltage output is provided. 1) A power-on reset, that trips at approximately 2.5V, holds CS and INC high internally. CS Chip Select (CS CS) is an active low input. Whenever CS is high the SMP9317 is in standby mode and consumes the least power. This mode is equivalent to a potentiometer that is adjusted to the required setting. When CS is low the SMP9317 will recognize transitions on the INC input and will move the VOUT either toward the VH reference or toward the VL reference depending upon the state of the UP/DN input. 2) Resistor pull-ups on all logic inputs prevent data change if the inputs are floating. Data Retention The SMP9317 is guaranteed to perform at least 1,000,000 writes to EEPROM before a wear–out condition can occur. After EEPROM wearout, the SMP9317 continues to function as a volatile digital-potentiometer. The wiper position can be changed during powered conditions using the digital interface. However, on power– up the wiper–position will be indeterminate. The host may exit an adjustment routine in two ways: deselecting the SMP9317 while INC is low will not perform a store operation (a subsequent power cycle will recall the original data); deselecting the SMP9317 while INC is high will store the current VOUT setting into nonvolatile memory. On shipment from the factory, Summit Microelectronics does not specify any EEPROM memory value. The value must be set by the customer as needed. 2031-04 12/4/98 2 SMP9317 *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Storage Temperature Voltage on pins with reference to GND: Analog Inputs Digital Inputs Analog Outputs Digital Outputs Lead Solder Temperature (10 secs) -55°C to +125°C -65°C to +150°C -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V 300°C RECOMMENDED OPERATING CONDITIONS Condition Min Max Temperature -40°C +85°C VDD +2.7V +5.5V 2031 PGM T1.0 DAC DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40°C to +85°C, unless specified otherwise Accuracy Symbol Parameter Conditions INL Integral Non-Linearity ILOAD = 50µA, DNL Differential Non-Linearity Min. Typ. Max. Units TR = C TR = I - 0.6 0.6 ±1 ±1 LSB LSB ILOAD = 100µA, TR =C TR = I - 1.2 1.2 - LSB LSB ILOAD = 50µA, TR = C TR = I - 0.25 0.25 ±0.5 ±0.5 LSB LSB ILOAD = 100µA, TR = C TR = I - 0.5 0.5 - LSB LSB 2.5 - VDD V Gnd - VDD-2.5 V - 38K - Ω References VH VrefH Input Voltage VL VrefL Input Voltage RIN VrefH to VrefL Resistance TCRIN Temperature Coefficient of RIN VrefH to VrefL - 700 - ppm/°C Analog GEFS Full-Scale Gain Error DATA = 7F - - ±1 LSB Output VOUTZS Zero-Scale Output Voltage DATA = 00 0 20 mV TCVOUT VOUT Temperature Coefficient, note 3 - 200 µV/°C 100 µA VH ≥ VL VDD = +5, ILOAD = 50µA, VrefH = +5V, VrefL = 0V IL Amplifier Output Load Current ROUT Amplifier Output Resistance IL = 100µA PSRR Power Supply Rejection eN +5V +3V - Ω Ω - 10 20 ILOAD = 10µA - - 1 Amplifier Output Noise f = 1KHz, VDD = +5V - 90 - THD Total Harmonic Distortion VIN = 1V rms, f = 1KHz - 0.08 - BW Bandwidth - 3dB VIN = 100mV rms - 1,000 - LSB/V nV/ HZ % kHz 2031 PGM T3.2 2031-04 12/4/98 3 SMP9317 RELIABILITY CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Min VZAP ESD Susceptibility ILTH Max Unit Test Method 2000 V MS-883, TM 3015 Latch-Up 100 mA JEDEC Standard 17 TDR Data Retention 100 Years MS-883, TM 1008 NEND Endurance 1,000,000 Stores MS-883, TM 1033 2031 PGM T2.0 DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, TA = -40°C to +85°C, Unless otherwise specified Symbol Parameter Conditions IDD Supply Current during store, note 1 CS = VIL to VIH W/INC HI ISB Supply Standby Current CS = VIH 100 µA IIH Input Leakage Current VIN = VDD 10 µA IIL Input Leakage Current, note 2 VIN = 0V -25 µA VIH High Level Input Voltage 2 VDD V VIL Low Level Input Voltage 0 0.8 VDD ≥ 4.5V Min Typ Max Units 1.0 mA V 2031 PGM T4.1 Notes: 1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference resistor chain. 2. CS, UP/DN and INC have internal pull-up resistors of approximately 200kΩ. When the input is pulled to ground the resulting output current will be VDD/200kΩ. 3. TCVOUT is guaranteed but not tested. 2031-04 12/4/98 4 SMP9317 OPERATIONAL TRUTH TABLE INC CS UP/DN DN Operation HITOLO L H VOUT toward VH HITOLO L L VOUT toward VL H LOTOHI X Store Setting L LOTOHI X Maintain Setting, NO Store X H X Standby, note 1 2031 PGM T5.1 Notes: 1. The Standby or operating current will be lowest with INC and UP/DN pins at H as there are weak internal pull-ups that draw current when connected LO. AC TIMING CHARACTERISTICS Symbol Parameter Min Max Units tCLIL CS to INC Setup 100 ns tIHDC INC High to UP/DN Change 100 ns tDCIL UP/DN to INC Setup 100 ns tIL INC Low Period 200 ns tIH INC High Period 200 ns tIHCH INC Inactive to CS Inactive 100 ns tWP Write Cycle Time 5 ms tILVOUT INC to VOUT Delay 5 µs 2031 PGM T6.0 CS tCLIL tIL tIH tIHCH tWP INC tIHDC tDCIL UP/DN tILVOUT VOUT 2031 ILL3.1 AC TIMING DIAGRAM 2031-04 12/4/98 5 SMP9317 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. .030 (.762) TYP. 8 Places 1 .196 (5.00) .189 (4.80) FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0098 (.25) .004 (.127) .05 (1.27) TYP. .0192 (.49) .0138 (.35) .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 ORDERING INFORMATION SMP9317 S Package S = 8 Pin SOIC Base Part Number 2031 ILL4.0 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 1998 SUMMIT Microelectronics, Inc. 2031-04 12/4/98 6