SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062B – NOVEMBER 1988 – REVISED MAY 1997 D D SN54HCT00 . . . J OR W PACKAGE SN74HCT00 . . . D, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1A 1B 1Y 2A 2B 2Y GND description These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A • B or Y = A + B in positive logic. H H L L X H X L H 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A OUTPUT Y B 13 1B 1A NC VCC 4B 1Y NC 2A NC 2B FUNCTION TABLE (each gate) A 14 2 SN54HCT00 . . . FK PACKAGE (TOP VIEW) The SN54HCT00 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HCT00 is characterized for operation from –40°C to 85°C. INPUTS 1 NC – No internal connection logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 & 2 3 1Y 4 6 5 2Y 9 8 10 3Y 12 11 13 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages. logic diagram (positive logic) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062B – NOVEMBER 1988 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HCT00 VCC VIH Supply voltage VIL VI Low-level input voltage VO tt TAz Operating free-air temperature High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V SN74HCT00 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 UNIT V V 0 0.8 0 0.8 V Input voltage 0 0 VCC VCC V 0 VCC VCC 0 Output voltage Input transition (rise and fall) time 0 500 0 500 ns –55 125 –40 85 °C V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = –20 µA IOH = –4 mA 45V 4.5 VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 45V 4.5 II ICC VI = VCC or 0 VI = VCC or 0, ∆ICC‡ 5.5 V IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC Ci MIN TA = 25°C TYP MAX 4.5 V to 5.5 V MIN MAX SN74HCT00 MIN 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MAX V 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±0.1 ±100 ±1000 ±1000 nA 2 40 20 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 POST OFFICE BOX 655303 UNIT 0.001 5.5 V 5.5 V SN54HCT00 • DALLAS, TEXAS 75265 V SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS062B – NOVEMBER 1988 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd d A or B Y tt Y VCC MIN TA = 25°C TYP MAX SN54HCT00 MIN SN74HCT00 MAX MIN MAX 4.5 V 11 20 30 25 5.5 V 10 18 27 22 4.5 V 9 15 22 19 5.5 V 8 14 20 17 UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate No load TYP UNIT 20 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test 3V Test Point Input 1.3 V 1.3 V 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 1.3 V 10% tPHL 90% 90% tr Input 1.3 V 0.3 V 2.7 V 2.7 V tr tPHL 3V 1.3 V 0.3 V 0 V Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOH 1.3 V 10% V OL tf tPLH 1.3 V 10% tf 1.3 V 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated