54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC t (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54ACT11010 . . . J PACKAGE 74ACT11010 . . . D OR N PACKAGE (TOP VIEW) 1A 1Y 2Y GND GND 3Y 3C 3B 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1B 1C 2A VCC VCC 2B 2C 3A 54ACT11010 . . . FK PACKAGE (TOP VIEW) description 2A VCC NC VCC 2B • • These devices contain three independent 3-input NAND gates. They perform the Boolean functions Y = ASBSC or Y = A + B + C in positive logic. The 54ACT11010 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11010 is characterized for operation from – 40°C to 85°C. 1C 1B NC 1A 1Y 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2C 3A NC 3B 3C FUNCTION TABLE A B C OUTPUT Y H H H L L X X H X L X H X X L H 2Y GND NC GND 3Y (each gate) INPUTS NC – No internal connection logic diagram (positive logic) logic symbol† 1A 1B 1C 2A 2B 2C 3A 3B 3C 1 & 16 2 15 1Y 14 11 3 10 1A 1B 1C 1 16 15 2 2A 2B 2C 14 11 10 3 3A 3B 3C 9 8 7 6 1Y 2Y 3Y 2Y 9 8 6 7 3Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions 54ACT11010 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL Dt /Dv Low-level output current TA Operating free-air temperature High-level input voltage 74ACT11010 2 2 0.8 Input transition rise or fall rate UNIT V V 0.8 V VCC VCC V – 24 – 24 mA 24 24 mA VCC VCC 0 0 V 0 10 0 10 ns / V – 55 125 – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 4.5 V IOH = – 50 mA VOH VOL VCC IOH = – 24 mA TA = 25°C MIN TYP MAX 54ACT11010 74ACT11010 MIN MIN MAX 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 IOH = – 50 mA‡ IOH = – 75 mA‡ 5.5 V IOL = 50 mA 4.5 V IOL = 50 mA‡ IOL = 75 mA‡ V 3.85 0.1 0.1 5.5 V 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 5.5 V 0.1 V 1.65 5.5 V 1.65 II ICC VI = VCC or GND VI = VCC or GND, 5.5 V ± 0.1 ±1 ±1 IO = 0 5.5 V 4 80 40 mA mA DICC§ One input at 3.4 V,, Other inputs at GND or VCC 55V 5.5 09 0.9 1 1 mA Ci VI = VCC or GND 5V 3.5 ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. 2–2 UNIT 3.85 5.5 V IOL = 24 mA MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993 switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Y MIN TA = 25°C TYP MAX 54ACT11010 74ACT11010 MIN MAX MIN MAX 1.5 5.8 8.2 1.5 9.3 1.5 8.9 1.5 5.7 7.4 1.5 8.7 1.5 8.2 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz TYP UNIT 27 pF PARAMETER MEASUREMENT INFORMATION 3V Input (see Note B) From Output Under Test CL = 50 pF (see Note A) 1.5 V 1.5 V 0V tPHL 500 Ω tPLH 50% VCC Output VOH 50% VCC VOL VOLTAGE WAVEFORMS LOAD CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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